The Development of The Development of Psec-Resolution Psec-Resolution TDC for Large Area TDC for Large Area TOF Systems TOF Systems Fukun Tang Fukun Tang Enrico Fermi Institute Enrico Fermi Institute University of Chicago University of Chicago With Karen Byrum and Gary Drake (ANL) Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David
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The Development of Psec-Resolution TDC for Large Area TOF Systems Fukun Tang Enrico Fermi Institute University of Chicago With Karen Byrum and Gary Drake.
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The Development The Development of Psec-Resolution of Psec-Resolution TDC for Large Area TDC for Large Area
TOF SystemsTOF SystemsFukun TangFukun Tang
Enrico Fermi InstituteEnrico Fermi Institute
University of ChicagoUniversity of Chicago
With Karen Byrum and Gary Drake (ANL)
Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC)
Major advances for TOF Major advances for TOF measurements:measurements:
Ability to simulate electronics and Ability to simulate electronics and systemssystems
to predict design performanceto predict design performance
Output at anode from simulation of 10 particles going through fused quartz window- T. Credo, R. Schroll
Time Stretcher:Time Stretcher: Simulation ResultSimulation Result
1ns Time Interval (Input Signal)
Stretched Time = 274ns
(pedestal=74ns)
x200 Stretched Time Interval (Output Signal )
0 50ns 100ns 150ns 200ns 250ns 300ns
Ultimate Goal:Ultimate Goal: To build TDC with 1 pSec Resolution for Large Scale of To build TDC with 1 pSec Resolution for Large Scale of
Time-of-Flight Detector.Time-of-Flight Detector.Primary Goal:Primary Goal: To build 2-Ghz VCO, key module of PLL that generates the To build 2-Ghz VCO, key module of PLL that generates the
To evaluate IHP SG25H1/M4M5 Technology for our To evaluate IHP SG25H1/M4M5 Technology for our applicationsapplications
To gain experiences on using Cadence tools To gain experiences on using Cadence tools (Virtuoso (Virtuoso Analog Environment)Analog Environment) Circuit DesignCircuit Design (VSE)(VSE) SimulationSimulation (Spectre)(Spectre) Chip LayoutChip Layout (VLE, XLE, VCAR)(VLE, XLE, VCAR) DRC and LVS Check DRC and LVS Check (Diva, Assura, Calibre)(Diva, Assura, Calibre) Parasitic ExtractionParasitic Extraction (Diva)(Diva) Post Layout SimulationPost Layout Simulation (Spectre)(Spectre) GDSIIGDSII Stream outStream out ValidationValidation Tape OutTape Out
VCO: Submission of Oct. VCO: Submission of Oct. 20062006
1N
Diagram of Phase-Diagram of Phase-Locked LoopLocked Loop
Diagram of Post Layout Diagram of Post Layout SimulationSimulation
Schematic
Analog_extracted
Transit Analysis: Comparison of Transit Analysis: Comparison of Schematic and Post Layout Schematic and Post Layout
SimulationsSimulations
Schematic
Post Layout
Outputs@50 loads
V-F Plot: Comparison of Schematic V-F Plot: Comparison of Schematic and Post Layout Simulationsand Post Layout Simulations
Post Layout
Schematic
Vcontrol
Frequency
Phase Noise: Post Layout SimulationsPhase Noise: Post Layout SimulationsVDD=2.5V Temp.=27C, 55CVDD=2.5V Temp.=27C, 55C
Phase Noise @100KHZ offset
27C27C -89.40 -89.40 dBc/HzdBc/Hz
(Sch: -89.75)(Sch: -89.75)
55C55C -88.90 -88.90 dBc/HzdBc/Hz
(Sch: -89.15)(Sch: -89.15)
ConclusionConclusion
(1) VCO time-jitter met our (1) VCO time-jitter met our requirement.requirement.
(2) Post layout simulation matched (2) Post layout simulation matched schematic simulation very well.schematic simulation very well.
(3) Some problems we have (3) Some problems we have encountered with pcell library, encountered with pcell library, layout, DRC, LVS and auto-routing layout, DRC, LVS and auto-routing functionalities.functionalities.
(4)(4) Ready for October Submission.Ready for October Submission.