The Delay blocks

The Delay blocks- Coarse_fineDelay_macro

- fineDelay_macro- halfFineDelay_macro

- Fdelay_macroThe first three blocks by Amogh Halgeri, the last block by Aditya Narayan

Coarse_FineDelay_macro• Four flip-flops to generate the coarse delay and fifteen delay blocks

(each consisting of two DELAY_C’ elements) to generate fine delay

• Coarse delay is a multiple of the clock cycle period, and fine delay is multiple of propagation time through delay blocks

• Two input bits to select Coarse delay (sel_CoarseFineDelay [1:0]) among the four possible delays • Four bit input to select the fine delay (sel_fineDelay [3:0]) among the sixteen possible delays• The select bits are decoded using combinational logic to decide what delay is to be introduced

Spectre simulation of the extracted layout– slow process ; temperature - 500 celcius• The minimum coarse delay – half a clock cycle. Clock is inverted to make it out of

phase with incoming data signal. Thus the design is more robust (no race condition when data changes duty cycle from 35% to 65%, clk at 320 MHz, data at 40MHz)• The minimum fine delay – zero (Not passing through any of the delay blocks),

delay through each DELAY_C element – 600 to 800 ps.

Spectre simulation –

Slow process and temperature of 500 celcius

Fine delay control Total fine delay Delay2 – Delay1 – half clk. cycle period (delay through each element)

0000 2.5532 -

0001 4.4545 1.9103

0010 6.4309 1.9764

0011 8.4427 2.0118

0100 10.3308 1.8881

0101 12.3634 2.0326

0110 14.325 1.9616

0111 16.3258 2.0008

1000 18.3269 2.0011

1001 20.114 1.7851

1010 22.0971 1.9851

1011 24.0032 1.9349

1100 25.91 1.91

1101 27.84 1.93

1110 29.77 1.93

1111 31.824 2.05

• Average delay through a delay block– about 1.9 to 2 ns

• This is the delay through two DELAY_C elements

• Delay due to delay elements, wiring, the AO2222 cells and other combinational logic.

FineDelay_Macro

The 30 delay cells and the decoder as depicted by cadence rtl compiler gui.

• Same as the Coarse_fineDelay_macro block but without the flip-flops, and thus without the clock cycle delay.• Each AO2222 cell basically ‘and’s four pair of inputs and ‘or’s the

‘and’ed outputs. • Four such cells used for selecting sixteen possible delays.• Each delay ‘block’ is serial combination of two DELAY_C cells.• Fifteen delay blocks are used, thus giving sixteen possible delays (one

is zero - delay)• The four bit input ‘sel’ is decoded combinatorially before being used

to select one of the possible sixteen delays.• The delay introduced by this combinational path is approximately 1.5 ns

(simulated by spectre at 500 C , conservative analysis).

Spectre simulation of the extracted layout– slow process ; temperature - 500 celcius

Fine delay control

Total fine delay Delay2 – Delay1

0000 1.5363 -

0001 3.7060 2.1697

0010 5.8665 2.1605

0011 7.7226 1.8561

0100 10.0685 2.3402

0101 12.0419 1.9734

0110 14.1361 2.0942

0111 16.210 2.0739

1000 17.584 1.39

1001 19.487 1.903

1010 21.1035 1.7165

1011 23.168 2.0645

1100 25.0010 1.833

1101 26.7915 1.7905

1110 28.7924 2.0009

1111 30.8424 2.050

• Average delay through a delay block– about 1.8 to 2.1 ns

• This is the delay through two DELAY_C elements

• Delay due to delay elements, wiring, the AO2222 cells and other combinational logic.

The 15 delay cells and the decoder as depicted by cadence rtl compiler gui.

halfFine_Delay_macro

• This block has fifteen delay ‘blocks’ each consisting of ONE DELAY_C cell• Apart from this difference, it is the same as fine delay macro• Delay control possible in smaller steps (0.8 ns instead 1.9 ns)• Makes use of AO2222 cells, and four bit input is decoded

combinationally.halfFine delay control Total fine delay Delay2 – Delay1

0000 0.4854 -0001 1.4679 0.98250010 2.2935 1.310011 3.09849 0.804990100 4.0581 0.95960101 5.2098 1.15170110 5.9718 0.7620111 6.9085 0.93671000 7.9019 0.99341001 8.9343 1.03241010 9.7733 0.8391011 10.66205 0.88881100 11.525 0.86291101 12.4098 0.88481110 13.293 0.88321111 14.2636 0.9706

Fdelay_macro - Aditya Narayan

• Selects one out of four input clocks and adds a delay to that clock specified by the four bit select input (sel_fdelay[3:0]).• Uses INVERTBAL_L cell instead of DELAY_C cell is the delay element. This

provides a much smaller step delay (each ‘block’ has two cells and a rough delay of 0.1 ns)• Each inverter adds a delay of around 50-60ps and a Mux adds a delay of 200-

350ps• Mux is used to select the clock to be transferred into the fdelay block (sel_FD

[1:0] is the two bit select input)• Thus clocks from 80 MHz to 640 MHz can be transmitted out by introducing

the required delay in them.

Block Diagram of FDelay_Macro, additional buffer and inverters added to maintain signal integrity

Each inverter adds a delay of around 50-60ps and a Mux adds a delay of 200-350ps. The additional inverters (apart from the delay cells) are used to provide greater load driving capacity.

Spectre simulations – for TT process

A delay of 112.8 ps between two delay elements