The Course’s Goals

Computer Architecture - The Instruction Set

The Course’s GoalsTo be interesting and fun.

An interested student learns more.To answer questions that are probably

keeping you awake at night: What is a Super-Scalar machine? How does branch prediction work? What does ILP stand for?

For you to write better programs.By understanding how your program is executed on a computer, will enable you to program better.

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Not the Course’s GoalsTo be b o r i n gb o r i n g. A bored student:

a. Fall asleep, that’s OK just don’t snore.b. Talks, that’s not OK.

To answer questions that aren’t related to computers: “Will George Clooney return to ER” has nothing to due with the course.

For you to design computers.But after this course you will have the necessary basics.

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General InformationContact is by e-mail ([email protected]),

phone (6751168 (jct), 6585766 (hu), 6786784 (home)),or in person (look at my home page for details).

Grade: the final grade is composed of a final exam (70%) and three mini-exams (30%), out of which the 2 best will be used.

Assignments are optional. They will be given in the same format as the mini-exams.

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What is Computer Architecture?

Computer Architecture (CA) is to a computer what classic architecture is to a building.

Classic Architecture

Computer Architecture

ALU ResultZero

Overflow

a

b

ALU operation

CarryOut

b

CarryOut

a

CarryIn

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Computer Architecture (CA) is to a computer what classic architecture is to a building.

The computer architect designs the functional properties of a microprocessor.

With this plan the hardware engineer designs the gates, bits, and lines that implement the processor. If there are problems in implementing the architect’s plan the engineer returns the plan to the architect with suggested modifications.

A computer then translates this plan to the actual transistors laid out on the chip.

Instruction Set Architecture (ISA) is one level above the architecture described above. The machine language of the processor defines the architecture. Processors that are binary compatible are said to have the same architecture.

Examples are the Intel x86 family, MIPS RxK family etc.


Instruction Set Architecture (ISA)The machine language instruction:add $s0,$s1,$s2defines the machines architecture. Addition is performed between 2 registers and the result is placed in a 3rd register.

How this is performed is the implementation of the processor.

Confused? Not for long. In this lesson we will define the Instruction Set Architecture of a modern RISC processor.

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The MIPS ISA

The instruction set we will study is the

instruction set of the family of

processors. Used mainly in the computers of

Silicon Graphics but also in the

products of Nintendo

and Sony.

RISC - Reduced Instruction Set Computer,

also called a Load/Store machine.

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A RISC processor has the following traits: All instructions perform operations between registers. The operands

are in registers and the result is written into a register. The exceptions are the load and store instructions. Data is loaded

from memory into a register, or data is stored from a register into memory.

All instructions are the same length, 32-bits, which is the length of the word of the machine.

The number of possible instruction types is reduced. This is due to the fact that the opcode field of the instruction is limited in size, thus the number of instructions is limited.

On the other hand a Complete Instruction Set Computer (CISC) such as the Intel x86 family (486,Pentium, Pentium II, …) : Can perform operations between registers and memory. Has variable length instructions (from 1 byte and upwards). Has a “complete” set of instructions. Is much more harder to implement as we will see in future lessons.


R-Format Instructionsa=b+c;compiles into: add $s0,$s1,$s2R-Format instructions use 3 registers:add $s0,$s1,$s2 # $s0 = $s1+$s2sub $s1,$s4,$s5 # $s1 = $s4-$s5or $t0,$t0,$t1 # $t0 = $t0|$t1slt $t5,$a1,$a2 # $t5 = $a1<$a2sllv $a0,$s1,$s2 # $a0 = $s1<<$s2sll $a0,$s1,3 # $a0 = $s1<<3

The R-Format instructions include most of the arithmetic and logical instructions.

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MIPS Instruction Fields

MIPS instruction fields are given names:

op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op: basic operation of the instruction called opcoders: first register source operandrt: second register source operandrd: destination register, gets the result of the opshamt: shift amount, used in shift instructions.funct: selects the specific variant of the operation.

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Load/Store InstructionsAre the only instructions thatchar a,b,A[100]; access memory. a = b + A[8]; will compile into:lw $t0, 8($s3) # $s3 holds the # address of Aadd $s1,$s2,$t0

int a,b,A[100];A[6] = b; will compile into:sw $s2,24($s3)

lw - load word, sw - store word

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The constant in a data transfer instruction is called the offset and the register the base register.

Lets look at another example:a = A[6] + A[8]; will compile into:lw $t0, 8($s3) # $s3 holds the lw $t1, 6($s3) # address of Aadd $s1,$t1,$t0

The above code is true if all variables are chars, ints of 1 byte. But if the variables are ints of 4 bytes?

The code is now:lw $t0, 32($s3) # $s3 holds the lw $t1, 24($s3) # address of Aadd $s1,$t1,$t0

The offset is always in bytes, the compiler translates offsets in ints in the C++ program to offsets in bytes in assembly language.


I-format Instructions

The I stand for Immediate, the instruction contains a number. In the case of load/store instructions it is the offset from the base register.

op rs rt address6 bits 5 bits 5 bits 16 bits

Lets look at a load instruction:lw $t0,32($s3) # $t0 = A[8]

rs: base address register ($s3)rt: destination register ($t0)address: offset of -215 to 215 bytes (32)

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Branchsif(i==j)

f=g+h;

else

f=g-h;

bne $s3,$s4,Else

add $s0,$s1,$s2

j Exit

Else: sub $s0,$s1,$s2

Exit:

The j instruction (j for jump) is an unconditional branch instruction.

i == j?

f = g– hf = g + h

Else:

Exit:

i=j ij

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Decision making is possible using branches (הסתעפויות).

The following instructions are conditional branch instructions: beq reg1,reg2,L1 #branch equal

goto the instruction labeled L1 if the register values are equal, if unequal goto the next instruction.

bne reg1,reg2,L1 #branch not equalgoto the instruction labeled L1 if the register values are’nt equal, if equal goto the next instruction.

The branch instructions are of the I-format instruction. The label is an immediate value.

The j instruction (j for jump) is an unconditional branch instruction. The machine always follows the branch. j is of the J-format, 6 bits for opcode and 26 for the jump address.


Addressing in Branchs and Jumps

j 10000 # go to location 10000 Jumps to the address 10000 in memory. 2 10000 6 bits (opcode) 26 bits (address)

bne $s0,$s1,Exit # branch if $s0!=$s1 5 16 17 Exit 6 bits 5 bits 5 bits 16 bits (address)

Addresses of the program have to fit into a 16-bit field.

Thus no program could be larger than 64KByte which is unrealistic.

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Branch Offset in Machine Language

Lets look at a loop in assembly:Loop: . . bne $t0,$t1,Exit subi $t0,$t0,1 j LoopExit:

The machine code of the bne instruction is: 5 8 9 8

The branch instruction adds 8 bytes to the PC and not 12 because the PC is automatically incremented by 4 when an instruction is executed.

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The Program Counter (PC) is a register the software can't access directly, that always contains the address of the current instruction being executed. Thus if we use the PC as the register to add to the branch address we can always branch within a range of -215 to 215 bytes of the current instruction.

This is enough for most loops and if statements. This form of addressing is called PC-relative addressing.

Procedures are not usually within a short range of the current instruction and thus jal is a J-type instruction.

Loop: . bne $t0,$t1,Exit subi $t0,$t0,1 j LoopExit:

The branch instruction adds 8 bytes to the PC and not 12 because the PC is automatically incremented by 4 when an instruction is executed.

In fact the branch offset is 2 not 8. All MIPS instructions are 4 bytes long thus the offset is in words not bytes. The range of a branch has been multiplied by 4.


Pseudodirect Addressing The 26-bit field in the jump instruction is also a word

address. Thus it is a 28-bit address. But the PC holds 32-bits?

The MIPS jumps instruction replaces only the lower 28 bits of the PC, leaving the 4 highest bits of the PC unchanged.

The loader and linker must avoid placing a program across an address boundary ( גבול ) of 256MB (64 million instructions). Otherwise a j must be replaced with a jr.

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Addressing Mode SummaryImmediate addressing - the Operand is a constantRegister addressing - the Operand is a registerBase or displacement addressing - the operand is at

the memory location whose address is the sum of a register and a constant in the instruction.

PC-relative addressing - the address is the sum of the PC and a constant in the instruction.

Pseudodirect addressing - the jump address is the 26 bits of the instruction concatenated ( מצורף ) to the upper bits of the PC.

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Immediate addressing - the Operand is a constantaddi $t0,$t1,102 # $t0=$t1 + 10andi $s0,$s0,16 # $s0=$s0 & 16

Register addressing - the Operand is a registeraddi $t0,$t1,102 andi $s0,$s0,16jr $s4 # jump to the address in $s4

Base or displacement addressing - the operand is at the memory location whose address is the sum of a register and a constant in the instruction.lw $t0,20($gp) # $t0 = $gp[5]lb $t1,7($s5) # $t0 = $s5[7]

PC-relative addressing - the address is the sum of the PC and a constant in the instruction.beg $s0,$s1,Label # if $s0<$s1 jump to Label

Pseudodirect addressing - the jump address is the 26 bits of the instruction concatenated ( מצורף ) to the upper bits of the PC.j L37jal strcmp


Addressing Modes (picture)

Byte Halfword Word

Registers

Memory

Memory

Word

Memory

Word

Register

Register

1. Immediate addressing

2. Register addressing

3. Base addressing

4. PC-relative addressing

5. Pseudodirect addressing

op rs rt

op rs rt

op rs rt

op

op

rs rt

Address

Address

Address

rd . . . funct

Immediate

PC

PC

+

+

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The Course’s Goals

Documents

machines architecture

risc reduced instruction

mips isathe instruction

modern risc processor

loadstore machine

number of instructions

family of processors

store instructions