The Architecture of Konrad Zuse’s Early Computers Raúl Rojas Freie Universität Berlin.

The Architecture of Konrad Zuse’s Early Computers

Raúl Rojas Freie Universität Berlin

Konrad Zuse (1910-1995)

Topics

•Overview•Arithmetic in the Z1 and Z3•The processor•The datapath•Highlights•Were the Z1 and Z3 universal?

The chronology

•Z1 1936-38•Z2 1939•Z3 1940-41•S1 1942 - „Sondermaschine 1“

•S2 1944 - „Sondermaschine 2“

•Z4 1942-45

The Z1 and Z3

Z1 (1936-1938)

Z3 (1938-1941)

- mechanical design

- programmable (punched tape)

- basic arithmetic operations

- completely binary

- floating-point machine

- built with relays

- logically equivalent to the Z1

The original Z1 (Berlin 1938)

A mechanical computing machine ...

The Z3 (1941): built out of relays

Memory

Processor

Light and shadow ...

The punched tape reader

The block architecture

Binary memory

64 wordsmantissa

FP processor

exponent

Numerickeyboard

Numericdisplay

control unit

punchedtape

Decimal input = + 13542 10

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

1

+_

0 6 7 8-8 -7 -6

decimal exponent

sign

decimalmantissa

2

4

5

3

1

+

7

7

•In the Z1 and Z3

•IEEE Standard

Floating-Point Coding

exponent mantissa

+, -

exponent mantissa+, -

1 bit 6 bit 14 bit

1 bit 7 bit 24 bit

Normalized floating-point and rounding

exponent

1 bit 6 bit 14 bit

mantissa

0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

copy to register in processor

1 .

leading one two extrarounding digits

0 00 1 0 1 0 1 0 1 0 1 0 1 0 11 1 1 1 1 1+

Numerical exceptions

zero (lowest exponent)

+ infinite (highest exponent)

- infinite

0 / 0

0 * infinite

infinite - infinite

Specialcoding for :

The machinestops at :

The instruction set - Arithmetic

• Addition Ls1 01 100000• Subtraction Ls2 01 101000• Multiplication Lm 01 001000• Division Li 01 010000• Square root Lw 01 011000

mnemonic

8-bit code

The instruction set - data handling

• Load Pr 11---------• Store Ps 10---------

• Binary to decimal Ld 01 111000• Decimal to binary Lu 01 110000

mnemonic

8-bit code

Structure of the processor

Register 1

exponent mantissa

Register 2

R1 R1

R2 R2

Adders( +, - )

A simple program (a+b)*c

Lu read decimal number to Register 1Lu read decimal number to Register 2Ls1 add Ps 10 store result in address 10Lu read decimal number to Register 1Pr 10 read from address 10 to Register 2Lm multiply Ld show the decimal result

The microsequencers

conducting rod: advancesone position per cycle

step 1

step 2

step 3

step 4

step 5

Pipelining

next instruction

Instruction store

Store operations run in “zero” cycles

Carry look-ahead

•Addition was performed in three steps:• compute sum (XOR)• compute all propagated carries• produce final result

•With relays addition can be performed in constant time (not logarithmic time)

Shifting

•Shifting can be done using a shifting tree (in logarithmic time)

•With relays shifting can be done in constant time

Java simulation of the Z3

The mechanical relays

bit A

bit B

control bit C

= 0

= 0= 1

= 0

A mechanical relay ( B = A AND C )

= 0

bit A

bit B

control bit C

A mechanical relay ( B = A and C )

= 0

= 0

= 0= 1

bit A

bit B

control bit C

A mechanical relay ( B = A and C )

= 0

= 0= 1

= 1

= 1

A two-bit multiplexer

bit A

bit B

bit C = A

A two-bit multiplexer

bit A

bit B

bit C

A two-bit multiplexer

bit A

bit B

bit C = B

The mechanical memory

Zero

prepare operation

The mechanical memory

prepare operation move to “1”

The mechanical memory

move to “1”

store 1

The Z4 in Zurich

Question:

Were the Z1 and Z3 universal?

YES

A single arithmetical loop is universal

we only need6 instructions:

LOADSTORE

+ - * /

Arithmetical operations

a = b op c

LOAD bLOAD copSTORE a

Compiled code

Simulating branching

section 1 0 0 1

section 2 0 1 0

section 3 0 1 1

“execute section 3 = 011”

Transform all operations

•Compute at the beginning of each section t :

t = 1 - [(b1 - z1)(b2 - z2)(b3 - z3)]2

•t is only zero if we are in the desired section

Transform operations

Transform

a = b op c

into

a = a t + (b op c) (1 - t)

this means: only operations in the desired sectionmodify the memory contents

The halting problem

•But how do we stop the

loop? -compute 0/q in

each iteration-the

machine stops when q=0

Summary

Z1 36-38

Z2 39

Z3 39-41

Z4 42-45

The logarithmicmachine

The „logical“machine

Theoretical machines Algebraic machines Special machines

S1 42S2 44

The S1 and S2 (1942-44): fixed point Z3‘s

Binary memory (5-6 words)

Numerickeyboard

Numericdisplay

control unit

punchedtape

mantissa

FP processor

exponent mantissa

processor (relays)

Program

Die Rekonstruktion der Z3

Das Pipeline

•Dr. Frank Darius (FU Berlin) - Schaltungsentwurf•Georg Heyne (Fritz-Haber-Institut) -

Hardwareentwurf•Wolfram Däumel (Fritz-Haber-Institut) - Layout• Lothar Schönbein (Fritz-Haber-Institut) - Fertigung• Torsten Vetter (Fritz-Haber-Institut) -

Mikrokontroller• Cüneyt Göktekin (FU Berlin) Programmierung• Mit Beiträgen von: Alexander Thurm, Fabian Stehn, Georg

Wittenburg (FU Berlin)