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Manufacturing, Cleaning, Gettering - Chapter 4
Text Book:Silicon VLSI Technology
Fundamentals, Practice and Modelingg
Authors: J. D. Plummer, M. D. Deal, and P. B. Griffina d G
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
FRONT END PROCESSES - CLEANING, LITHOGRAPHY, OXIDATIONION IMPLANTATION, DIFFUSION, DEPOSITION AND ETCHING
• Over the next several weeks, we’ll study front end processes individually.• Cleaning belongs to front end processes and is an important part of fabrication
Reference ITRS Roadmap for Front End Processes
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
• Reference - ITRS Roadmap for Front End Processes (http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_FEP.pdf ).
Manufacturing, Cleaning, Gettering - Chapter 4
Defect and Impurities•• Importance of unwanted Importance of unwanted
impurities increases with impurities increases with shrinking geometries of shrinking geometries of devicesdevicesdevices. devices.
•• 75% of the yield loss is 75% of the yield loss is due to defects caused by due to defects caused by particles (1/2 of the min particles (1/2 of the min feature size)feature size)feature size)feature size)
•• Wafer localized light Wafer localized light scatterersscatterers (LLS) is a (LLS) is a starting wafer teststarting wafer test
C l i i dC l i i d•• Crystal originated Crystal originated (45(45--150nm) particles 150nm) particles (COP) ~1,000Å=void (COP) ~1,000Å=void with with SiOSiOxx --> affect gate > affect gate oxide integrity (GOI)oxide integrity (GOI)g y ( )g y ( )
•• --> anneal in H> anneal in H22 --> oxide > oxide decomposes and surface decomposes and surface reconstructs! & oxide reconstructs! & oxide precipitates from deep precipitates from deep
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Wafer Cleaning• Surface films and doped regions must not be
significantly attacked.• Photoresist strip and particle removal typical• Room air and process equipment delivered particles
Significant elements that cause severe problems in silicon– Significant elements that cause severe problems in silicon include: organics, metals (Fe, Au, Cu, etc.) and alkali ions (Na, K, etc.)
Particles
PhotoresistAu
Cu
Fe
ParticlesNa
SiO2 or other thin films
AuFe
Interconnect Metal
N, P
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
– Storage of charge based on minimal charge leakage in time.• Refresh required to maintain charges after a technology defined period of time. g gy
– Dominated by Shockley, Reed Hall (SRH) recombination (intermediate impurity related energy levels).
• σ is the trap cross sectional area, (10-15cm-2) vth is the minority carrier thermal l it (107 / ) d N i th d it f tvelocity (107 cm/sec), and Nt is the density of traps.
• Deep-level traps (Cu, Fe, Au etc.) Pile up at the surface where the devices are located.
BIT LINE
WORDLINE • Refresh time of several msec
requires a generation lifetime of
1- - - -- --- -- -- STORED
CHARGEON MOS
CAPACITOR
ACCESSMOS
TRANSISTOR
sec 1001R μ≈
⋅⋅=
tth Nvστ (2)
• This requires Nt ≈ 1012 cm-3 or
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Clean Factories – Wafer Fab Facility• The wafer fabrication area “Clean Rooms” must
particle free.– Sources of particles
• Air (normal presence of particles) and Water• Machinery – particularly due to friction, metals• People – 5 to 10 million particles per minute, organic• Supplies – brought in to room for use• Processing
– Rooms and People• Clean room limited access, finger wall machine access• Bunny suits, gloves, air showers, covered faces/facemask• Glove box and robots
– Air handling• Positive air pressure, HEPA filters
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Stanford’s CIS Clean Room• The 10,500 square feet clean room is vibration-
isolated from the rest of the building. Support equipment, such as chilled water, vacuum pumps,
i d id t t liair compressors, and acid waste neutralizers, are located in the basement. Corrosive and toxic gases are in a monitored gas area. Liquid gas storage tanks, emergency power generators, and a de-ionized water plant are outdoors.p
• Every 8 seconds, the entire air volume of this room is circulated out to large air ducts, like the meter-wide duct just behind the glass. From there the air flows up to the third floor, down through filters on the
d fl d th b k i t th lsecond floor, and then back into the clean room through the ceiling.
• People inside the room wear bunny suits to minimize the release of human particles into the air. The result is that each cubic foot of air has fewerThe result is that each cubic foot of air has fewer than 100 particles of size 500 nanometers (Class 100), much cleaner than the air in a hospital operating room.
• Air quality is measured by the “class” of the facility.
o Less than X total particleso Less than X total particles greater than 0.5 um per cubic foot of air.
Factory environment is cleaned by:Factory environment is cleaned by:• HEPA filters (99.07% eff.)• Air recirculation (laminar >50 cm/sec)• Bunny suits for workers• Filtration of chemicals and gases• Manufacturing protocols
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
• Frontend Wafer Cleaning based on RCA process– RCA was originally the Radio Corporation of America– Werner Kern developed the basic procedure in 1965 while
working for RCA.
• The RCA clean involves the following :The RCA clean involves the following :1. Removal of the organic contaminants (Organic Clean)2. Removal of thin oxide layer (Oxide Strip)3 R l f i i t i ti (I i Cl )
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
The RCA Clean• The first step (called SC-1, where SC stands for Standard Clean) is
performed with a 1:1:5 solution of NH4OH + H2O2 + H2O at 70º to 80º C for 10 minutes.for 10 minutes.
– This treatment oxidizes organic films and complexes Group IB and IIB metals as well as Au, Ag, Cu, Ni, Zn, Cd, Co, and Cr. The solution dissolves and regrows a thin native oxide layer on the silicon.
Th t t i h t i i i 1 50 l ti f HF + H2O t• The next step is a short immersion in a 1:50 solution of HF + H2O at 25º C
– Remove the thin oxide layer and some fraction of ionic contaminants.• Perform a DI rinsePerform a DI rinse.• The next step (called SC-2) is performed with a 1:1:6 solution of HCl +
H2O2 + H2O at 70º to 80º C for 10 minutes. – This treatment removes alkali ions and cations (AL, Fe, Mg) that form ( g)
NH4OH insoluble hydroxides in solutions like SC-1. In SC-2 they for soluble complexes. This solution also completes the removal of metal contaminants.
• Perform a DI rinse
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Measurement Methods• Clean factories = particle control
– Detect concentrations < 10/wafer of particles smaller than 0.1 µm
• Unpatterened wafers (blank)C t ti l i i– Count particles in microscope
– Laser scanning systems → maps of particles down to ≈ 0.2 µm(see MEMC video on laser inspection from Chapter 3)
• Patterned wafers– Optical system compares a die with a “known good reference”
die (adjacent die, chip design - its appearance) ( j , p g pp )– Image processing identifies defects (SEM)– Test structure (not in high volume manufacturing)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
X-Ray Electron SpectroscopyAuger Electron Spectroscopy
Manufacturing, Cleaning, Gettering - Chapter 4Monitoring of Gettering Through Device Properties and Dielectricp – n leakage, refresh time DRAM junction and dielectric breakdown, β of n-p-n
Material properties : τG(>>τR) in the bulk and on the surface emission↔capture
Device Properties and Dielectric
Photoconductive Decay Measurements
∆n=gopτG
•Carriers are generated due to light •Decrease resistivity•Recombine
)/exp()0()( Rtntn τ−Δ=Δ
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Manufacturing, Cleaning, Gettering - Chapter 4Lifetime Measurements: Open Circuit Voltage Decay
VD (t) = VD (0) − kT ln(erfc t )
t=0
≈0.7V
Voltage Decay
τ R
Diode switched from ON VD when carriers recombine
off
for t/τ>4
τR =kT/q
dVD /dtMeasurements include surface and
for t/τ>4
bulk recombination
Use also DLTS: identifies traps (Et) and concentrationsThermal or photoexcitation processes in voltage modulable space-charge region (Schottky Diode, p-n junction, MOS Capacitor)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Deep Level Transient Spectroscopy• An experimental tool for studying electrically active
defects (known as charge carrier traps) in semiconductors. – DLTS enables to establish fundamental defect parameters
and measure their concentration in the material. – Some of the parameters are considered as defect “finger
prints” used for their identifications and analysis.– identifies traps (Et) and concentrationsidentifies traps (Et) and concentrations– http://en.wikipedia.org/wiki/DLTS
• Thermal or photoexcitation processes in voltage d l bl h imodulable space-charge region
(Schottky Diode, p-n junction, MOS Capacitor)– Measured: capacitance, currents or conductance
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
(photoresist) and metals from wafer surfaces.– Particles are largely removed by ultrasonic agitation during
cleaning.– Organics like photoresists are removed in an O2 plasma or in g p 2 p
H2SO4/H2O2 solutions.– The “RCA clean” is used to remove metals and any remaining
organics.g
• Metal cleaning can be understood in terms of:– Convert metal into ions soluble in the cleaning solution
Oxidation: the process that removes electrons from an atom ( )• Oxidation: the process that removes electrons from an atom (→)• Reduction: the process that gains and electron (←)
Si + 2H 2O ↔ SiO 2 + 4H + + 4e− (5)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
• If we have a water solution with a Si wafer and metal atoms and ions, the stronger reaction will dominate
++↔ eHOHOH 222 222 (7)
the stronger reaction will dominate.• Generally (7) is driven to the left and (5) and (6) to the right so that
SiO2 is formed and Mz+ is a solution soluble ion.• Good cleaning solutions drive (6) to the right since Mz+ is soluble and• Good cleaning solutions drive (6) to the right since Mz is soluble and
will be desorbed from the wafer surface.
N d l i t b t th i l d t di f th h i t
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Manufacturing, Cleaning, Gettering - Chapter 4Trapping the Metal Atoms at the Gettering Sites (1)
• Trapped by: ion implantation, P diffusion, laser damage, poly-Si films, mechanical damage, etc. But HOW?
at the Gettering Sites (1)
• Physical damage -> metal trapped at defect sites; binding energy Eg depends on T;
i d ( )Fraction Bound=(1-K1exp-Eg/kT)
• Segregation, related to solubility in the silicon perfect crystal and in the gettering regionand in the gettering region
CAu,Si=NSiexp(-EA1/kT) in silicon regionCAu,G=NGexp(-EA2/kT) in gettering region
• The segregation coefficient is defined asThe segregation coefficient is defined ask0=(CAu,G+CAu,Si)/CAu,Si= 1+K2exp[-(EA1-EA2)/kT]For the case of phosphorousk0=1+NG/5x1022exp(0.82eV/kT ) (fraction of Au bound in gettering )
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Manufacturing, Cleaning, Gettering - Chapter 4Trapping the Metal Atoms at the Gettering Sites (2)
• Enhances sol.sol by high dopant concentrations: in “n” Au=acceptor, “p” - Au=donorA + - A - K [A -]/[A ][ -] t t
at the Gettering Sites (2)
Au+e- ↔Au-, Keq=[Au-]/[Au][e-]=constant,
[Au-i]/[Au]ni= [Au-
n]/[Au]n or [Au-n]/[Au-
i] = n/ni
Au acceptor ↑ in “n+” Si (100x if ni(1000°C)=7 14x1018 -> 1021cm-3 doping level)Au acceptor ↑ in n Si (100x if ni(1000°C) 7.14x10 > 10 cm doping level)
• Ion pairing model: AuP ↔ less strainIncreases with Phosphorous concentration
• Coulombic attraction Au+P → Au-P+
• Interaction with point defects V- ↑↑ in “n+” Aui+V- ↔Aus at the trapepd siteInteraction with point defects V ↑↑ in n Aui V Aus at the trapepd site
• Intrinsic gettering - trapping on dislocations and SF which surround precipitates. Dislocations have compressive and tensile stress - accommodate smaller and larger atoms
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
– intrinsic (less extrinsic), – control Oi, Cs, – use low T processing, – use modeling tool →point defects engineering, g p g g,– release, diffuse, entrap.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Summary of Key Ideas• A three-tiered approach is used to minimize contamination in wafer
processing.• Particle control wafer cleaning and gettering are some of the "nuts and• Particle control, wafer cleaning and gettering are some of the nuts and
bolts" of chip manufacturing.• The economic success (i.e. chip yields) of companies manufacturing
chips today depends on careful attention to these issues.c ps oday depe ds o ca e u a e o o ese ssues• Level 1 control - clean factories through air filtration and highly purified
chemicals and gases.• Level 2 control - wafer cleaning using basic chemistry to remove g g y
unwanted elements from wafer surfaces.• Level 3 control - gettering to collect metal atoms in regions of the wafer
far away from active devices.• The bottom line is chip yield. Since "bad" die are manufactured
alongside "good" die, increasing yield leads to better profitability in manufacturing chips.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin