Testing21.pdf

Mar 17, 2008 E0286@SERC 1

VLSI Testing Delay Test

Virendra SinghIndian Institute of Science

[email protected]

E0286: Testing and Verification of SoC Designs

Lecture 21

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Sequential Circuit Test

S0

S1 S2

S4

S6

S3

S5

Ohtake, ATS’98Non-Scan DFT Methodology

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Sequential Circuit TG

Combinational TG Model

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Sequential Circuit TGAdvantages:

1. Use of Combinational ATPG

2. Complete FE

3. Shorter TA time

4. At-speed testing

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Sequential Circuit TG

An FSM traversing invalid state

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Sequential Circuit TGDFT Methodology:

1. Logic Synthesis

2. Combinational TG

3. Appending an extra logib

1. Synthesis of ISG

2. Appending ISG

4. Adding Hold mode to the status register

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Sequential Circuit TG

A controller augmented with invalid test state generated

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Sequential Circuit TG

A controller augmented with invalid test state generated

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Delay Test

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Delay Test DefinitionA circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing.For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic.Delay test problem for asynchronous circuits is complex and not well understood.

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Digital Circuit Timing

Inpu

tsO

utpu

tstime

Transientregion

Clock period

Comb.logic

OutputObservation

instant

InputSignal

changes

SynchronizedWith clock

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Circuit DelaysSwitching or inertial delay is the interval between input change and output change of a gate:

Depends on input capacitance, device (transistor) characteristics and output capacitance of gate.Also depends on input rise or fall times and states of other inputs (second-order effects).Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output.

Propagation or interconnect delay is the time a transition takes to travel between gates:

Depends on transmission line effects (distributed R, L, Cparameters, length and loading) of routing paths.Approximation: modeled as lumped delays for gate inputs.

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Event Propagation Delays

2 4 61

1 3

5

3

10

0

0

2

2

Path P1

P2

P3

Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew

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Circuit OutputsEach path can potentially produce one signal transition at the output.The location of an output transition in time is determined by the delay of the path.

Initial value

Initial value

Final value

Final value

Clock period

Fast transitions Slow transitions

time

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Delay Test

Exposes temporal defectsDetermines the operational correctness of a circuit at its specified speedFault models

Transition Fault (TF) modelPath Delay Fault (PDF) modelSegment Delay Fault (SDF) model

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Definitions

Controlling value (cv) : An input of a gate is said to have a controlling value if it uniquely determines the output of the gate independent of other inputs

For example, 0 for AND or NAND

A path R in a circuit is a sequence (g0g1……gr), where g0 is a PI, g1g2.. are gate outputs, gr is a PO

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DefinitionsAn on-input of path R is a connection between two gates along path R

A side-input (off-input) of path R is any connection to a gate along path R other than its on-input

A path that starts at a primary input and ends at a side-input of path R is called a side-pathof R

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Transition Delay Fault

Two faults per gate; slow-to-rise and slow-to-fall.Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault.Models spot (or gross) delay defects.

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Transition Delay Test

1

3

1

1

1

2

Path P1

P2

P3SA0

D’

D’

D’ D

1

D’

1

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Transition Delay Test

1

3

1

1

1

2

Path P1

P2

P3

Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew

SA0

D’

D’

D’ D

0

0

D

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Transition Delay Test

1

3

1

01

01

2

Path P1

P2

P3SA00D’

0D’

0D’ 1D

00

X0

1D

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Path Delay Fault

Cheng’s classificationRobustly testableNon-robustly (NR) testableFunctional sensitizable (FS) testableFunctionally unsensitizable(functionally redundant)

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Thank You