Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM Test Set Compaction for Sequential Circuits based on Test Relaxation M.S Thesis Defense M.S Thesis Defense S. Saqib Khursheed S. Saqib Khursheed Advisor: Dr. Aiman H. El-Maleh Advisor: Dr. Aiman H. El-Maleh Members: Dr. Sadiq M. Sait & Dr. Members: Dr. Sadiq M. Sait & Dr. Alaaeldin Amin Alaaeldin Amin 29 29 th th Dec 04 Dec 04
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Test Set Compaction for Sequential Circuits based on Test Relaxation
Test Set Compaction for Sequential Circuits based on Test Relaxation. M.S Thesis Defense S. Saqib Khursheed Advisor: Dr. Aiman H. El-Maleh Members: Dr. Sadiq M. Sait & Dr. Alaaeldin Amin 29 th Dec 04. Outline. Motivation State of the Art Static Compaction Algorithms - PowerPoint PPT Presentation
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Test Set Compaction for Sequential Circuits based on Test Relaxation
Exp. Results: Hybrid-FC-LRORSTRATEGATE Test Sequences
Circuit TSITE
LROR [12]
ITE SIFAR [13]
ITE MISC[12
]
ITE Hyb-FC-
LROR
S298 194 125 112 98 95
S344 86 47 48 43 38
S641 166 78 87 63 59
S713 176 72 94 60 45
S820 590 394 388 335 347
S832 701 458 435 368 366
S1196 574 221 237 216 180
S1238 625 222 251 222 192
S1488 593 343 312 364 380
S1494 540 297 313 296 362
S5378 11481 711 597 583 561
Total 15983 2968 2874 2648 2625899Better
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Exp. Results: Hybrid-FC-LRORHITEC Test Sequences
ITE ITE ITE
Ckt TS LROR [12] MISC [12] Hyb-FC-LROR
s298 322 109 97 96
s344 127 47 47 44
s641 209 63 72 60
s713 173 74 74 57
s820 1115 578 432 403
s832 1137 562 383 379
s1196 435 226 223 182
s1238 475 227 225 188
s1488 1170 571 572 586
s1494 1245 540 492 462
s5378 912 245 271 215
s3271 709 555 443 351
s3330 578 219 218 188
s3384 161 104 92 56
s4863 518 302 315 136
Total 9286 4422 3956 3403
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Limitations of Justification Algorithm
• Justification of G/F value is done based on cost functions, which is an approximate method.
• Cost of Good value is only used.
• These limitations result in extraction of longer test sequences than necessary.
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Conclusion & Future Work
• In this work, we have proposed several efficient static compaction techniques, which achieve the following:– Better or comparable level of compaction while reducing the
runtime.
– All important attributes of static compaction techniques are integrated.
– Limitation of quick saturation of Restoration based techniques has been addressed.
– A new class of compaction algorithms has been introduced, based on increasing the fault-coverage of restored subsequences.
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Conclusion & Future Work
• Investigate techniques to overcome the limitations of Justification Algorithm.
• Investigate techniques for increasing the fault coverage of an extracted Subsequences.
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Thank you!Q & A
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Backup Slides
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
• Unique opportunities provided by Static Compaction:– It may be applied to test vectors generated by any
ATPG tool without modifying the test generation process.
– It may be applied after dynamic compaction.– It takes lesser time to get final test set.– The shortest test sequence for sequential circuits are
generated by static compaction techniques.• For these reasons, Static Compaction is more popular in
Sequential circuits than Dynamic Compaction.
Types of Compaction Algorithms
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Modified LROR
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
• SIFAR uses the basic idea of Test Vector Restoration.
• It considers a single target fault (in decreasing order of detection time) and restores test vectors until fault is detected.– This is also called Test Vector Restoration.
• SIFAR uses parallel fault simulator to speed up the restoration process.
Targeting f1 and f2. Restoring vector #9 doesn’t detect the fault. r=2, i=1
Restoring vector # 7, 8 and 9, doesn’t detect the fault f1 and f2. r=2, i=2
f1 and f2 detected
Restoring vector # 3, 4, 5 and 6, detects the faults f1 and f2.
r=2, i=3
Restored vector # 3, 4 … 9, are concatenated with previously restored test vectors .
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
• A newly restored subsequence may be merged with previous subsequences either towards Top or Bottom or from where the savings are highest.
• Merging towards bottom starts from top and slides the newly restored SS downwards until merged or appended.
• Merging towards TOP starts from Bottom and slides the newly restored SS upwards until merged or appended
Merging Restoration
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Test Set Compaction for Sequential Circuits
Computer Engineering, KFUPM
Fault-Coverage based Compaction
• Observations: Initially restored test sequences cover a large number of faults. This is called covering effect, which is used by Restoration based compaction algorithms.
• Motivation: A large reduction in test size is possible by increasing the fault coverage of currently restored subsequences.