Technology Roadmap for Wide Band Gap
Power Electronics 2018
Editorial Committee
Consultant:
Gan Zizhao, Zheng Youliao, Wang Lijun, Hao Yue, Liu Ming, Braham
Ferreira
Guiding Expert:
Bai Song, Cai Shujun, Daniel Shi, Jiang Fengyi, Li Jinmin, Liu Guoyou,
Qiu Yufeng, Shen Bo, Xu Ke, Xu Xiangang, Zhang Bo, Zhang Guoqi,
Zhang Rong,
Editor:
Sheng kuang, Wang Xinqiang, Yu Kunshan
Chapter Editor:
Substrate, Epitaxy and Device: Zhang Yun, Li Xihuang, Wang Ronghua
Packaging and Module: Xie Bin, Mei Yunhui
SiC Applications: Ru Yonggang, Dai Chaobo, Li Chengzhan
SiC Applications: Li Shunfeng, Yehuaiyu, Wangwenbo
Editorial Committee:
Chang Guiqin, Chen Lixia, Chen Peng, Chen Ping, Cheng Kai, Dai
Xiaoping, Gao Ziyang, Han Yongjie, Huang Yiming, Ji Bing, Jia Lifang,
Ke Haotao, Li Chengzhan, Li Haiyan, Li Jianhua, Liang Lin, Liu Jianli,
Liu Jianping, Liu Kun, Liu Qiqi, Liu Xuechao, Liu Yadong, Liu Zhe,
Lu Hai, Ning Puqi, Niu Pingjuan, Pei Yi, Qian Qinsong, Qu Hanbin,
Ren Tianling, Ruan Xinbo, Shen Zhanwei, Sheng Junyi, Song Huiqi,
Sun Guosheng, Sun Weifeng, Sun Yaofeng, Tao Xutang, Wang Fangfang,
Wang Gang, Wang Haitao, Wang Jianfeng, Wang Laili, Wang Liqiang,
Wei Yongqiang, Wei Yueyuan, Wu Haiping, Xiao Hongling, Xie Feng,
Xu Hengyu, Xu Ju, Xu Sha, Xu Xiaohui, Yang Kun, Yang Lanfang, Yang
Shu, Yang Xu, Zhang Bin, Zhang Feng, Zhang Jincheng, Zhang Jing,
Zhang Xinhe, Zhao Botao, Zhao Lubing, Zheng Liu, Zhou Qi, Zou Shihe,
Note: If there is any conflict between the English version and the
Chinese version, please refer to the Chinese Version.
CATALOG
1. Substrate, Epitaxy and Device ...................................................................................................... 1
1.1 Background Information ..................................................................................................... 2
1.2 Summary of the driving force of the development of technology / product ....................... 4
1.3 Key Performance/Development Trend of Parameter .......................................................... 5
1.3.1 SiC substrate and epitaxy ......................................................................................... 5
1.3.2 SiC power device ................................................................................................... 12
1.3.3 Si-based GaN epitaxy and power devices .............................................................. 30
1.3.4 GaN single crystal substrate and vertical power device ......................................... 37
1.3.5 Diamond materials and devices .............................................................................. 48
1.3.6 Ga2O3 epitaxy and device ....................................................................................... 53
1.4 Summary ........................................................................................................................... 61
2. Packaging and Module ................................................................................................................ 62
2.1 Background ....................................................................................................................... 63
2.2 Product Definition ............................................................................................................. 63
2.3 Overview of Driving Force ............................................................................................... 64
2.4 The Trend of Key Indicators/Parameters........................................................................... 65
2.4.1 Structure and Dimension ........................................................................................ 65
2.4.2 Electrical Performance ........................................................................................... 67
2.4.3 Power and Heat Dissipation ................................................................................... 71
2.4.4 Materials and Process ............................................................................................. 73
2.4.5 Reliability ............................................................................................................... 79
2.5 Summary ........................................................................................................................... 81
3. SiC Applications ......................................................................................................................... 83
3.1 Status of SiC devices ......................................................................................................... 84
3.2 Development trends of SiC devices .................................................................................. 84
3.3 The overall technology roadmap of SiC device applications ...................................... 85
3.3.1 Competitive analysis of SiC devices and Si devices .............................................. 85
3.3.2 Driving force .......................................................................................................... 85
3.3.3 Differentiated development .................................................................................... 87
3.3.4 Common weaknesses ............................................................................................. 87
3.4 Technical route of SiC devices in power grid application ........................................... 88
3.4.1 DC transmission ..................................................................................................... 88
3.4.2 Flexible substations ................................................................................................ 89
3.4.3 Flexible AC transmission ....................................................................................... 90
3.4.4 Photovoltaic system ............................................................................................... 91
3.4.5 Solid state switches ................................................................................................ 93
3.5 Technology routes of SiC devices in electric traction applications ............................. 94
3.5.1 Introduction ............................................................................................................ 94
3.5.2 Driving forces ........................................................................................................ 95
3.5.3 Requirements for device ........................................................................................ 95
3.5.4 Development forecast ............................................................................................. 95
3.6 Technology routes of SiC devices in electric vehicle applications ............................. 98
3.6.1 Introduction ............................................................................................................ 98
3.6.2 Driving forces of technology/ product development .............................................. 99
3.6.3 Requirements for device ...................................................................................... 102
3.6.4 Key indicators/ parameters development trend .................................................... 102
3.6.5 Development forecast ........................................................................................... 104
3.7 Technology routes of SiC devices in household appliances and consumer electronics
105
3.7.1 Introduction .......................................................................................................... 105
3.7.2 Driving forces of SiC devices in household consumer product applications ....... 105
3.7.3 Development trends of SiC in household appliance and consumer product
applications ................................................................................................................... 107
3.8 Summary ................................................................................................................... 110
4. GaN Applications ...................................................................................................................... 111
4.1 Introduction ..................................................................................................................... 112
4.1.1 Cascode GaN transistors ...................................................................................... 113
4.1.2 P-gate GaN transistors .......................................................................................... 113
4.1.3 Insulatedgate structure GaN transistor ................................................................. 114
4.2 Application areas ............................................................................................................. 115
4.2.1 Overview of GaN applications ............................................................................. 115
4.2.2 Server power supply applications ........................................................................ 117
4.2.3Power adapters ...................................................................................................... 119
4.2.4 Power PFC applications ....................................................................................... 120
4.2.5 High frequency lidar applications ........................................................................ 122
4.2.6 Signal envelope tracking ...................................................................................... 123
4.2.7 Wireless charging ................................................................................................. 125
4.2.8 On-board charging ............................................................................................... 126
4.3 Discussion and countermeasures of some necessary conditions for application
implementation...................................................................................................................... 126
4.3.1 New requirements of new applications for GaN devices ..................................... 126
4.3.2 Problem of matching components ........................................................................ 128
4.3.3 Thermal management ........................................................................................... 129
4.3.4 Evolution of topology .......................................................................................... 130
4.4 Prediction of evolution of main performance parameters ............................................... 131
4.4.1 Efficiency ............................................................................................................. 131
4.4.2 Evolution of power dimension and power density ............................................... 132
4.4.3 Cost ...................................................................................................................... 134
4.5 Risk and related issues .................................................................................................... 135
4.5.1 Market and price .................................................................................................. 135
4.5.2 Problems ............................................................................................................... 136
4.5.3 Risk control proposal ........................................................................................... 138
1
Substrate, Epitaxy and Device
2
1.1 Background Information
The third-generation semiconductor has many attractive properties such as a large
bandgap energy, high breakdown electric field, high thermal conductivity, high
saturation electron velocity, and strong radiation resistance. It plays an important role
in the fields of high voltage, high power, energy saving, and high efficiency, and can
meet the demand of high voltage and low power consumption of electronic devices in
future power system. In recent years, under the situation of the rapid development of
substrate and epitaxy, the device has also achieved remarkable achievements. Some
performances exceed the silicon-based devices a lot, which promotes the application
and industrialization of devices represented by SiC and GaN so that it has gradually
replaced silicon-based devices in some important energy fields and shown great
market potential.
Since the breakthrough made by the SiC single crystal growth method in the late
1970s, especially the industrialization in the 1990s, the SiC substrate preparation
technology has been in a state of rapid development, the controlling of substrate
defect density and surface quality are rapidly improved, so the SiC substrate is in the
upstream of the industry. However, the quality of SiC epitaxial materials and the
performance and reliability of SiC-based power electronic devices is limited by
substrate crystal defects and surface processing quality. In recent years, the rapid
development of unipolarity device fabrication technology represented by SiC-based
MOSFET has made the substrate defects more and more important to device’s
performance and reliability. Besides the quality of the substrate material, the cost of
the substrate still occupies a relatively high proportion, which limits the rapid
application of SiC-based power electronic devices. With the rapid development of
downstream industries and the advancement of single crystal preparation technology,
it is expected that SiC substrates will rapidly develop in the direction of large size,
low crystal defect density and low cost of unit area in the next 20 to 30 years. At
present, SiC-based electronic devices have been widely used in photovoltaic, power
factor correction/power, automotive, wind power, and traction locomotive. The
market share of SiC power electronic devices has also been rapidly developing. In
2017, Yole investigated that the market size of SiC-based power electronic devices
has reached $250 million, and it is expected to reach $800 million in 2021.
While maintaining higher conversion efficiency, systems using GaN electronics
can operate at higher switching frequencies, the large size and indirect cost of
components such as inductors, transformers, heat sinks, drive circuits, and EMC
circuits in the circuit can be effectively controlled so that we can improve the system
integration and cost performance. Since the GaN substrate or SiC substrate required
for GaN epitaxy is expensive, and the Si substrate has the advantages of large size and
low cost, industrialization of GaN power devices on Si substrates has become a
consensus in the industry.
The diamond has the advantages of high breakdown electric field, high saturation
electron velocity, good chemical stability, strong radiation resistance and high thermal
3
conductivity, which can meet the future applications of high power, strong electric
field, and extreme radiation. However, in addition to the application of diamond as a
heat sink and detector, other products are still in the research stage. The diamond
material epitaxy is in the upstream of the industry, and the low-cost, large-size,
high-quality substrate is the basis for industrialization. In the 20th century, artificial
diamond epitaxy technology developed rapidly. Based on homoepitaxial technology, a
2-inch single crystal diamond has been realized with a defect density of fewer than
1000 cm-2 and a 4-inch area based on heteroepitaxial growth. However, homoepitaxial
growth depends on the quality and size of the substrate, and heteroepitaxial nucleation
and defect control are difficult, which severely limits the development of diamond.
The doping of diamond is very difficult, and it is hard to form high conductivity at
room temperature. At present, termination of diamond surfaces with hydrogendevices
with P-type surface conductivity at room temperature have emerged in high-voltage,
high-temperature high-frequency device applications. However, the hydrogen
terminal diamond surface conductance has the disadvantages of low carrier mobility
and poor stability of the device. In general, diamond substrates are expected to
develop rapidly in the future 20 to 30 years toward large size, low crystalline defect
density, and low unit cost. With the improvement of epitaxial quality and carrier
mobility, as well as breakthroughs in key issues such as new doping technology, the
characteristics of diamond electronic devices are expected to surpass existing GaN,
SiC-based electronic devices, and diamond-based electronic devices will get a certain
market share in the power, automotive, wind power, and traction locomotive
industries.
As a new type of ultra-wide bandgap semiconductor material, gallium oxide
(Ga2O3) has received extensive attention. Compared with SiC and GaN, Ga2O3 is a
wide bandgap material with a bandgap of ∼4.9 eV, and its critical breakdown electric
field is 8MV/cm, which is suitable for making large voltage and high power field
effect transistor. Due to the strong electric field breakdown resistance, Ga2O3-based
electronics can achieve low heat losses by reducing the on-resistance. Although Ga2O3
has lower electron mobility than SiC and GaN, it can withstand the high electric field
required to reach a saturated electron rate due to its higher breakdown electric field,
also, it has high power frequency product, and the Johnson quality factor is higher
than SiC and GaN. Therefore, Ga2O3-based electronic devices are not only suitable
for power switching devices, but also for RF devices. In addition, the most attractive
advantage of Ga2O3materials is that its single crystal is easy to prepare, such as
Czochralski method, floating-zone technique, vertical Bridgman method,
guided-mode method, so it is possible to realize the cost-effective thin-film epitaxy,
which facilitates the realization of inexpensive, high-performance electronic devices.
Since the Ga2O3material device is used for high power and high withstand voltage
applications, the crystal quality is highly demanded. Correspondingly, most of the
devices for Ga2O3 are β- Ga2O3 single crystal. At present, the preparation of Ga2O3
materials and devices is still in infancy. The factors include larger device series
resistance and lower electron mobility, which restricts Ga2O3 devices, especially
MOSFET devices. To utilize the ultra-wide bandgap of Ga2O3, it is necessary to
4
continue to optimize and improve the quality of single crystal and epitaxy, device
structure and process flow.
This roadmap describes the development trends of SiC substrates and epitaxy, SiC
power devices, GaN epitaxial and power devices, diamond materials and devices,
Ga2O3 epitaxy and devices in the next 30 years (2018~2048). We will discuss the key
aspects of substrate diameter, crystal defect density, and unit area cost, the key index
of SiC, GaN, diamond, Ga2O3 such as electrical properties, packaging, heat
dissipation, reliability, and the cost.
1.2 Summary of the driving force of the development
of technology / product
Market: With the continuous drive of the downstream market of the power system
for the high voltage and low power consumption of power electronic devices, the third
generation of power electronic devices represented by SiC and GaN will gradually
replace Si-based power electronic devices in some fields. Therefore, the market share
will be increasing year by year, which also drives the growth of substrate and epitaxy.
Commercial products appear in diamond power electronic devices as well.
Cost: As an alternative product of Si-based devices, SiC and GaN devices are
challenged by the cost in the process of marketization. The continuous reduction of
cost is their own development trend and market demand. The increase of artificial
diamond wafer size will greatly reduce its material and device costs.
Material defect density: Due to the demand for system reliability, the requirements
for device performance and reliability will become more and more stringent, so higher
requirements are placed on the defect density of substrate and epitaxial materials.
Voltage/current carrying capacity: With the high power and high-efficiency
requirements of the power electronic system, the demand for voltage/current carrying
capacity of SiC power devices and GaN power devices is increasing. The
development of diamond power devices is also driving the increase of device
voltage/current carrying capacity.
Packaging and heat dissipation: SiC power devices, GaN power devices have low
loss, and the operating junction temperature range is higher than that of Si devices, so
the cooling device volume can be reduced. These excellent features promote the
development of power devices toward integration, miniaturization, and high
efficiency.
Frequency requirements: SiC power devices and GaN power devices have high
electron saturated drift rates and small capacitance, so the device operating frequency
can reach above MHz, thus reducing the passive device and the overall size of the
system.
Conversion efficiency: The increase of power conversion efficiency in large-scale
power consumption not only saves energy consumption but also reduces the need for
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heat dissipation. The extremely high thermal conductivity of diamond is beneficial to
reduce power consumption and improve conversion efficiency.
Reliability: The superior characteristics of high temperature, high frequency, high
power and anti-irradiation of SiC power devices and GaN power devices make it
more likely to be used in future high-end industrial fields and extreme environments.
Improvement of the reliability of the third-generation semiconductor promotes its
market expansion.
1.3 Key Performance/Development Trend of
Parameter
1.3.1 SiC substrate and epitaxy
1.3.1.1 SiC substrate
◼ Substrate diameter
➢ Development trend: (as shown in Fig1.1)
⚫ The diameter of the substrate currently used is mainly 100mm. With the
gradual popularization and application of SiC-based power electronic
devices, the cost of the device is becoming more and more sensitive.
Large-diameter substrates can effectively reduce the cost of device
fabrication. For example, using a substrate with a diameter of 150 mm can
reduce the device fabrication cost by about 30% compared to a diameter of
100 mm. Therefore, It is expected that the proportion of large-sized
substrates will continue to increase in the next 30 years..
⚫ At present, the mainstream manufacturers have completed the research
and development of 150mm diameter SiC substrate and have entered the
mass production stage. Therefore, from 2018, the proportion of 100mm
diameter SiC substrate will start to decrease year by year.
⚫ Some manufacturers have completed the research and development of
200mm diameter SiC substrate and can provide a small number of samples.
It is estimated that the 200mm diameter substrate will enter the market
before 2020.
➢ Challenge:
⚫ Temperature field design and implementation:
The suitable temperature field is the basis for the preparation of SiC single
crystal. The quality of the single crystal is directly related to the
temperature field. Unsuitable temperature field is likely to cause cracking
6
of single crystal and the proliferation of crystal defects. With the increase
of the diameter of the single crystal, the size of the hot zone increases
rapidly, which makes the design and the implementation of the suitable
temperature field difficult.
⚫ Low defect density seed crystal:
It is difficult to expand the diameter of the single crystal by the
vapor-phase growth method. Besides, it is hard to obtain low defect
density seed crystal by using small diameter seed crystal diameter
expansion.
⚫ Comprehensive control of large-size single crystal and crystal defects:
The increase in the size of single crystals tends to be accompanied by a
decrease in the quality of the crystal. How to increase the size while taking
into account the control of the density of crystal defects is another key
problem that needs to be solved to increase the size of the substrate.
Fig 1.1 The development trend of SiC substrate size
➢ Potential solution:
⚫ Using numerical simulation to guide the design of large-scale temperature
field of single crystal growth, to achieve temperature field control in
different growth stages.
◼ Crystallographic defect density
➢ Development trend: (as shown in Fig1.2)
⚫ With the rapid application of SiC-based power electronic devices, the
requirements for device performance and reliability are getting more and
more stringent. Crystal defects (such as microtubules, threading screw
dislocations (TSD), and basal plane dislocations (BPD)) can adversely
affect the device. With the rapid development of diverse technology that
decreases and converts single crystal defects, it is expected that the density
of crystal defects in the substrate will continue to decrease.
⚫ At present, mainstream manufacturers have the ability to fabricate low
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micro tube density substrates (
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substrate will decrease slightly for the rapid promotion of the 150mm
diameter substrate. After the most substrate manufacturers have completed
the research and development of the single crystal growth of low
dislocation and the thick single crystal growth, the unit area price of the
substrate will reduce rapidly.
➢ Challenge:
⚫ The research and development cycle of the single crystal growth of low
dislocation
⚫ For the growth temperature of SiC is high, traditional methods for
reducing defects (such as masking method) are no longer applicable, so it
is necessary to invest in a long time and a large cost to develop new
processes, and a long research and development cycle may hinder the unit
area cost reduction of the substrate.
⚫ With the increase of the thickness of single crystal growth, the residual
internal stress of single crystal increases rapidly, which may lead to the
degradation of single crystal quality and even the cracking of single crystal.
It is difficult to not only increase the available thickness of single crystal
but also improve the quality of single crystal.
Fig 1.3 The development trend of per unit price of the SiC substrate(RMB/cm2)
1.3.1.2 SiC epitaxy
◼ Size:
➢ Development trend
⚫ Diameters of SiC with 100mm and 150mm are the normal sizes of SiC
epitaxial wafers. With the widespread use of SiC devices, the cost
requirements for SiC devices are becoming more and more stringent.
Larger SiC epitaxy can effectively reduce the cost of subsequent device
fabrication, so in the next 30 years, the proportion of large-size SiC
epitaxial wafers will increase year by year.
⚫ Now, mainstream substrate suppliers at home and abroad are already
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2018~2023 2023~2028 2028~2033 2033~2038 2038~2043 2043~2048
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selling 150mm diameter SiC substrates or have completed 150mm
substrate preparation technology. The market share of 100mm diameter
substrates will decrease year by year.
⚫ At present, the main manufacturers of SiC devices in China still use
100mm SiC epitaxial wafers widely. Under the condition that the supply
of 150mm SiC substrate cannot be greatly improved, it is expected that
100mm SiC epitaxial wafers will be widely used in the next three years.
⚫ The international mainstream SiC device manufacturers have basically
completed the transfer to 150mm SiC technology. The demand will grow
rapidly in the next 5-10 years. Some companies’ original process lines also
retain 100mm technology.
⚫ Although the 200mm SiC substrate and epitaxy have been demonstrated, it
will be a long process entering the SiC power device market. After 5 years,
200mm SiC epitaxial technology will be mature, and 200mm SiC power
device production line may appear after 10 years.
➢ Challenge:
⚫ Cost: By now, 100mm SiC epitaxial wafer is close to its lowest price, and
the price reduction space is limited in the future; the price of 150mm SiC
epitaxial wafer is still relatively high due to insufficient substrate supply.
As the substrate quality improve and wafer supply increase and the yield
of epitaxial wafers increases, the price of the epitaxial wafer will reduce
rapidly.
⚫ Control of epitaxial wafer uniformity: The increase of epitaxial wafer size
tends to be accompanied by the decline of epitaxial wafer uniformity. How
to control the uniformity of the large-scale epitaxial wafer is a key
problem to be solved to improve device yield and reliability and thus
reduce cost.
⚫ Epitaxial defect control: Large-sized devices are the mainstream demand
in the future application market. Defect density is the key index to
restricting the yield of large-size chips. Therefore, epitaxial defect control
including crystal defects and surface topography defects is a major
challenge.
➢ Potential solution:
⚫ Improve the temperature field and flow field distribution of large-scale
epitaxial growth, and control the interface morphology at the initial stage
of epitaxy.
◼ BPD dislocation density
➢ Development trend ( as shown in Fig 1.4)
⚫ The basal plane dislocation (BPD) is an important crystalline defect
affecting the stability of SiC bipolar power devices. Continuous reduction
of BPD density is the main direction of epitaxial growth technology. As
the substrate quality is improved, the BPD of SiC epitaxial layer is
expected to reduce from 1/cm2 to 0.1/cm2.
10
⚫ The most mature preparation technology of SiC crystal is physical vapor
transport (PVT). At present, the SiC crystal grown by PVT has a high BPD
density, and the BPD which is harmful to the device in the epitaxial layer
mostly comes from the BPD in the substrate. Therefore, improving the
crystal quality of the substrate can effectively reduce the BPD dislocation
density of the epitaxial layer.
⚫ With the application of SiC devices, the device size and flow capacity are
increasing, and the requirement for crystal defect density is stringent, so
the crystal defects density of SiC epitaxial wafers will decrease.
Fig 1.4 The development trend of BPD density in SiC epitaxial wafer
◼ The thickness of the epitaxial wafer
➢ Development trend
⚫ The application advantages of SiC are high-voltage, ultra-high voltage
devices. At present, 600V, 1200V, 1700V SiC devices have been
commercialized. It is expected that the application requirements of 3300V
and 6500V, and even more than 10,000 volts will be rapidly improved in
the future, and then the SiC thick epitaxial wafers will be needed.
⚫ In order to obtain thick epitaxial wafers, fast epitaxial growth technology
will become the mainstream of technology development.
➢ Challenge
⚫ Device stability: especially the stability of bipolar SiC power devices. Due
to the existence of BPD dislocations in the epitaxial layer, under the
forward bias condition, the stacking fault defects caused by the BPD will
expand, leading to reduce carrier lifetime and drift in forward voltage.
⚫ Carrier lifetime: The current carrier lifetime of 100μm thick SiC epitaxial
layer is 1-2 μs, which cannot fully meet the manufacturing requirements of
high-performance SiC power devices, so it needs to improve carrier
lifetime.
➢ Potential solution
⚫ Optimize the growth process and improve the conversion efficiency of
BPD dislocation to TED dislocation in epitaxial growth.
⚫ Use the method of enhancing the carrier lifetime of the epitaxial layer,
such as high-temperature oxidation and annealing processes, to improve
carrier lifetime.
◼ The price of a unit area of epitaxial wafers
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➢ Development trend ( as shown in Fig1.5, Fig1.6)
⚫ The substrate accounts for more than 50% of the cost of the epitaxial
wafers. As the price of the substrate decreases and equipment, factory, and
labor costs will reduce as the equipment improves, the epitaxial price will
decrease. As the epitaxial quality requirements become more and more
stringent, the cost of research and development and yield loss will remain
at about 7%.
⚫ In the recent 5 years, the price of unit area will be reduced slightly with
the rapid promotion of 150 mm diameter substrate. With the price
reduction of equipment, factory, and labor, the price reduction of a unit
area of epitaxial wafers will be relatively fast.
Fig 1.5 Cost analysis of epitaxial wafers
Fig 1.6 The development trend of a unit price of the SiCsubstrate(RMB/cm2)
53%
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Cost Analysis of Epi-wafer
Raw Material
Equipment Cost
Clean Room Cost
Labor Cost
R&D Yield Losses
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2018-2023 2023-2028 2028-2033 2033-2038 2038-2043 2043-2048
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1.3.2 SiC power device
1.3.2.1 Structure and size
◼ SiC Schottky device
➢ Development trend: (as shown in Fig1.7[1], Fig1.8[2])
⚫ SiC Schottky devices are widely used in power factor correction (PFC)
circuits, which are the most important application areas for SiC devices,
with a share of more than 50%. By now, SiC devices mainly include pure
Schottky-contacted SBD devices and junction-barrier JBS devices with
p-type implants. The former is widely used in the low-voltage field, and
the latter is used in high-voltage applications. To meet the demand of surge
resistance, SiC Schottky device of JBS type is often used for power
conversion circuits.
⚫ The reverse recovery loss of SiC Schottky devices does not change with
temperature and forward current, so it can achieve fast recovery regardless
of the environment. Junction capacitance is the main indicator affecting its
charge and discharge loss, so the next step should be developing
low-capacitance SiC Schottky devices.
⚫ The specific on-resistance of SiC Schottky devices has been reduced to
1mΩ.cm2, and the forward voltage drop has been greatly improved. In
order to obtain a SiC Schottky device of lower conduction voltage drop, a
trench structure can be used to increase the effective Schottky contact area
or reduce the carrier conduction path (thinning the substrate).
⚫ To enhance the device reliability, packaging working under high
temperature is an important way to improve the efficient operation of SiC
Schottky devices. A part of the failure of SiC Schottky devices is due to
the mismatch of thermal expansion coefficients of the packaging materials
leading to the premature damage of the device. Therefore, optimizing the
device current sharing capability, improving packaging technology is the
future development trend.
➢ Challenge
⚫ Cost: As the area of SiC Schottky device chips continues to decrease,
reducing the cost of the device in the development process is an important
challenge.
⚫ Low forward voltage drop Schottky devices: As the static operating
capability increases, the on-resistance of the device must be reduced, so it
is necessary to obtain SiC devices with low dropout Schottky contact and
good wafer uniformity.
⚫ Low reverse leakage Schottky device, the edge termination can effectively
improve the breakdown characteristics and reduce the reverse leakage
current, so that the breakdown voltage of the device is more than 80% of
13
the ideal planar junction breakdown voltage.
⚫ High temperature operation: to improve the carrier drive capability of the
device, to optimize the internal heat balance of the cell, to improve the
heat dissipation capability of the device, to optimize the ohmic contact
reliability design of the device, and to improve the high temperature
resistance of the device.
➢ Potential solution
⚫ Optimize the internal cell layout and structure of the device with a new
terminal structure design.
⚫ Optimize the balance of the forward conduction resistance and reverse
breakdown of the devices using a low dropout Schottky contact design or
trench structure design.
⚫ Improve the high-temperature reliability of ohmic contact of the device.
Fig 1.7 The development of SiC Schottky device
14
Fig 1.8 The distribution of withstand voltage of SiC Schottky device
◼ SiC MOSFET device
➢ Development trend: (as shown in Fig1.9[3], Fig1.10)
⚫ The current mainstream SiC three-terminal device is MOSFET device.
The MOSFET is based on the control of the gate terminal to implement
turning on and turning off of the switching device, so as to meet the
requirements of high frequency and high power. It can replace the
conventional Si-based IGBT device in some fields, and the device
performance does not drift severely with operating temperature changes.
The on-resistance of the MOSFET has a positive temperature coefficient,
and the device performance does not drift severely with the change of the
operating temperature, so MOSFET is suitable for parallel operation.
⚫ The specific on-resistance of SiC MOSFETs can be reduced to 1mΩ.cm2.
The withstand voltage is mainly distributed in the medium voltage field.
SiC DMOSFET devices are used in more than 10kV. The chip area is more
than 8×8mm2 and is developing to 6 inches.
⚫ SiC UMOSFET has lower specific on-resistance than DMOSFET and has
better performance. The channel mobility of SiC non-polar plane is high,
and the channel structure MOSFET has higher cell integration. Therefore,
SiC UMOSFET become the focus of R&D and application in the medium
voltage field.
⚫ SiC MOSFET devices with integrated Schottky devices improve the
device's third quadrant operation while reducing overall chip area,
increasing device integration and reducing cost.
⚫ A SiC MOSFET device with an accumulated channel enhances the
forward conduction capability of the device and develops in large the
crystal size.
⚫ SiC MOSFET devices have characteristics of high-temperature and high
frequency-operation, but the high-temperature working potential of SiC
15
MOSFET device is not exerted due to the mismatch between the thermal
expansion coefficients of SiC and SiC chip’s lead and the limitations of
packaging materials and technologies. Selecting materials with excellent
insulation properties and high thermal conductivity as device packages can
effectively avoid thermal stress caused by temperature changes, which is
an important point for future SiC power device packaging technology.
➢ Challenge:
⚫ The SiC material can form an oxide layer by in-situ oxidation as a gate
dielectric layer, which has a high compatibility with the process of Si.
However, the process of SiC oxidation is much more complicated than Si
oxidation. Besides, high-density interface defects and interface trap
charges have a huge influence on carrier transport and recombination in
the interface channel of SiC-based MOSFETs, resulting in carrier loss and
device mobility degradation.
⚫ The gate dielectric of SiC MOSFET will change under high-temperature
conditions, causing the threshold voltage of the device to be unstable, and
the interface defect causes the gate leakage current of the device to rise.
⚫ The gate voltage driving of SiC MOSFET is different from that of Si
device. The former has asymmetry, usually +20V/-10V, so we should pay
special attention to the driver circuit design of SiC MOSFET device.
⚫ The breakdown electric field of SiC is high, so that the electric field in the
gate dielectric SiO2 is also strong in reverse operation, especially in the
trench MOSFET structure, the two-dimensional electric field
concentration of the groove angle reduces the stability of the device.
⚫ We can expand the capacity and reduce the cost of the device through
improving wafer yield control of SiC MOSFET, the on-chip and inter-chip
consistency of the device.
⚫ Improvement of the high-temperature and high-frequency reliability of
ohmic contact of devices.
16
Fig 1.9 Market share analysis of SiC MOSFET device
Fig 1.10 Market distribution of SiC MOSFET device in the future
1.3.2.2 Electrical properties
◼ SiC Schottky device
➢ Development trend of the device: (as shown in Fig1.11)
⚫ The structure of SiC junction barrier Schottky devices with p-type
implants will become more and more to meeting high power requirements
and improving the surge resistance of devices.
⚫ Cell design: including the effect of the integrated cell on chip current
density, heat distribution uniformity, breakdown point consistency and
chip capacitance. Common SiC Schottky diode cell topological layouts
17
include strip distribution, square lattice distribution, spherical lattice
distribution, etc. Among them, strip cell design is a relatively mature
technical means.
⚫ Junction termination extension (JTE), field plate (FP), etched mesas, and
combinations of them are used to reduce the reverse leakage current
characteristics of the device.
➢ Challenge:
⚫ It’s a contradiction between the blocking voltage and the on-resistance of
the power device. Therefore, we need through optimization of the
structure to design SiC Schottky diode with high blocking voltage and low
forward voltage drop.
➢ Potential solution:
⚫ A SiC Schottky device with a minimum on-conduction voltage drop and
good reverse blocking characteristics can be obtained by simulation using
a trench-type structure, a double-barrier metal contact, etc., in combination
with the process difficulty and repeatability.
Fig1.11 The blocking voltage of SiC Schottky device
➢ Development trend of reliability:
⚫ An important reliability issue for SiC Schottky devices is the reverse bias
leakage current of the device.
⚫ The conduction characteristics and reliability of SiC SBD devices and JBS
devices are well guaranteed after repeated surge current surges.
⚫ After high temperature and high-frequency operation, the electrical
properties of the device did not drift seriously.
➢ Challenge:
⚫ How to optimize the SiC Schottky device of higher performance, improve
the forward conduction and reverse blocking capability, ensure high
temperature and high-frequency reliability.
18
➢ Potential solution:
⚫ JBS diodes are less affected by thermal induced voltage surges and have a
higher reliability of thermal induced surge voltage.
⚫ For SiC SBD devices and JBS devices, reducing the self-heating effect of
devices and their impact on high voltage reliability is an important
research and development direction.
⚫ To optimize device structure and package form to reduce thermal
resistanceas the device can work at low temperatures.
◼ SiC MOSFET device:
➢ Development trend of the device: (as shown in Fig1.12[4], Fig1.13)
⚫ The development of SiC MOSFET device structure is similar to that of Si
devices. DMOSFET devices are the most mature SiC MOS devices at
present. The electrical properties of the devices are more stable, and the
gate oxide is effectively protected by the good shielding layer. The typical
cell size of SiC DMOSFET devices is 10μm. The device cell structure is
mostly strip-type cells, and other cell layouts such as rectangular cells,
square cells, diamond cells, etc.
⚫ Optimize device structure, reduce JFET resistance, drift region resistance,
channel resistance, substrate resistance, etc., thereby improving the
on-state characteristics of the device.
⚫ Junction termination extension (JTE), field plate (FP), etched mesas, and
combinations of them are used to optimize the device termination structure
and improve the breakdown characteristics of the device.
⚫ Optimize device cell layout and interlayer structure, reduce the gate
capacitance of the device so that to improve the dynamic characteristics of
the device
⚫ The cell gate integration can be further improved by using a trench gate
structure to form SiC UMOSFET. The typical cell gap of SiC UMOSFET
is 5 μm.
⚫ The new structure is used to reduce the gate dielectric field of the SiC
UMOSFET and improve the reverse blocking reliability of the device.
⚫ Optimize the design of the gate dielectric structure of SiC MOS devices,
reduce device gate-drain capacitance, gate-source capacitance, etc., which
can effectively improve the dynamic switching performance of the device.
➢ Challenge
⚫ How to get high-quality SiC MOS gate dielectric structure, improve the
forward turn-on gate bias and reverse turn-off gate bias capability of SiC
MOSFET devices is a major problem.
⚫ How to optimize the device channel layout, improve device channel
mobility, and thus reduce channel resistance.
⚫ How to reduce the gate capacitance of the device is an important project to
improve the high-frequency switching capability of SiC MOSFET devices.
⚫ How to effectively protect the trench gate dielectric of SiC UMOSFET.
19
➢ Potential solution
⚫ SiC MOS gate dielectric can use traditional SiO2 or high-k dielectric, but it
must reduce the gate leakage current of the device so as to improve the
gate control capability of the device.
⚫ Using a channel alignment technique to form a non-polar surface channel
to obtain a high mobility non-polar surface of SiC MOSFET device.
⚫ For the DMOSFET structure, the split-gate structure can be used to reduce
the gate contact area of the JFET region, thereby effectively reducing the
gate-drain capacitance, and the gate charge of the device is greatly reduced,
so that the dynamic switching performance of the SiC MOSFET device is
greatly improved.
⚫ For the UMOSFET structures, a bottom-thickened gate dielectric structure
can be used to reduce Miller capacitance and Miller charge, thereby
reducing the dynamic switching losses of SiC MOSFET devices.
⚫ It is common to implant a p-type shield on the bottom of the trench to
protect the structure of the trench gate dielectric. The current leading
technology is Rom's dual-trench structure, which implants a deep p-layer
to protect the oxide at the bottom of the gate through the bottom of the
source, and Infineon's single-channel shielded UMOSFET structure
optimizes the gap of the p-type shield to obtain SiC UMOSFET devices
with low on-resistance and high gate oxide reliability. We believe that the
structures of SiC UMOSFET are various in the future. The gate structure
will be adopted a more precise three-dimensional structure, and the oxide
layer at the bottom of the gate trench will be protected so that the static
conduction characteristics and the reverse blocking feature can be greatly
improved. At the same time, as the channel resistance of the SiC
UMOSFET decreases, the area of the SiC UMOSFET device of the same
current will be greatly reduced, so that the effective gate capacitance is
also proportionally decreased. Therefore, the dynamic performance of the
device will be significantly enhanced. In the future, the overall market
share of SiC MOSFET devices will maintain a steady increase of 30%,
and the UMOSFET structure in MOSFET devices will gradually expand
its market share.
20
Fig 1.12 Current current voltage level of SiC MOSFET
Chart1.1 Forecast of power device development
2020 2025 2030 2035 2040 2048
Schottky
diode V/I
600V~1700
V/~150A
600V~6500
V/~200A
600V~10kV
/~400A
PiN diode 10kv~18kV/
~10A
10kv~25kV/
~50A
10kv~30kV/
~100A
10kv~30kV/
~200A
10kv~30kV/
~300A
10kv~30kV/
~400A
MOSFET
V/Ω
600V~1700
V/~150A
600V~6500
V/~200A
600V~10kV
/~400A
GTO
V/I
10kv~30kV/
~50A
10kv~30kV/
~150A
10kv~30kV/
~300A
10kv~30kV/
~500A
10kv~30kV/
~1000A
IGBT
V/I
10kv~18kV/
~10A
10kv~25kV/
~50A
10kv~30kV/
~100A
10kv~30kV/
~200A
10kv~30kV/
~300A
10kv~30kV/
~400A
21
Fig 1.13 The specific on-resistance of SiC MOSFET
➢ Integrated device development of SiC MOSFET: (as shown in Fig 1.14[5])
⚫ Several applications of SiC MOSFET-based circuits, including switching
power supplies, adjustable speed drivers, etc., the excess current flowing
through the parasitic diodes within the MOSFET power device during the
operating cycle. When used as a front-end switch for a power converter,
the body diode of the power MOSFET acts as a flyback diode that flows
through half of the current during the power conversion cycle. The stored
charge of the SiC PN diode causes the MOSFET power device to generate
additional reverse recovery current, so the parasitic SiC PN junction diode
limits the device's safe operating area (SOA), turn-off loss, and switching
speed.
⚫ Due to the increased electrical performance of SiC chips, there is an
increasing demand for integrated manufacturing of devices. The so-called
SiC MOSFET integrated device refers to the technology of integrating SiC
MOSFET and SiC SBD into one cell for chip layout and optimization. The
high-frequency operation of the device in the first quadrant is still
controlled by the gate of the SiC MOSFET, while in the third quadrant, the
flyback operation is mainly performed by the internal Schottky device.
This saves the peripheral parallel diode to a certain extent, reduces the
chip area integration overall. It can also accelerate the reverse recovery of
the body diode, reduce the on-resistance of the device, improve the
device's figure of merit, and overall reduce the SiC MOSFET device and
Schottky device manufacturing costs.
⚫ Optimized structural design improves device performance by integrating
Schottky devices, such as rationally arranging the SiC Schottky contact
area and the MOSFET active area the current sharing design of the carrier
conduction path in the drift region, and the shielding design of the leakage
current during blocking. Enhance the functionality and efficiency of
individual cells in a semiconductor device through miniaturization and
integration of devices.
22
Fig 1.14 SiC module performance with integrated SiC MOSFET and SBD devices
1.3.2.3 Materials and processes
◼ SiC Schottky device
➢ Development trend of processes:
⚫ The contact of Metal and SiC semiconductor is the most basic and core
structure of SiC Schottky devices. It is the hub responsible for device
energy input/output. Corresponding to ohmic contact is Schottky contact.
SiC Schottky devices operate in the high-frequency, high-temperature
environment, and the electrical performance of SiC diodes will be
significantly affected. When used in extreme military or space
environments, the Schottky barrier of the SiC device is reduced after
irradiation, resulting in increased leakage current of the device during
reverse bias operation. The control of Schottky contacts is an important
process technology in the fabrication of SiC Schottky devices. To ensure
uniformity of lateral Schottky barrier of the device, to improve the
reproducibility of SiC Schottky devices
➢ Challenge:
⚫ Firstly, how to form a well-connected Schottky contact with the rectifying
effect. Secondly, how to adjust the interface state and the barrier height, so
that the reverse leakage of the SiC Schottky device can be reduced.
Thirdly, how to ensure the consistency of barrier height to increase wafer
throughput.
➢ Potential solution:
⚫ The forward current transport model of SiC Schottky diode is established
23
according to the regulation mechanism of different surface doping
concentration on SiC Schottky rectification characteristics. Study on the
electron transport mechanism of SiC surface under different process
conditions.
⚫ Develop new surface treatment technology to control the barrier height
and surface state of metal/SiC contacts. At present, Ti is a common metal
for SiC Schottky contact. As an alternative, the contact process of
Al-based metal and SiC interface needs more development.
⚫ Study the relationship between the barrier height of SiC Schottky devices
and the temperature field and radiation field. Research the dependence of
the ideal factor n on temperature. Improve the Schottky contact
inhomogeneity theory, including the influence of surface doping
concentration non-uniformity, the chemical reaction in the interface and
the non-uniformity of the surface state of Schottky contact in different
distribution ranges.
◼ SiC MOSFET device
➢ Development trend of processes: ( as shown in Fig 1.15)
⚫ The fabrication process of SiC MOSFET is much more complicated than
SiC Schottky devices, including n- and p-type ohmic contact process
techniques based on ion implantation, getting n- and p-type ohmic contacts
close to the epitaxial process. In the current mainstream SiC MOSFET
devices, the n-type specific contact resistivity is ≤5×10-5Ω.cm2, and the
p-type specific contact resistivity is ≤10-5Ω.cm2, but the performance
degradation is obvious during high-temperature aging. Then we believe
that in the future, in SiC ohmic contact process: n-type specific contact
resistivity ≤ 5 × 10-7 Ω.cm2, p-type specific contact resistivity ≤ 10-6
Ω.cm2, and during 100 hours 600℃ aging test, ohms contact resistivity
and the mechanical joint strength are not significantly degraded.
⚫ High activation rate surface and smoothing ion implantation doping
process technology. SiC is different from conventional Si-based devices,
which can be doped by diffusion methods. The impurity diffusion
coefficient in SiC is very small, the temperature at which the diffusion
condition is reached is very high, and the high temperature causes the SiC
material to be denatured. Usually, a high-temperature ion implantation
process is used. Currently, the active region doping of the SiC MOSFET
device including n-well and p-well, terminal, source area, base area, etc.
need the ion implantation process.
⚫ Gate oxygen oxidation and nitriding technology for SiC MOSFET.
Thermal oxidation growth gate SiO2 is the most mature technology on
silicon. SiO2 layer has the best compactness and pressure resistance.
However, there are C atoms in SiC, the aggregation and vacancy of C
atoms on the surface make the MOS interface have more interface states,
which is about 2-3 orders of magnitude higher than silicon. This is also a
technical difficulty of SiC MOS. Thermal oxidation above high
24
temperature (1300 °C) can effectively reduce deep level traps, while
oxidation or thermal oxidation annealing in NO, N2O atmospheres can
effectively passivate interface dangling bonds, thereby improving interface
states.
⚫ Physical and chemical mechanism and morphology control technology for
wide bandgap semiconductor etching. The trench type SiC MOSFET
device requires an etching process to replicate the sidewall morphology of
the mask at a certain ratio while ensuring a smooth surface and no
over-etched micro-grooves at the bottom of the sidewall. Especially for
high-voltage devices, these topographical parameters directly affect the
withstand voltage performance of the device. Failure to do so at any point
will result in partial premature breakdown. On the basis of ensuring the
above key indicators, it is also necessary to optimize the etching
uniformity in the wafer through process window optimization.
➢ Challenge:
⚫ Controlling the SiC gate-oxide thermal growth process and annealing
process technology, reducing the SiC MOS interface state and improving
the channel mobility are major challenges in enhancing the performance of
SiC MOSFET devices.
⚫ Lattice damage caused by high-dose and high-energy ion implantation,
activation efficiency at high temperature, and repair of lattice defects are
key processes in the fabrication of SiC MOSFET devices.
⚫ SiC trench etching technology and interface repair technology after
etching are important means to improve trench SiC MOSFET devices.
➢ Potential solution:
⚫ The N-atom passivation technology, P atom passivation technology, Sb
atom passivation technology, and high-temperature oxidation annealing
process are used to reduce the interface trap state. Improve channel
mobility and increase gate dielectric reliability. The high-k material such
as Al2O3, AlON is used as the SiC MOS gate dielectric, or the high-k/SiO2
composite material is used as the SiC MOS gate dielectric. The new oxide
annealing process for developing SiC non-polar surfaces is another way to
enhance the forward conduction performance of SiC MOSFET. At present,
the interface state density of the SiO2/SiC interface of conventional SiC
MOSFET is about 1012eV-1cm-2, and the channel field mobility is
30-50cm2/V.s. In the future, it is hoped that the interface state will be
reduced to 5×1011eV-1cm-2 or less by the new SiC oxidation process, and
the channel field mobility is increased to 100cm2/Vs or more.
⚫ Combined with the device preparation process, the effects of process
parameters such as temperature, time, temperature increase and decrease
rate and atmosphere on the activation of impurities and lattice recovery
process should be systematically studied. The process of impurity
activation and lattice recovery should be considered to analyze the roles
played by these factors. The effects of ion implantation and annealing
25
activation processes on the blocking ability, on-state resistance and
switching speed of SiC devices need to be investigated. At present, the
conventional energy for ion implantation of SiC MOSFET devices is 700
keV. We believe that SiC implantation can advance toward the range of
MeV energy, and the increase of injection energy can make us obtain a
special structure of SiC MOSFET devices, such as super junction
structures, which has greatly improved the overall performance of the
device. At the same time, the target of high-temperature high-energy ion
implantation of SiC is: surface roughness ≤ 5nm, injection activation rate
is not less than 90%, and the uniformity of annealing activation carrier
concentration is ≤ 10%.
⚫ Gate trench etching requires the formation of a good sidewall with less
roughness to reduce the reverse leakage characteristics of the SiC
MOSFET device. The gate trench needs to form a better collimation,
sub-trenching structure to improve the reverse breakdown reliability of the
device. Etch mask selection ratio and precise control of SiC etch rate:
adjusting etching power and chamber pressure control the morphology and
rate of etched SiC by adjusting the ratio of etching gas, such as
fluorine-based gas, oxygen, etc. SiC mild slope etching process: 4-inch
SiC mild slope ≤ 30 °, no micro-grooves, etch depth uniformity deviation
≤ 5%, surface roughness ≤ 5nm.
Fig 1.15 Channel mobility development of SiC
1.3.2.4 Packaging and heat dissipation
◼ SiC Schottky device
➢ Development trend of packaging
⚫ SiC is a revolutionary semiconductor material used in power electronics.
Compared to Si Schottky devices, its key features include superior
26
switching performance, no reverse current, and temperature that hardly
affects switching behavior and wide operating temperature range -55 ° C -
175 ° C. However, as the on-resistance of SiC Schottky devices continues
to decrease, the packaging requirements for SiC Schottky devices are
becoming higher and higher. Due to the fact when Schottky diodes operate
under high current conditions, it will have significant heating effects so
that the reliability of the device will be affected. With the application of
high-power SiC Schottky diodes, device packages related to lowering
thermal resistance and maintaining good heat dissipation are receiving
more and more attention.
➢ Challenge:
⚫ While improving the miniaturization of the device, how to reduce the
thermal resistance of the internal chip to the pin, effectively improve the
heat dissipation area inside the device, and make up for the heat
dissipation defect of the internal isolation layer are important challenges
for the packaging and heat dissipation of the SiC Schottky device.
➢ Potential solution:
⚫ Improve device package design, including packaging materials, structural
improvements.
⚫ Selecting materials with excellent insulation properties and high thermal
conductivity as the substrate material of the device package such as
aluminum nitride, aluminum oxide, etc. which can transfer the power
consumption heat source of the chip well. Materials with a thermal
expansion coefficient close to SiC can effectively avoid thermal stress
caused by temperature changes.
⚫ Select a more reliable patch material to bond the silicon carbide chip to the
substrate. Common materials such as Ag/Ag nanoparticles/Ag glass,
Ag-Au alloy materials, etc.
⚫ Select a bonding metal material with a melting point greater than 600 °C,
such as Al, Au, Pt, etc. Generally, the bonding metal material should be
consistent with the electrode metal material of the SiC Schottky device, so
that internal diffusion of the metal will not happen and the structure is
stable.
◼ SiC MOSFET device
➢ Development trend of packaging: ( as shown in Fig 1.16[6] )
⚫ As the size of the chip shrinks, the power density of SiC MOSFET devices
increases, which makes the requirements of parasitic inductance and
capacitance of the package more stringent. Since the SiC MOSFET
operates in the high-frequency environment, and the gate dielectric of the
device is susceptible to electrical stress leading to degenerate. Therefore,
the device package of the SiC MOSFET should be distinguished from the
packaging technology of the conventional Si-based MOSFET.
⚫ The packaging material also brings lead resistance. Reduce SiC MOSFET
27
gate resistance, minimize switching energy consumption, to improve
device maximum switching frequency, stability, and short-circuit
tolerance.
⚫ Thanks to the improvement of the heat dissipation capability of the
package and the characteristics of SiC high-temperature operation and
high-temperature packaging technology, the power density of SiC
MOSFETs will continue to increase significantly in the future. The
integrated package of SiC SBD device and SiC MOSFET device can
greatly reduce the forward voltage drop of the internal diode, achieve
lower loss, and reduce the number of components, thus achieving chip size
miniaturization.
➢ Challenge:
⚫ In addition to the same problems faced by SiC Schottky devices, SiC
MOSFET device packages must also face the challenges of gate oxide
films that are prone to failure.
➢ Potential solution:
⚫ Improve the internal package gate contact resistance of the device,
improve the consistency and high frequency of device switching control.
⚫ Reduce parasitic inductance, improve power cycle capability and
anti-interference of electrical oscillation of dI/dt, dV/dt. At present, the
electrical oscillation of most SiC MOSFET causes the operating voltage of
the gate dielectric to exceed the rated +20/-10 range, thus causing the
device to fail.
⚫ High-temperature packaging technology with high thermal conductivity
and high thermal expansion matching. Packaging materials must have
operating characteristics of high temperature and high electric field.
⚫ Improved EMI capability and self-heat management performance.
⚫ Use SiC MOSFET 4-lead package technology, which provides additional
emitter terminals to reduce source stray inductance, to increase the
switching frequency of the device, and reduce gate dielectric impact on
SiC MOSFET devices.
28
Fig 1.16 Materials that can be used in SiC power device packages in the future
1.3.2.5 Reliability
◼ SiC Schottky device
➢ Development trend of reliability:
⚫ Due to its high thermal conductivity and large band gap, SiC materials
have strong application potential under high-temperature conditions.
However, due to various problems of SiC material quality and process,
SiC Schottky devices still face various reliability problem.
⚫ When the SiC Schottky device is in reverse bias, the electron emission
from the metal to the semiconductor dominates. Ideally, the reverse
current is a constant value, but in actual cases, the device has a large
leakage current. With the increase in temperature and the number of
switching, this leakage will lead to the increased power consumption of
the circuit, and it will cause thermal out of control .
⚫ The turn-off loss of the SiC JBS Schottky device is much higher at 300 °C
than usual, while the turn-off loss of the SBD Schottky device does not
change much with temperature. However, JBS Schottky devices have
better surge voltage reliability, while SiC SBD devices experience
repeated surge current surges, the device's ability to withstand surge
voltages decreases, and the device's turn-on voltage drop rises.
⚫ The package type has an important influence on the reliability of SiC
Schottky devices. The forward voltage drop and reverse bias leakage of
the SiC Schottky device in the TO220–Green A package after the
29
1000-hour high-temperature anti-aging experiment are stable. However,
the forward voltage drop and reverse bias leakage of the SiC Schottky
device in the TO220–STD package after the 100-hour high-temperature
anti-aging experiment change a lot, and the device fails.
◼ SiC MOSFET device
➢ Development trend of reliability:
⚫ Although research on SiC MOSFET devices has been around for 20 years,
the implementation of high-reliability MOS-based SiC power devices
faces significant physical challenges due to the presence of tunneling
currents in the oxide layer. This tunneling mechanism causes carriers to be
emitted into the dielectric and induces time-dependent dielectric
breakdown (TDDB) and Fowler–Nordheim tunneling.
⚫ SiC MOSFET devices operate in high-energy particle environments,
which can cause vacancies, gaps, and other related defects. The energy
states induced by these defects affect the electrical properties of materials
and devices. Exposure to 100k rad MOS capacitors (n-type epitaxial,
oxide thickness is 67.5nm), the interface state density changes little, but
produces a flat-band voltage shift of about -1.2 V, due to the combined
effect of trapped charge of radiation-induced oxides and the trapped
charge of the deep level interface (trapped by hole). After the irradiated,
the interface state density of the device has a large increase.If the radiation
dose is changed from 100 to 600 kilo cd, the calculated interface state
densities are 6×1011 eV-1.cm-2 and 1.3×1012 eV-1.cm-2, respectively.
⚫ At 375 °C, the SiC MOS capacitor formed by thermal oxygen still has
intrinsic reliability. When the electric field is less than 3.9 MV/cm, the
working life can reach 100 years. The results show that the barrier height
of 4H-SiC/SiO2 is 2.57 eV (room temperature) and 2.36 eV (200 °C),
which does not change sharply with temperature. For SiC MOSFET
devices, the high-temperature stress reliability is greatly reduced compared
with the MOS capacitor because the subsequent process has undergone ion
implantation annealing and a terminal oxide layer on the periphery of the
device. At 175 °C, 3 MV/cm, the dielectric breakdown test of 2 KV
DMOSFET can have an average life of up to 100 years, about two orders
of magnitude lower than MOS capacitors. Reliability under high thermal
stress also is exhibited by the stability of the MOSFET threshold voltage
and the magnitude of the reverse leakage current. Positive bias causes a
positive shift of threshold voltage, negative bias moves negatively, and
increases with offset amplitude.
⚫ The thermal stress failure mechanism of SiC MOSFET devices is different
from that of Si-based. The latter is mostly due to the physical reasons of
the device materials. The former is mostly caused by structural design
defects such as termination structures. If the design can be optimized on
the structure and package, the material properties of the SiC wide band
30
gap can be fully utilized and the thermal stress reliability can be improved.
The superiority of SiC MOSFET devices over Si MOSFET devices is also
reflected in higher frequencies and higher load currents. The same
problem faced by the former is that the repeated load power consumption
changes cause the periodic change of the junction temperature of the
device, which causes thermal stress damage to the inside of the package of
the SiC-based MOSFET. The lifetime of high-voltage SiC power
MOSFET is also subject to degradation of some electrical and mechanical
interconnects, such as solder joints, bond wires, and the link between tube
and core. This degradation mechanism is by a mismatch in the thermal
expansion coefficient at the interface or a thermoelectric stress generated
by temperature fluctuations during high-frequency operation.
1.3.3 Si-based GaN epitaxy and power devices
1.3.3.1 Si-based GaN epitaxy
➢ Development trend: (as shown in Fig1.17)
⚫ The marketization process of Si-based GaN power electronic devices
requires the cost of material epitaxy to decrease.
⚫ The size of the Si substrate used for GaN epitaxy in the next 30 years will
be extended from 6 inches to 8 inches in the next 5 years and will expand
to 12 inches or even 18 inches in the next 10-15 years.
⚫ In the case of gradually grasping the mechanism of epitaxial leakage and
the influence mechanism on the dynamic performance of the device, the
epitaxial quality is continuously improved on the basis of reducing the
epitaxial thickness. For example, the epitaxial thickness suitable for 650 V
products is thinned from the currently used ~5 μm to ~ 3 μm.
➢ Challenge:
⚫ Stress control and yield for large-scale epitaxy.
⚫ Uniformity of large-scale epitaxy.
⚫ The long-term effects of epitaxial parameters on device dynamic
performance and reliability are still unclear.
⚫ Potential solution:
⚫ Stress control relies on in-situ detection and stress compensation during
epitaxial growth.
⚫ Uniformity depends on the upgrading of epitaxial equipment and accurate
modeling of growth dynamics.
⚫ The effect of epitaxial parameters on device performance and reliability
depends on the accumulation of data.
31
Fig 1.17 Development trend of 650 V/200 V Si-based GaN epitaxy
1.3.3.2 Si-based GaN power device
◼ Withstanding voltage level of the device
➢ Development trend: (as shown in Fig1.18)
⚫ The withstanding voltage level of Si-based GaN power electronic devices
is expected to increase from the current 600/650 V to 1200 V in the next
5-10 years, and then will be in a stable state, mainly due to both technical
and market factors; vertical GaN power electronics are more subject to
cost, so no market forecast is made here.
⚫ 600/650 V products have the largest market share, and it is predicted that
600/650 V products will account for 80% of the GaN market share after
market formation, while 900/1200 V devices and 200 V devices account
for 10% each.
➢ Challenge:
⚫ Technical: There are more uncertainties in the dynamic performance and
reliability of GaN power electronic devices under higher electric fields.
⚫ Market: With the continuous optimization of GaN power electronic device
development and production control, the cost is gradually reduced; but due
to the cost reduction of large-size SiC substrate, the mainstream
application of GaN power electronic devices is 1200 V and below.
➢ Potential solution:
⚫ In the 900 V and 1200 V areas, it is necessary to increase the epitaxial
thickness to increase the withstanding voltage in the vertical direction,
while optimizing the field plate structure and regulating the electric field
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distribution.
Fig 1.18 Development trend of withstand voltage level of Si-based GaN power electronic devices
◼ Structure of device
➢ Development trend: (as shown in Fig1.19)
⚫ At present, there are only a handful of IDM companies in the industry to
promote cascading devices. Many companies (especially design
companies) promote enhanced devices based on the foundry model. In
terms of product performance, the cascode cascading device in practical
applications above 600 V is easy to achieve marketization in the short term,
and its market share will occupy 50% in 10 years. With the mature of
E-mode device technology, the share of cascode will be reduced and at last,
it will only have part of the share of 1200V.
⚫ Based on the need to further reduce costs and improve performance,
E-mode devices will occupy the majority of the market share after the
technology matures, but the time required will be quite long.
➢ Challenge:
⚫ Cascaded devices face the problem of packaging cost and the problem that
the single-tube current of multi-chip micro-modules cannot be further
increased.
⚫ Enhanced devices are more subject to fundamental and functional issues,
such as threshold voltage, gate withstanding voltage is not high enough,
threshold voltage drift, hard drives in applications, etc.
➢ Potential solution:
⚫ Cascaded devices increase output current and output power in parallel.
⚫ Enhanced devices require the introduction of a more withstand voltage
gate dielectric layer and a smaller interface charge to get higher threshold
voltage and gate withstanding voltage.
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⚫ Develop dedicated drivers for enhanced devices or different drive methods
such as current drive.
Fig 1.19 Development trend of market share of different device structures
in the GaN power electronics
◼ The current density of the device
➢ Development trend: (as shown in Fig1.20)
⚫ Based on the requirements of both device performance and control cost,
the current density of the device is continuously increased, that is, the
Ron*Qg or the characteristic resistance Ron*Area of the device is
continuously reduced. In the next 30 years, the current density of 650 V
devices will be doubled from the current 1.8 A/mm2, and the current
density of 100 V devices will now increase from 4.1 A/mm2 to 6.5 A/mm2.
➢ Challenge:
⚫ The increase in current density makes high demands on the heat
dissipation of the device.
⚫ The size of the device's field plate and the reduction of the spacing
between the electrodes pose a high challenge to device reliability.
➢ Potential solution:
⚫ Device cooling depends on new packaging technologies and substrates
with higher thermal conductivity, heat sinks, etc.
⚫ Increased investment in the study of reliability to establish failure models
and device life-dependent size models.
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Fig 1.20 Current trends in GaN power electronics current density
◼ Chip package form
➢ Development trend: (as shown in Fig1.21)
⚫ The main form of power electronics package is TO series (including
TO-220/247, etc., major manufacturers are Transphorm, Panasonic, etc.),
SMD series (including QFN/DFN, etc., major manufacturers are
Transphorm, Panasonic, etc.) and module package. In addition to the
above-mentioned conventional forms, the package form of GaN chips
currently available on the market includes low-voltage devices LGA
packages (EPC), Power IC packages with integrated drivers and other
components (TI, Navitas, etc.) and others (such as GaN Systems
embedded).
⚫ TO package as the traditional mainstream packaging form of power
electronic devices is also the main packaging form of GaN devices. In the
current, GaN power electronic device market is not fully opened, all kinds
of new packages are emerging. The market share of TO package will be
from the current 30% to 45% with the update of mainstream power
electronics applications.
⚫ The inductance of the traditional SMD surface mount package is slightly
smaller than that of the TO package, but the heat dissipation capability is
slightly worse. About 20% of the current market share will shift with the
high-frequency application technology to the power integration type, that
is, the Power IC package form.
⚫ Integrated driver-type Power ICs can take full advantage of the
high-frequency characteristic of GaN devices. As the technology of
high-frequency applications continues to mature, its market share will rise
to 10% in the next 30 years.
⚫ The market share of low-voltage products below 200 V will be squeezed
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to below 10% as the mainstream 600/650 V market matures.
⚫ The market share of module applications will exceed 12% with the
increase in application requirements above 5 kW and the maturity of the
technology.
⚫ Other packaging forms will maintain a market share of around 10%. Some
existing products are difficult to break through the limitations of thermal
performance. There is limited room for development, but I believe there
will be more complete package forms.
➢ Challenge:
⚫ As the current density or power density of the device increases, the heat
dissipation of the chip will hinder the improvement of system integration.
⚫ In high-frequency applications, the conversion efficiency is relatively low,
and the power dissipation capability of the Power IC will cause negative
feedback on the conversion efficiency.
➢ Potential solution:
⚫ Device cooling depends on new packaging technologies and substrates
with higher thermal conductivity, heat sinks, etc.
⚫ For high-frequency applications above 5 MHz, develop dedicated drivers
and low-loss cores for GaN devices, and optimized layout designs to
improve system efficiency.
Fig 1.21 Development trend of chip packaging form
◼ Reliability
➢ Development trend:
⚫ The chip downstream industry has strict requirements on device reliability.
This is another important factor that restricts the market development of
GaN devices in addition to cost performance.
⚫ GaN device vendors have tested reliability at different levels, and the
published data shows that the device can work reliably for a long time.
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⚫ At the beginning, a series of tests were conducted on the long-term
withstanding voltage and environmental resistance of the device using the
JEDEC standard commonly used in Si devices, including high-temperature
reverse bias, high acceleration temperature, and humidity, temperature
cycling, power cycling, and life expectancy of high-temperature storage,
etc.. High-temperature reverse bias is the key test for evaluating the
withstand voltage of the device (temperature = 150℃, drain voltage = 80%
of the voltage class, time 1000 hours). In 2012-2013, Transphorm
announced that its 600 V GaN product is the first company in the world to
pass the JEDEC standard test; so far, TSMC is another company that has
announced that its product line is certified by this standard.
⚫ For automotive electronics, Transphorm announced in 2016 that its
products have passed the AEC-Q101 standard test, which has more test
content and more stringent requirements on withstanding voltage of the
device. For example, the drain voltage applied in the high-temperature
reverse bias test is classified voltage. This standard lays the foundation for
GaN devices to enter the automotive electronics market.
⚫ In addition to the existing JEDEC and AEC-Q101 standards mentioned
above, GaN device suppliers have released more application data for
industry concerns about new products, such as Transphorm's release the
3000-hour HTOL data of GaN devices with 200V to 400V boost circuits at
175℃ junction temperature, which indicates that the conversion efficiency
in the booster circuit remains unchanged during the 3000 hours of
high-temperature application test, manifest that the performance
parameters of the surface GaN device are less changed in the test.
⚫ Further, by performing accelerated aging tests on GaN devices at higher
voltages or higher junction temperatures, the average lifetime of the
products at 650V and 150℃ junction