MRS Spring Symposium, Tutorial: Advanced CMOS—Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University of California, Santa Barbara [email protected] 805-893-3244, 805-893-5705 fax
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MRS Spring Symposium, Tutorial: Advanced CMOS—Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco
Technology Development for InGaAs/InP-channel MOSFETs
Mark Rodwell University of California, Santa Barbara
[email protected] 805-893-3244, 805-893-5705 fax
Scope of Presentation
Topic of discussion is channel materials for CMOS...the potential use of III-V materials...and their advantages and limitations
To understand this, we must examine in some detailMOSFET scaling limits
Z th O d Zeroth-Order MOSFET O iMOSFET Operation
Bipolar Transistor ~ MOSFET Below Threshold
beV ceV
cI
)/exp(al)(exponenti thermalison distributienergy emitter Because
bec kTqVI ∝
voltagecollector with little variesit through pass base reaching electrons allAlmost
cI→
Field-Effect Transistor Operation
gatesource drain
g
Positive Gate VoltagePositive Gate Voltage→ reduced energy barrier→ increased drain current
FETs: Computing Their Characteristics
chdC /~ DACgs ε chd−
/ where/ electrongd vLQI == ττ
gs
dschdgsgs VCVCQ δδδ −+=
ττδδδ / and / where chdgdgsmdsdsgsmd CGCgVGVgI −==⋅+⋅=
FET Characteristics
ID
increasingVGS
hdC/~ DAC ε
GS
chdC − / DACgs ε
VGVgI δδδ ⋅+⋅=
VDS
dsdsgsmd VGVgI δδδ ⋅+⋅=
LCGC /// electrongchdgdgsm vLCGCg / / / === − τττ
FET Subthreshold Characteristics
kT)()( δδ
s
s
ox
schanneloxgate
Vq
kTqnqn
CqnVVV
ithlinearly wvarieschargechannel:drivegateStrong
)()( ⋅+=+=δδδδδ
gs
gs
VV
lly withexponentia variescharge channel :drive gateWeak ithlinearly wvarieschargechannel :drive gate Strong
Classical Long-Channel MOSFET Theory
:sAssumption
)( .channel in field lateral Moderate1)
:sAssumption
xnE
∂
*/ :channeloff-pinchedofendat city Exit velo3)
)()(usiondrift/diffby modeledTransport )2
mkTvvxxnqDExnqJ
thermalexit
nn
==
∂∂
+= μ
/:c a eop c edoe datc tyt ve o3) mkvv thermalexit
Classic Long-Channel MOSFET Theory
t t t
Idmobility-limited
ID
Ohmi
cconstant-current
velocity-limitedincreasingVGS
VgsVthVDS
c rrentlimitedmobilit ExpressiondGeneralize
:saturation nlarger tha voltagesdrainFor
gthgsgoxD LVVWcI 2/)(current limitedmobility
2, −=
−
μμ1
ExpressiondGeneralize2
=⎟⎟⎞
⎜⎜⎛
+⎟⎟⎞
⎜⎜⎛
DD
II
II
)(current limitedvelocity
, thgsexitgoxvD VVvWcI −=− ,,
⎟⎠
⎜⎝
⎟⎠
⎜⎝ μDvD II
Classic Long-Channel FET : Far Above Threshold
IdΔVΔV
VgsV gsVth
/h1/)(for )( thgsthgsexitgoxD
LVVVVVVVvWcI
Δ
>>Δ−Δ−−≈
μ/ where gexitLvV =Δ
Exponential, Square-Law, Linear FET Characteristics
Relevance of DC Parameters
Digital circuit speed largely controlled by on-state current
Standby power consumption controlled by off-state current
Dynamic power consumption controlled by supply Voltage
→ Examine VLSI Power & Delay Relationships
Z th O dZeroth-OrderS fVLSI Performance
Analysis
CMOS Power Dissipation & Gate Delay
delayGateC
dominatesusually ecapacitanc g wirin2/)(2/
delayGate++=≈ onddPFETNFETwireonddtotalgate IVCCCIVCτ
Vdd
Cwire
PFETC
onI
y)probabilitswitching(frequency
: ndissipatiodower Dynamic2
⋅⋅= ddtotald
VCPNFETC y)probabilitswitching(frequency2
=dynamicP
IVdd
thonoff nkTqVII −> )/exp(/current state Off offI dd
ddoffstatic VIP ⋅>on DissipatiStatic
kTqVonddstaticddwiredynamic
theIVPpfVCP /2 ~ ~ :ndissipatio dynamic and static between Tradeoff −⋅
Why Large Current Density is Needed
S D S D S D S
G
Wgg nWW
n widthtotal widthof each
fingers, 6 withFET=→
=
G
Wg
C ,delay at drive To τwireC
Vdd
Cwire
PFETC
onI
.2/current requires τddwired VCI =
NFETC needed. are FETslarge small, is If gd /WI. large wireslong FETsLarge wireC→→
Device Requirements
High on-state current per unit gate width
Low off-state current→ subthreshold slope
Low device capacitance; but only to point where wires dominate
Low supply voltage: probably 0.5 to 0.7 V
What Are Our Goals ?
Low off state current (10 nA/μm) for low static dissipationLow off-state current (10 nA/μm) for low static dissipation→ good subthreshold slope → minimum Lg / Toxlow gate tunneling, low band-band tunneling
Low delay CFET ΔV/I d in gates wheretransistor capacitances dominate.~1 fF/μm parasitic capacitances→ low Cgs is desirable,
but high Id is imperativeg d p
Low delay C ΔV/I in gates whereLow delay Cwire ΔV/Id in gates wherewiring capacitances dominate.large FET footprint → long wires between gates→ need high Id / Wg ; target ~5 mA/μm @ ΔV= 0.7V
target ~ 3 mA/μm @ ΔV= 0.5V
I i FETImproving FETsby Scalingby Scaling
Simple FET ScalingGoal double transistor bandwidth when used in any circuit
→ reduce 2:1 all capacitances and all transport delays→ keep constant all resistances, voltages, currents
All lengths, widths, thicknesses reduced 2:1
S/D contact resistivity reduced 4:1
ε~/d WC
oxgm TvWg /~/ ε If Tox cannot scale with gate length, Cparasitic / Cgs increases,
ε/ ggd WC
oxgggs TLWC /~/ ⋅ε
ε~/ gfgs WC
gm / Wg does not increasehence Cparasitic /gm does not scale
, gfgs
subcgsb TLWC /~/ ⋅ε
FET scaling: Output Conductance & DIBLeffects)D.O.S.neglectsexpression( gsC )gp( gs
hd WC ε~/~ TLWC ε gchd WC ε−
dhdd VCVCQQI δδδτ +== where/
/ oxgggs TLWC ε
dschdgsgsd VCVCQQI δδδτ −+== where/
transconductance output conductance
→ Keep Lg / Tox constant as we scale Lg
FET Scaling LawsGL
Changes required to double transistor bandwidth:( )GW widthgate
parameter changegate length decrease 2:1
Changes required to double transistor bandwidth:
gate dielectric capacitance density increase 2:1gate dielectric equivalent thickness decrease 2:1channel electron density increase 2:1channel electron density increase 2:1source & drain contact resistance decrease 4:1current density (mA/μm) increase 2:1
nm Transistors: it's all about the interfaces
Metal-semiconductor interfaces (Ohmic contacts):very low resistivity
Dielectric-semiconductor interfaces (Gate dielectrics):very high capacitance density
Transistor & IC thermal resistivity.
FET Scaling LawsGL
Changes required to double transistor bandwidth:( )GW widthgate
parameter changegate length decrease 2:1
Changes required to double transistor bandwidth:
gate dielectric capacitance density increase 2:1gate dielectric equivalent thickness decrease 2:1channel electron density increase 2:1channel electron density increase 2:1source & drain contact resistance decrease 4:1current density (mA/μm) increase 2:1
What do we do if gate dielectric cannot be further scaled ?
Why Consider MOSFETs with III-V Channels ?
If FETs cannot be further scaled, instead increase electron velocity:
III-V materials → lower m*→ higher velocityId / Wg = qnsv Id / Qtransit = v / Lg
III V materials → lower m → higher velocity( need > 1000 cm2 /V-s mobility)
Candidate materials (?) In Ga As InP InAs ( InSb GaAs)
Difficulties:
Candidate materials (?) InxGa1-xAs, InP, InAs ( InSb, GaAs)
High-K dielectricsIII-V growth on Sibuilding MOSFETsbuilding MOSFETslow m* constrains vertical scaling, reduces drive current
III-V CMOS: The Benefit Is Low Mass, Not High Mobility
h h ldbfdhdiff id ifSi l :thresholdabovefar ate,nondegenertheory,diffusion -drift Simple
)/(~ where 1/2*mkTvv thermalinjection = )( VVVvWcI thgsinjectiongoxD Δ−−≈
Idμ/ginjectionLvV =Δ
thatEnsure )( VVV −<<Δ⇒
VmV700
that Ensure
~
)( thgs VVV <<Δ⇒
VgsVthlow effective mass → high currentslow effective mass high currents
mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg
III-V MOSFETs for VLSI
Wh t i it ?What is it ?MOSFET with an InGaAs channel
Why do it ?l l t ff ti hi h l t l itlow electron effective mass→ higher electron velocitymore current, less charge at a given insulator thickness & gate lengthvery low access resistance
What are the problems ?low electron effective mass→ constraints on scaling !must grow high-K on InGaAs, must grow InGaAs on Si
Device characteristics must be considered in more detail
III V MOSFETIII-V MOSFETCharacteristicsCharacteristics
Low Effective Mass Impairs Vertical Scaling
Shallow electron distribution needed for high gm / Gds ratio, l d i i d d b i l ilow drain-induced barrier lowering.
2*2 ./ 2*2wellTmL∝
For thin wells,only 1st state can be populated
Energy of Lth well state
only 1st state can be populated.For very thin wells,
1st state approaches L-valley.
Only one vertical state in well. Minimum ~ 5 nm well thickness.→ Hard to scale below 22 nm Lg.
Semiconductor (Wavefunction Depth) Capacitance
energy state Bound./ 2*2
wellwell TmLE ∝
123
V)
Tsemi
ecapacitanctor Semiconduc
-2-101
Ener
gy(e
VsemiTc /
p
torsemiconduc ε=
-4-3
0 50 100 150 200 250Y (Ang.)
Density-Of-States Capacitance
)//( 2* hπnmnEE swellf =−motion) nalbidirectio(
2*2 /h h
dosswellf cVV /ρ=−
and n is the # of band minima
22 / where hπnmqcdos =
Two implications:- With Ns >1013/cm2, electrons populate satellite valleys
Fischetti et al, IEDM2007
- Transconductance dominated by finite state densitySolomon & Laux , IEDM2001
Current Including Density of States, Wavefunction Depth
h h ldbfdhdiff id ifSi l :thresholdabovefar ate,nondegenertheory,diffusion -drift Simple
)( VVVvWcI thgsthermalgeqD Δ−−≈
IDOSoxeq /c /c /c/c 111 1 where torsemiconduc ++=
Id
VgsVth...but with III-V materials, we must also consider degenerate carrier concentrations.
Current of Degenerate & Ballistic FET ...) Asbeck, , FischettiSolomon, Laux,Natori, , Lundstrom(
dHi hl
motion) ional(unidirect 2//:states ofDensity 2*⋅=fs mndEdN πh
( )/)(l ii
),)(2/( :density electron :degenerateHighly
2/1*
2* −⋅= cfs EEmnn πh
( ).)3/4( : velocityelectron ean M
,/)(2 : velocity ermi F 2/1*
=
−=
f
cff
vvmEEvπ
( ) ( )/)(2
:densityCurrent 2/32/1*2/52/3 −⋅
⎟⎞
⎜⎛ f qEEmnq ( ) ( )
mA
/)(32
2/32/1*
22
⎟⎞
⎜⎛ −
⎟⎞
⎜⎛⎟⎞
⎜⎛
⎟⎟⎠
⎞⎜⎜⎝
⎛==
cf
cfs
EEm
qEEmnqvqnJ
π h
eV 1mmA84
0⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⋅= cf
mmn
μ
2D vs. 1D Field-Effect Transistors in Ballistic LimitDrain
mAmAmA
)04.0/( channel InGaAs FET;-2D2/32/32/1*
0*
⎞⎛⎞⎛⎞⎛⎞⎛⎞⎛
=
EEEEm
mm
Id
gateE
tor.semiconduc inshift levelFermieV0.3for
m
mA8.2eV 1m
mA17eV 1m
mA840 μμμ
=⎟⎟⎠
⎞⎜⎜⎝
⎛ −⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛ −⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛≅ cfcf EEEE
mmJ
Lg
Wg gate
g
Source
Id
Drains
d
gateE S78/2 eV, 37.0
*2
pitchnm 6@wellsInGaAsnm5 FETs;-1DofArray
2,2
22
μπ==== wellm
wellwell hqg
TmE h
Lg
Wg gate
torsemiconduc inshift level FermieV 0.3for m
mA9.3eV 1m
mA13eV 1nm 6
A 78μμ
μ=⎟⎟
⎠
⎞⎜⎜⎝
⎛ −⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛ −⎟⎠⎞
⎜⎝⎛= cfcf EEEE
J
Sources
2D FET vs. Carbon Nanotube FET
Drain
mA82mA17
)04.0/*( channel InGaAs FET;-2D2/3
0
⎟⎟⎞
⎜⎜⎛ −⎟⎟⎞
⎜⎜⎛
=
cf EEJ
mmId
Drain
gate
tor.semiconduc inshift level FermieV 0.3for
, m
8.2eV 1m
17μμ
=⎟⎟⎠
⎜⎜⎝⎟⎟⎠
⎜⎜⎝
≅ cfJ
L
Wg gate
Lg
Source
Drains
mAmAA78
S78/2 pitch nm 5 nanotubes, carbon ofArray
2,
μ
μ
⎟⎞
⎜⎛ −⎟⎞
⎜⎛
⎟⎞
⎜⎛ −⎟⎞
⎜⎛
==
ff
tubem
EEEE
hqggate
torsemiconduc inshift level FermieV 0.3for m
mA7.4eV 1m
mA5.15eV 1nm 5
A78μμ
μ=⎟⎟
⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛⎟⎠⎞
⎜⎝⎛= cfcf EEEE
J
Lg
Wg
Sources
Ballistic/Degenerate Drive Current vs. Gate Voltage
More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007
Drive Current in the Ballistic & Degenerate Limits
( ) 2/1*2/3⎞⎛⎞⎛ ( )
( ) 2/3*,
2/1*2/3
)/()/(1 where,
V 1mmA84
ooxodos
othgs
mmnccmmnK
VVKJ
⋅⋅+
⋅=⎟⎟
⎠
⎞⎜⎜⎝
⎛ −⋅⎟⎟⎠
⎞⎜⎜⎝
⎛⋅=
μ
0 25
0.2
0.250.7 nm, n=6 0.4 nm, n=6
Error bars on Si data points correct for (Ef-Ec)>> kT
0.15
K
0.8 nm, n=1 n = # band minimacdos,o = density of
(Ef Ec) kT approximation
0 0
0.11.0 nm, n=1
,states capacitance for m*=mo & n=1
0
0.05
EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well)
0.01 0.1 1m*/m
o
High Drive Current Requires Low Access Resistance
sidewall
metal gategate dielectric
source contact drain contact
barrier
quantum well / channelN+ source N+ drain
source contact drain contact
current, drive onimpact 10% For <
substrate
1.0)/( <− thDDSD VVRI
V 5.0)( @ mmA/ 3~/Target V3.0)(@mmA/5.1~/Target
μ
μ
=−
=−
thDDgD
thDDgD
VVWIVVWI
m 2015 μ−Ω−<→ gsWR
M i l S l iMaterials Selection;What channel material What channel material
should we use ?should we use ?
Common III-V Semiconductors B. Brar
1350
450
GaSb770
AlSb1550
1350 200
500450
250
InGaP1900InSb
AlAs2170
InAs
770GaAs1420 InGaAs
760
InAlAs1460 InP
1350200
1900220
2170
360
200
150
550170
200
6.48 A lattice constant
6.48 A lattice constant 5.65 A lattice constant;grown on GaAs
5.87 A lattice constant;grown on InP
Semiconductor & Metal Band Alignments M. Wistey
Materials of Interest
Source: Ioffe Institutehttp://www.ioffe.rssi.ru/SVA/NSM/Semicondrough #s only
material Si Ge GaAs InP In0.53Ga0.47As InAs
n 6 6 1 1 1 1
m*/m0 0.98 ml 1.6 ml 0.063 0.08 0.04 0.023m /m0 0.98 ml 1.6 ml 0.063 0.08 0.04 0.0230.19 mt 0.08 mt
Γ-(L/X) separation, eV -- -- 0.29 ~0.5 0.5 0.73( ) p ,
bandgap, eV 1.12 0.66 1.42 1.34 0.74 0.35
mobility, cm2/V-s 1000 2000 5000 3000 10,000 25,000
high-field velocity 1E7 1E7 1-2E7 3.5E7 3.5E7 ???
Drive Current in the Ballistic & Degenerate Limits
( ) 2/1*2/3⎞⎛⎞⎛ ( )
( ) 2/3*,
2/1*2/3
)/()/(1 where,
V 1mmA84
ooxodos
othgs
mmnccmmnK
VVKJ
⋅⋅+
⋅=⎟⎟
⎠
⎞⎜⎜⎝
⎛ −⋅⎟⎟⎠
⎞⎜⎜⎝
⎛⋅=
μ
0 25
0.2
0.250.7 nm, n=6 0.4 nm, n=6
Error bars on Si data points correct for (Ef-Ec)>> kT
0.15
K
0.8 nm, n=1 n = # band minimacdos,o = density of
(Ef Ec) kT approximation
SiGe
0 0
0.11.0 nm, n=1
,states capacitance for m*=mo & n=1InPInGaAs
0
0.05
EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well)
0.01 0.1 1m*/m
o
Intervalley Separation Source: Ioffe Institutehttp://www.ioffe.rssi.ru/SVA/NSM/Semicond
Intervalley separation sets:-high-field velocity throughhigh field velocity throughintervalley scattering-maximum electron density in channel without increased carrier effective mass
Choosing Channel Material: Other Considerations
Ge: low bandgap
G A l i t ll tiGaAs: low intervalley separation
InP: good intervalley separationGood contacts only via InGaAs→ band offsetsmoderate mass→ better vertical scaling
InGaAs good intervalley separationbandgap too low ? → quantizationl hi h ll ti l lilow mass→ high well energy→ poor vertical scaling
InAs: good intervalley separationbandgap too lowvery low mass→ high well energy→ poor vertical scaling
Non-Parabolic Bands
zero.near for only parabolic~ are Bands
k
hyperbolicnearlybecomebands energies, highAt
velocitygroupAsyptotic
.hyperbolicnearly become
→tors.semiconducmost inSimilar
velocity.group Asyptotic→
c.pessimistigenerally aresexpression FETband-Parabolic
pg y
Non-Parabolic Bands
T. Ishibashi, IEEE Transactions on Electron Devices, 48,11 , Nov. 2001,
MOSFET D iMOSFET DesignA i Assuming
G CIn0.5Ga0.5As Channel
Device Design / Fabrication Goalssidewall
metal gate
quantum well / channel
gate dielectric
N+ source N+ drain
source contact drain contact
substrate
barrier
quantum well / channel
DeviceDevicegate overdrive 700 500 300 mVdrive current 5 3 1.4 mA/μmN 6*1012 4*1012 2.5*1012 1/cm2Ns 6 10 4 10 2.5 10 1/cm
Dielectric: EOT 0.6 nm target, ~1.5 nm short term
Channel : 5 nm thickμ > 1000 cm2/V-s @ 5 nm, 6*1012 /cm2
S/D access resistance: 20 Ω-μm resistivity→ 0.5 Ω-μm2 contacts , ~2*1013 /cm2 , ~4*1019 /cm3 , 5 nm depth
Target Device Parameters
sidewall
gate dielectricmetal gate
quantum well / channelN+ source N+ drain
source contact drain contact
substrate
barrier
thicknm5cm/105~:well 212⋅n thicknm5,cm/105~ :well ⋅sn
213319 cm1052 thicknm 5 , cm105 /./ ⋅=→⋅ sn
m 10contact widenm 25 )m 250 2 μμ −Ω=−Ω )/(.(
Device StructureDevice Structure& &
P FlProcess Flow
Device Fabrication: Goals & Challenges
III-V HEMTs are built like this→ Source Drain
GateSource Drain
K Shinohara
and most ....and most III-V MOSFETs are built like this→
Device Fabrication: Goals & Challenges
εr
TiWN+ drainregrowth
N+ sourceregrowth
Yet, we are developing,at great effort,
εr
InGaAs wellInP well
at great effort,a structure like this →
barrierInP well
Why ?Why ?
So rce DrainGate
Source Drain
K Shinohara
Why not just build HEMTs ? Gate Barrier is Low !
Gate
Gate barrier is low: ~0.6 eV
Source DrainGate
K Shinohara
Tunneling through barrier Emission over barrier
K Shinohara
g g→ sets minimum thickness
Ec EcEF
→ limits 2D carrier density
Ewell-Γ
EF
Ewell-Γ
EF
eV 6.0~)( ,cm/10At 213cfs EEN −=
Why not just build HEMTs ? Gate barrier also lies under source / drain contacts
Gate
Gate barrier also lies under source / drain contacts
Source DrainGate
widegap barrier layer
N+ layer
K Shinohara
low leakage: low resistance:
K Shinohara
EcEF
gneed high barrier under gate
Ec
need low barrier under contacts
Ewell-ΓN+ caplayerEwell-Γ
EF
sidewall
The Structure We Need -- is Much Like a Si MOSFET sidewall
metal gategate dielectric
source contact drain contact
barrier
quantum well / channelN+ source N+ drain
substrate
no gate barrier under S/D contacts
high-K gatebarrier
Overlap between gateand N+ source/drain
How do we make this device ?
S/D RegrowthS/D Regrowth Process Flow
Regrown S/D FETs: VersionsWistey et al2008 MBE conference
planar regrowthregrowth under sidewalls
need thin sidewalls(now ~20-30 nm)
..or doping under sidewalls
S/D Regrowth by Migration-Enhanced Epitaxy Wistey et al2008 MBE conference
MBE growth is line-of-sight → gaps in regrowth near gate edges
MEE pro ides s rface migration d ring regro th eliminates gapsMEE provides surface migration during regrowth→ eliminates gaps
SEM Cross Section SEM Side View (Oblique)
SiO2 dummy t
SiO2 dummy t
Top of gate
Side of gate
Original InterfaceInGaAs Regrowth
gate
InGaAs Regrowth
gate
g
SEM: Greg Burek
No gapsSEM: Uttam Singisetti
High Si activation (4x1019 cm-3)
60
g pSmooth surfaces.
High Si activation (4x10 cm ). Quasi-selective: no growth on sidewalls
Self-Aligned Planar III-V MOSFETs by RegrowthWistey Singisetti BurekLee
N+ InGaAs regrowth, Mo contact metal
Mo contact metal
gate
Self-Aligned Planar III-V MOSFETs by RegrowthWistey Singisetti BurekLee
Regrown S/D FETs: Images
Regrown S/D FETs: Images
III-V MOSIII V MOS
InGaAs / InP MOSFETs: Why and Why Not
lo m*/m high more c rrent
0.250.7 nm, n=6 0 4 nm n=6
low m*/m0 → high vcarrier → more currentlow m*/m0 → low density of states → less current
ballistic / degenerate
0.15
0.2
K
0.8 nm, n=1
0.7 nm, n 6 0.4 nm, n=6
( ) 2/1*
2/3
where
, V 1m
mA84
⋅=
⎟⎟⎠
⎞⎜⎜⎝
⎛ −⋅⎟⎟⎠
⎞⎜⎜⎝
⎛⋅=
o
thgs
mmnK
VVKJ
μError bars on Si data points correct for (Ef-Ec)>> kT approximation
calculation
0.05
0.1
K
1.0 nm, n=1
( )2/3*
,1
where
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⋅⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛+
=
oox
odos
mmn
cc
Kn = # band minimacdos,o = density of states capacitance for m*=mo & n=1
00.01 0.1 1
m*/mo
EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well)
Low m* impairs vertical (hence L ) scaling ;Low m impairs vertical (hence Lg ) scaling ;InGaAs no good below 22-nm.
InGaAs allows very low access resistance
Si wins if high-K scales below 0.6 nm EOT; otherwise, III-V has a chance
InGaAs allows very low access resistance
InGaAs/InP Channel MOSFETs for VLSI
Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm
Devices cannot scale much below 22 nm Lg→ limits IC density
Little CV/I benefit in gate lengths below 22 nm LgLittle CV/I benefit in gate lengths below 22 nm Lg
Need device structure with very low access resistanceNeed device structure with very low access resistanceradical re-work of device structure & process flow
Gate dielectrics, III-V growth on Si: also under intensive development
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