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Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Mar 26, 2015

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Page 1: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Techniques for Combinational Techniques for Combinational Logic OptimizationLogic Optimization

Page 2: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Minimizing CircuitsMinimizing Circuits

Karnaugh Maps

Page 3: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Goals of Circuit MinimizationGoals of Circuit Minimization

(1) Minimize the number of primitive Boolean logic gates needed to implement the circuit.Ultimately, this also roughly minimizes the number of transistors, the

chip area, and the cost.Also roughly minimizes the energy expenditure

among traditional irreversible circuits.

This will be our focus.

(2) It is also often useful to minimize the number of combinational stages or logical depth of the circuit.This roughly minimizes the delay or latency through the circuit, the time

between input and output.

Note: Goals (1) and (2) are often conflicting!In the real world, a designer may have to analyze and optimize some

complex trade-off between logic complexity and latency.

Page 4: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Minimizing ExpressionsMinimizing Expressions

We would like to find the smallest sum-of-products expression that is equivalent to a given function.This will yield a fairly small circuit.

Page 5: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Simplification of Switching Functions

Page 6: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Karnaugh Maps (K-Map)

A K-Map is a graphical representation of a logic function’s truth table

Page 7: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Relationship to Venn Diagrams

0m

1m

2m

3mb

a

Page 8: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Relationship to Venn Diagrams

0

1

2

3b

a

Page 9: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Relationship to Venn Diagrams

0 1

0

1

ab

0

1

2

3

Page 10: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Two-Variable K-Map

0 1

0

1

ab

Page 11: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map

abc 00 01 11 10

0

1

0m

1m

2m

3m

6m

7m

4m

5m

Note: The bit sequences must alwaysbe ordered using a Gray code!

Page 12: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map

abc 00 01 11 10

0

1

Note: The bit sequences must always be ordered using a Gray code!

Page 13: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Four-variable K-Map

abcd 00 01 11 10

00

01

11

10

0m

1m

2m

3m

6m

7m

4m

5m

12m

13m

14m

15m

10m

11m

8m

9m

Note: The bit sequences must be ordered using a Gray code!

Not

e: T

he b

it s

eque

nces

mus

t be

orde

red

usin

g a

Gra

y co

de!

Page 14: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Four-variable K-Mapab

cd 00 01 11 10

00

01

11

10

Page 15: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Plotting Functions on the K-map

SOP Form

Page 16: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Canonical SOP Form

Three Variable Example

F ABC ABC ABC ABC

using shorthand notation

6 3 1 5F m m m m

, , 1,3,5,6F A B C m

Page 17: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

, , 1,3,5,6F a b c m

Plot 1’s (minterms) of switching function

1 1 1

1

Page 18: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

, ,F a b c ab bc

Plot 1’s (minterms) of switching function

1 1 1

1 abbc

Page 19: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Four-variable K-Map Exampleab

cd 00 01 11 10

00

01

11

10

, , , 0, 2,9,12,14F a b c d m

1

1

1

1

1

Page 20: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Karnaugh Maps (K-Map)

Simplification of Switching Functionsusing K-MAPS

Page 21: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Or, logically adjacent terms can be combined

Terminology/Definition Literal

A variable or its complement Logically adjacent terms

Two minterms are logically adjacent if they differ in only one variable position

Ex:

abc abcand

m6 and m2 are logically adjacent

Note: abc abc a a bc bc

Page 22: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Terminology/Definition

Implicant Product term that could be used to cover

minterms of a function Prime Implicant

An implicant that is not part of another implicant

Essential Prime Implicant A prime implicant that covers at least one

minterm that is not contained in another prime implicant

Cover A minterm that has been used in at least one

group

Page 23: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Guidelines for Simplifying Functions

Each square on a K-map of n variables has n logically adjacent squares. (i.e. differing in exactly one variable)

When combing squares, always group in powers of 2m , where m=0,1,2,….

In general, grouping 2m variables eliminates m variables.

Page 24: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Guidelines for Simplifying Functions

Group as many squares as possible. This eliminates the most variables.

Make as few groups as possible. Each group represents a separate product term.

You must cover each minterm at least once. However, it may be covered more than once.

Page 25: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

K-map Simplification Procedure

Plot the K-map Circle all prime implicants on the K-

map Identify and select all essential

prime implicants for the cover. Select a minimum subset of the

remaining prime implicants to complete the cover.

Read the K-map

Page 26: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Example

Use a K-Map to simplify the following Boolean expression

, , 1, 2,3,5,6F a b c m

Page 27: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 1: Plot the K-map

1 1 1

1

, , 1, 2,3,5,6F a b c m

1

Page 28: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 2: Circle ALL Prime Implicants

1 1 1

1

, , 1, 2,3,5,6F a b c m

1

Page 29: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 3: Identify Essential Prime Implicants

1 1 1

1

, , 1, 2,3,5,6F a b c m

1

EPI

EPI

PI

PI

Page 30: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 4: Select minimum subset of remaining Prime Implicants to complete the cover.

1 1 1

1

, , 1, 2,3,5,6F a b c m

1

EPIPI

EPI

Page 31: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 5: Read the map.

1 1 1

1

, , 1, 2,3,5,6F a b c m

1

bcab

bc

Page 32: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Solution

, ,F a b c ab bc bc ab b c

Page 33: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Example

Use a K-Map to simplify the following Boolean expression

, , 2,3,6,7F a b c m

Page 34: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 1: Plot the K-map

11

11

, , 2, 4,5,7F a b c m

Page 35: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 2: Circle Prime Implicants

11

11

, , 2,3,6,7F a b c m

Wrong!!We reallyshould drawA circle aroundall four 1’s

Page 36: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 3: Identify Essential Prime Implicants

EPIEPI

, , 2,3,6,7F a b c m

11

11Wrong!!We reallyshould drawA circle aroundall four 1’s

Page 37: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 4: Select Remaining Prime Implicants to complete the cover.

EPIEPI

11

11

, , 2,3,6,7F a b c m

Page 38: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 5: Read the map.

abab

11

11

, , 2,3,6,7F a b c m

Page 39: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Solution

, ,F a b c ab ab b

Since we can still simplify the functionthis means we did not use the largestpossible groupings.

Page 40: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 2: Circle Prime Implicants

11

11

, , 2,3,6,7F a b c m

Right!

Page 41: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 3: Identify Essential Prime Implicants

EPI

, , 2,3,6,7F a b c m

11

11

Page 42: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

Step 5: Read the map.

b

11

11

, , 2,3,6,7F a b c m

Page 43: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Solution

, ,F a b c b

Page 44: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Special Cases

Page 45: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1 1 1 1

1

, , 1F a b c

11

1

1

Page 46: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1

, , 0F a b c

Page 47: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Three-Variable K-Map Example

abc 00 01 11 10

0

1 1

, ,F a b c a b c

1

1

1

Page 48: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Four Variable Examples

Page 49: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Example

Use a K-Map to simplify the following Boolean expression

, , , 0, 2,3,6,8,12,13,15F a b c d m

Page 50: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Four-variable K-Mapab

cd 00 01 11 10

00

01

11

10

, , , 0, 2,3,6,8,12,13,15F a b c d m

1

1

1

1

11

1

1

Page 51: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Four-variable K-Mapab

cd 00 01 11 10

00

01

11

10

0,2,3,6,8,12,13,15F m

1

1

1

1

11

1

1

Page 52: Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.

Four-variable K-Mapab

cd 00 01 11 10

00

01

11

10

F abd abc acd abd acd

1

1

1

1

11

1

1