TechnicalUniversityofDenmark MasterThesis2006etd.dtu.dk/thesis/195553/oersted_dtu2953.pdfTechnicalUniversityofDenmark MasterThesis2006 ... B.2 PSpice ... 7.2 Bode plot for the worst

Technical University of DenmarkMaster Thesis 2006

A DC-DC Converter for RF PAin WCDMA Mobile Phones

s041932 Ólafur Haukur Sverrisson

Supervisors:Per Møller Michael A. E. Andersen Ole Cornelius Thomsen

October 23, 2006

Abstract

The popularity of low voltage portable devices increases rapidly. The market demandfor smaller and more ecient electric circuits is theatrical. The 3rd generation WCDMAmobile phone has suered from a signicant power dissipation in the last years. Improve-ments in circuit design and semiconductor devices have alleviated this problem. TheRF PA in a WCDMA mobile phone is a big power consumer and very inecient. Theeciency can be improved dramatically by employing a DC-DC converter to control itssupply voltage. This thesis explains how this can be done with a Buck-Boost converterwith an emphasis on high switching frequency.

Previous research and proposals for the topic are presented and discussed. Descriptionof the design steps of an envelope tracking synchronous non-inverting Buck-Boost DC-DC converter with a 20MHz switching frequency is then presented. The high switchingfrequency was chosen to examine if it is of interest to use higher switching frequency thanneeded. Smaller component size and lower spectral emission are among the advantagesof operating at higher switching frequency.

Despite showing promising performance in simulations and calculations the physi-cal realization failed to impress. Although the converter uses fairly sized components,L = 43nH and C = 1µF , and has low ripple < 50mV it does not have an acceptable e-ciency. The RF PA's average eciency can probably be improved by using the designedconverter but not as much as desired.

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Contents

1 Introduction 1

2 Problem Description 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 DC-DC Converter Requirements . . . . . . . . . . . . . . . . . . . . . . . 3

3 Research and Proposals 53.1 Previous Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1.1 Probability Distribution . . . . . . . . . . . . . . . . . . . . . . . 53.1.2 WCDMA Modulation and Power Control . . . . . . . . . . . . . . 63.1.3 Linearity Requirements . . . . . . . . . . . . . . . . . . . . . . . . 83.1.4 The RF Power Amplier and Linearity . . . . . . . . . . . . . . . 93.1.5 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Proposals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2.1 Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2.2 Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.3 Envelope Detection . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.4 Controller and Modulation . . . . . . . . . . . . . . . . . . . . . . 143.2.5 RF Power Amplier . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.6 Eciency Improvement . . . . . . . . . . . . . . . . . . . . . . . . 143.2.7 Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.8 Fixed Levels or Dynamic Output Voltage . . . . . . . . . . . . . . 153.2.9 Component Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Problem Statement 16

5 Topologies and Control Circuitry 175.1 Regulator Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.2 Boost/LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.3 Boost Followed by a Buck . . . . . . . . . . . . . . . . . . . . . . . . . . 185.4 Inverting Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.5 Non-Inverting Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . 195.6 Cuk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.7 SEPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.8 Zeta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9 Topology Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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5.10 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.11 Modulation Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.12 Comparison Signal - Triangle/Sawtooth . . . . . . . . . . . . . . . . . . . 225.13 Envelope Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.14 Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.15 Controller Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Dynamically Adaptive Buck-Boost Converter 256.1 The Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.2 Buck-Boost States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.3 Power Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.4 Compensation Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.5 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.6 Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.7 Sawtooth Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.8 Oset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.9 Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.10 Soft Start-Up Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.11 Duty Cycle Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.12 Design Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7 Simulations and Calculations 437.1 Bode Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437.2 Matlab Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467.3 Switching Loss and Eciency . . . . . . . . . . . . . . . . . . . . . . . . 49

8 Physical Realization 558.1 LC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558.2 MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568.4 Error Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568.5 Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568.6 Snubber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.7 PCB Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9 Measurements 609.1 Noise Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609.2 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 609.3 DTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629.4 Stability Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649.5 Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649.6 Switching Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669.7 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10 Conclusion 69

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A Appendix 71A.1 Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71A.2 Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

B Appendix 81B.1 Matlab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81B.2 PSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81B.3 Datasheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81B.4 Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

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List of Figures

2.1 Simplied block diagram of the setup where the RF PA is supplied from aDC-DC converter that is controlled by a DSP. . . . . . . . . . . . . . . . 3

3.1 Probability curves for transmit power level for talk and data mode as wellas the required supply voltage. . . . . . . . . . . . . . . . . . . . . . . . 6

3.2 RF PA current consumption when supplied with a xed supply (Old sys-tem) or a dynamic supply (New system) for dierent transmission powerlevels. The PDF is also plotted for comparison. . . . . . . . . . . . . . . 7

3.3 Block diagram of a modulation scheme in the transmitter of a mobilephone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.4 Constellation diagram of a QPSK modulation scheme. . . . . . . . . . . 93.5 Simplied RF power amplier and its connections to the power supply and

antenna. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.6 Input to output power transfer function of a power amplier. . . . . . . 10

5.1 Boost and LDO converter . . . . . . . . . . . . . . . . . . . . . . . . . . 185.2 Boost converter followed by a Buck converter. . . . . . . . . . . . . . . . 185.3 Inverting Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.4 Non inverting Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . 205.5 Cuk converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.6 Sepic converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.7 Zeta converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.8 Switching frequencies that do not introduce switching harmonics from the

fundamental frequency at the 1920MHz - 1980MHz WCDMA transmissionbandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1 Buck-Boost circuit with four switches. . . . . . . . . . . . . . . . . . . . 256.2 Buck-Boost converter when in state 1. . . . . . . . . . . . . . . . . . . . 266.3 Buck-Boost converter in state 2. . . . . . . . . . . . . . . . . . . . . . . . 276.4 Buck-Boost converter in state 3. . . . . . . . . . . . . . . . . . . . . . . . 276.5 Bode plot of the open loop converter in Boost mode with maximum duty

cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.6 3-pole, 2-zero Compensation network . . . . . . . . . . . . . . . . . . . . 306.7 Bode plot of the compensated converter in Boost working at maximum

duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.8 PWM stage. Comparators compare feedback voltages with a sawtooth

signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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6.9 The three operating modes of the Buck-Boost converter. . . . . . . . . . 346.10 PWM waveforms in Buck-Boost mode. . . . . . . . . . . . . . . . . . . . 356.11 Adder circuit used for the oset circuit. . . . . . . . . . . . . . . . . . . . 366.12 Oset circuit (adder) for the Buck feedback error signal. . . . . . . . . . 366.13 Dead-time control for the Buck stage. . . . . . . . . . . . . . . . . . . . 376.14 Waveform presentation of the DTC logic for the Buck stage. . . . . . . . 386.15 Dead-time control for the Boost stage. . . . . . . . . . . . . . . . . . . . 386.16 Waveform presentation of the DTC logic for the Boost stage. . . . . . . . 396.17 Soft-start circuit to limit the converter's duty cycle. . . . . . . . . . . . 396.18 Illustration of the PWM signal when soft start-up circuit is used. . . . . 406.19 Duty cycle limiting circuit for the Boost PWM. . . . . . . . . . . . . . . 416.20 The Buck-Boost with feedback and control circuitry. . . . . . . . . . . . . 42

7.1 Bode plot of the uncompensated Buck-Boost converter in the worst casescenario. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.2 Bode plot for the worst case scenario when the Buck-Boost converter isoperating at full output power with minimum battery supply. . . . . . . 45

7.3 Bode plot of the Buck-Boost in a typical working environment. . . . . . 457.4 Bode plot of the Buck-Boost converter when Vout = Vbat = 3.6V . . . . . 467.5 A Buck-Boost converter with four switches. . . . . . . . . . . . . . . . . 477.6 Simulation setup for Matlab Simulink. . . . . . . . . . . . . . . . . . . . 487.7 The Buck-Boost converter simulation block in Matlab Simulink. . . . . . 487.8 Simulated output voltage when RF PA changes output power level from

27dBm to 28dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497.9 Simulated output voltage rise when RF PA changes output power level

from 27dBm to 28dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 507.10 Simulated output voltage fall when RF PA changes output power level

from 27dBm to 28dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507.11 Simulated output voltage ripple when RF PA changes output power level

from 27dBm to 28dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517.12 Eciency of a Buck converter with a switching frequency of 20MHz as-

suming a lossless diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527.13 Eciency of a Buck converter with a switching frequency of 33.6MHz as-

suming a lossless diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527.14 Power dissipation in a Buck converter with a switching frequency of 20MHz.

Three dierent calculations of the switching loss and one of the conductionloss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.15 Power dissipation in a Buck converter with a switching frequency of 33.6MHz.Three dierent calculations of the switching loss and one of the conductionloss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.16 Calculated eciency for the Buck-Boost converter in Buck mode. . . . . 54

8.1 The Buck-Boost PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.2 The 20MHz sawtooth signal generator PCB. . . . . . . . . . . . . . . . . 59

9.1 Sawtooth signal measured at the sawtooth PCB (Green) and at the Buck-Boost PCB (red). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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9.2 Feedback signal from the oset circuit to the Buck comparator. . . . . . 619.3 Ringing at the inductor's input. . . . . . . . . . . . . . . . . . . . . . . 629.4 Voltage waveform at the inductor with a RC snubber. . . . . . . . . . . . 639.5 Rise and fall time measurements of a MOSFET gate signal. . . . . . . . 639.6 DTC in Buck mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649.7 Unstable output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 659.8 Output voltage ripple in Buck mode. . . . . . . . . . . . . . . . . . . . . 659.9 The Buck PMOS gate signal(blue) and the resulting switching transi-

tion(red) at half duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . 669.10 The Buck PMOS gate signal(blue) and the resulting switching transi-

tion(red) at small duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . 679.11 Eciency of the Buck-Boost converter in Buck mode. . . . . . . . . . . 67

A.1 Voltage divider. The input voltage is divided between two resistors. . . . 71A.2 Insertion of a switch can change the DC component of the voltage. . . . . 72A.3 A low pass LC lter added to remove the switching harmonics. . . . . . . 72A.4 A control system with a feedback adjusts the duty cycle to regulate the

output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73A.5 Buck converter circuit when the switch is in position 1. . . . . . . . . . . 74A.6 Buck converter switch when the switch is in position 2. . . . . . . . . . . 75A.7 Boost converter circuit with an ideal switch. . . . . . . . . . . . . . . . . 78A.8 Boost converter circuit when the switch is in position 1. . . . . . . . . . . 78A.9 Boost converter circuit when the switch is in position 2. . . . . . . . . . 79

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Glossary

2G Second Generation3G Third Generation3GPP 3rd Generation Partnership ProjectAC Alternating CurrentACLR Adjacent Channel Leakage RatioACPR Adjacent Channel Power RationBW BandwidthCDMA Code Division Multiple AccessDAC Digital to Analog ConverterDC Direct CurrentDTC Dead Time ControlDSP Digital Signal ProcessorEMI Electromagnetic InterferenceEER Envelope Elimination and RestorationESC Equivalent Series CapacitanceESL Equivalent Series InductanceESR Equivalent Series ResistanceEVM Error Vector MagnitudeGSM Global System for Mobile CommunicationsIC Integrated CircuitLC Filter: Inductor and CapacitorLDO Low Drop-OutMOSFET Metal-Oxide-Semiconductor Field-Eect TransistorNMOS N-Channel MOSFETNPR Noise Power RatioOp amp Operational AmplierPA Power AmplierPAE Power Added EciencyPCB Printed Circuit BoardPDA Personal Digital AssistantPDF Power Density Function

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PFM Pulsed Frequency ModulationPMOS P-Channel MOSFETPWM Pulsed Width ModulationRF Radio FrequencyRHP Right Half PlaneRMS Root Mean SquareSEPIC Single Ended Primary Inductance ConverterSNR Signal to Noise RatioUMTS Universal Mobile Telecommunication SystemWCDMA Wide band Code Division Multiple Access

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Chapter 1

Introduction

Along with the third generation (3G) of mobile communication system, that is beinginstalled all around the world, come mobile phones with high speed data transmissioncapability and a lot of new applications like video and music players. These versatilephones need much power and therefore demand power management solutions to extendthe battery lifetime.In each mobile phone there is an antenna that transmits and receives electromagneticwaves to and from the base station. The antenna is powered by a radio frequency (RF)power amplier (PA) so that the transmitted signal is powerful enough to reach the basestation. The RF PA is usually the most power consuming part of the mobile phone andit is therefore of interest to make it as ecient as possible to increase battery life. The3G wideband code division multiple access (WCDMA) mobile phones have suered froma signicant power dissipation in the past years but improvements in circuit design andsemiconductor devices have made them competent in the communications market.

The PA has to be linear in the 3G WCDMA system to preserve the integrity of thetransmitted signal and minimize interfere in neighboring channels. Linear PA are lowecient in nature but by dynamically controlling the supply voltage for the RF PA, it ispossible to improve the average PA eciency and extend the battery life time.

The objective of this thesis is to examine the possibilities of making the RF PA moreecient and to design a DC-DC converter that can dynamically supply voltage to the RFPA. The thesis also discusses the advantages and disadvantages of using higher switchingfrequency in the DC-DC converter.First, the RF PA eciency problem and possible solution is described. Previous studiesand proposals are then discussed and the projects problem statement dened. Subse-quently, dierent topologies are discussed and a high frequency Buck-Boost converter isdesigned. Simulations and calculations are made to estimate the converter's performancefollowed by a description of the physical realization of the prototype and then the mea-surements are presented. Finally the conclusions are made and accomplishments andresults are discussed.

I want to thank my instructors; Per, Michael and Ole for making this project pos-sible. I would also like to thank all at the power electronics department at DTU thatcontributed to the project for being very helpful when help was needed.

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Chapter 2

Problem Description

2.1 IntroductionThe 3rd generation of mobile phones in the universal mobile telecommunication system

(UMTS) standard use the WCDMA technology. WCDMA is a wideband spread-spectrummobile telecommunication air interface that utilizes code division multiple access whichallows up to 2Mbps transmission speeds. The user can expect 384kbps which is still muchgreater than the 14.4kbps from GSM.

More and more technologies are being integrated into the modern mobile phones. Asa result, the mobile phone is becoming more like a personal digital assistant (PDA) thanjust a phone. A video and photo camera, MP3 player and more have been interweavedwith the mobile phone increasing the power consumption. This leads to overweighthandsets with poor battery life.

In battery operated wireless systems the RF PA is often the most power consumingcomponent. Therefore, oppertunities of improvement are likely to be found there.

The code division multiple access (CDMA) multiplexing scheme requires power con-trol from the base station. This, and the fact that the signal is amplitude modulated, setschallenging requirements for the RF PA that is usually Class A or Class AB and thereforehighly linear. These PAs have traditionally been powered directly from the battery whichmakes the implementation easy. This setup is however inecient and can be improveddramatically by powering the PA with a DC-DC converter that changes it's output volt-age dynamically according to the signal being transmitted. In other words, the DC-DCconverter supplies only the voltage needed to the RF PA according to the signal beingtransmitted at each time instant so the semiconductor device in the PA operates in theright operating point and does not saturate.

Figure 2.1 shows a simple block diagram of the setup where the RF PA is poweredfrom a DC-DC converter. The digital signal processor (DSP) is the main control stationin a mobile phone. The DSP modulates the baseband signal using the WCDMA codingscheme and mixes it with a radio frequency carrier and sends to the RF PA that ampliesthe signal for the antenna where it is transmitted wireless to the base station. The basestation sends information about the transmitting power level to the DSP. This informationcan be sent further to the DC-DC converter so it can vary its output voltage accordingly.This setup looks simple but there are certain requirements that have to be fullled whichdiscussed in the following chapter.

2

Figure 2.1: Simplied block diagram of the setup where the RF PA is supplied from aDC-DC converter that is controlled by a DSP.

2.2 DC-DC Converter RequirementsThe UMTS specications state that the WCDMA envelope bandwidth is 3.84MHz

operating at a 1920− 1980MHz carrier frequency. The power level changes every 666µsand the phone is informed of what power level it should transmit on from the base station.

A converter that would dynamically change its output voltage according to theWCDMAenvelope would have to have a bandwidth that is four times the envelope bandwidth inorder to suppress the fourth-order harmonics in the envelope amplier, this means a con-verter bandwidth equal to 4× 3.84MHz = 15.36MHz [27]. The closed loop bandwidthof the DC-DC converter is generally limited to 1

10of the switching frequency [10] but it

can possibly be extended to 15with good design, this gives a switching frequency equal

to 5× 15.36MHz = 76.8MHz [27].A DC-DC converter that can follow the WCDMA envelope is hard to design so the

converter is usually designed to follow the power level changes. The RF PA power changesare 1dBm every 666µs and the converter has to change its output voltage and settle withina 50µs window. The mobile phone can also change its transmission mode from voice todata every 10ms.

The maximum RF PA output power is 28dBm which is equal to 631mW . Researchhas shown that a RF PA supply voltage of minimum 3.4V should be enough in mostcases to fulll requirements of linearity. The RF PA operating at full output power hasusually an eciency of 30% to 40% so the maximum supply current would be around

Ioutmax =0.631W

3.6

1

0.35= 0.701A (2.1)

when the RF PA eciency is 35% and the converter is supplying 3.6V [23]. At low

3

power levels it is enough to supply down to 0.4V and still meet the linearity requirements.Lowering the supply voltage at low power levels improves the average RF PA eciencybecause it operates mostly at lower power levels.

The DC-DC converter needed has to be ecient for a wide output voltage range andload range. It has to supply current up to 0.7A and have fast output slew rate andsettling. Hence, the main requirements are

• Input voltage range, Vbat = 2.7V to 4.2V

• Output voltage, Vout = 0.5V to 3.6V

• Output current, Iout = 50mA to 0.7A

• Output ripple voltage as low as possible

• High eciency over wide output voltage range and load range

• Output slew rate and settling < 50µs

This is a challenging task. The following chapter is dedicated to previous work in eldwhere the operating environment is examined and proposals are covered.

4

Chapter 3

Research and Proposals

Many proposals have been made in the past years to solve the problem introduced inchapter 2. However, no solution has yet gained general acceptance as the best solution.The eld is therefore still wide open and new exciting ideas are published frequently.

This chapter dwells on previous research that has been used as a foundation for thisthesis and proposals that inuenced the project.

3.1 Previous ResearchTwo important facts about the WCDMA environment are discussed in this section;

the probability density function (PDF) and the RF PA characteristics. The importantRF PA linearity-eciency performance trade o is explained and the CDMA/WCDMAmodulation scheme is presented.

3.1.1 Probability DistributionThe probability density function of the transmission power in WCDMA mobile phones

is important to see where the possibilities for eciency enhancements are. The WCDMAPDF for voice and data mode is shown on gure 3.1 [17] [16] as well as the required supplyvoltage. The curves for urban and suburban environments are not shown but they dierslightly. The urban curve has higher probability of lower power levels because there aresmaller cells in urban areas while the suburban has higher probability of high power levels.The output power ranges from −50dBm to 28dBm where 28dBm is equal to 631mW .The highest probability is at approximately 8dBm. This dynamic output power range isdierent from the power range in the GSM system where the mobile phones transmit ata narrow output power range.

From the gure it can been seen that there is a little probability that the phone istransmitting at the highest power level. The most eciency improvement can be madein the lower power levels where the probability is higher. Figure 3.2 shows the RF PAcurrent usage with a xed supply and the current usage with a dynamic supply [16].

A PDF for the reverse link IS-95B CDMA system is plotted in gure 3.2 for com-parison with WCDMA PDF on the previous gure. The PDF states that the maximumprobability is around 4dBm and there we can see much improvement. The current sup-plied by the dynamic supply is nearly 6 times smaller than the current supplied withthe xed supply. The CDMA and WCDMA PDF are very similar. The WCDMA PDF

5

Figure 3.1: Probability curves for transmit power level for talk and data mode as well asthe required supply voltage.

is expected to have higher probability on higher power levels because of increased datatransfer.

3.1.2 WCDMA Modulation and Power ControlFigure 3.3 shows a block diagram of the modulation scheme in a typical transmit-

ter stage in a mobile phone. The baseband in-phase (I) and quadrature-phase (Q) aremodulated into an intermediate frequency signal which is amplied by a variable gain am-plier. The signal is bandpassed ltered and mixed with a RF carrier signal from a localoscillator. The resulting RF signal goes through another variable gain amplier before iteventually goes to the RF PA and the antenna. The last variable gain amplier controlsthe signal level at the PA input which means that it controls the antenna power level [26].

The CDMA is a form of multiplexing that is used in WCDMA and GPS for example.It does not divide up the channel by time or frequency, it encodes the data with a codeso that it separates dierent users in code space and enables access to a shared mediumwithout interference. The CDMA spreads the bandwidth needed to transmit data overa wider bandwidth. This has the advantage that it tolerates narrow band interference.The power level of the spreaded signal can be much lower than the original narrow bandsignal without loosing information. It can even be as low as the background noise whichmakes it dicult to distinguish the user signal from the noise [28]. It is no surprise thatthis multiplexing scheme was developed for military communications.

6

Figure 3.2: RF PA current consumption when supplied with a xed supply (Old system)or a dynamic supply (New system) for dierent transmission power levels. The PDF isalso plotted for comparison.

Figure 3.3: Block diagram of a modulation scheme in the transmitter of a mobile phone.

7

The CDMA multiplexing is often compared to an international cocktail party wheremany people are talking. Some people talk in English, some in Danish and others inIcelandic. The language is equivalent to a code. Those who speak English focus on whatis said in English and so on, because they have the same code. As the number of peopletalking in the party rises, the power level increases and you have to talk louder if youwant people to hear you. This is a simple metaphor for the CDMA and WCDMA powercontrol where the base station controls the transmitting power level of each mobile phoneconnected to it so that all signals are at the same power level at reception.

3.1.3 Linearity RequirementsWireless communication systems are supposed to maintain their signal transmission

within the bandwidth allocated for them. The interference with other systems shouldbe kept at minimum. Linear modulation schemes are dened as those that transmit inboth the amplitude and the phase of the RF signal. The envelope of the RF signal varieswith time and its delity must be preserved in order to demodulate the information beingsent. The linearity of an RF PA is measured in terms of both in-band and out-of-bandundesired signal generation.

There are strict specications for the linearity of the IS-95 (CDMA) and 3GPP(WCDMA) wireless communication spread spectrum standards. There are three im-portant measures of the linearity performance of the RF PA, the adjacent channel powerratio (ACPR), error vector magnitude (EVM) and the noise power ratio (NPR).

ACPR is a measure of how much the transmission interferes with neighboring channelsand is therefore classied as out-of-band undesired signal. It is dened as the power inthe transmission bandwidth at a certain oset from the channel center frequency dividedby the power in the transmission bandwidth around the channel center frequency.

The EVM is a measure of a phase-shift modulation radio transmitter. The error vectoris the vector from the transmitted signal location to the ideal location. The informationsignal being sent can be aligned in a constellation diagram in the I-Q complex plane.Constellation points are a set of modulation symbols. The WCDMA mobile phones usehybrid phase shift keying (HPSK) modulation which is a variation of the quadraturephase shift keying (QPSK) where two successive transitions through the origin are notallowed to reduce the peak to average ratio. The constellation diagram for a QPSK/H-PSK is shown on gure 3.4.

The EVM is the distance in the complex plane between the ideal constellation pointand the point that was transmitted. The symbols are modulated by varying the magni-tudes of the cosine and sine waves in the modulation scheme in gure 3.3. The receiverhas to compare the received signal to the constellation diagram for demodulation. Inideal transmission the received signal will align perfectly with one constellation point inthe diagram but in the real world the demodulator has to estimate what was actuallytransmitted by selecting the closest constellation point from the received signal. Thesignal is usually corrupted with noise and one noise source is the DC-DC converter. TheDC-DC converter adds noise to the transmitted signal due to switching ripple of the RF

8

Figure 3.4: Constellation diagram of a QPSK modulation scheme.

Figure 3.5: Simplied RF power amplier and its connections to the power supply andantenna.

PA supply voltage. It is therefore of interest to minimize the output voltage ripple.

The noise power ratio is a measure of the unwanted in-band distortion power causedby the nonlinearity in the power amplier. This measurement is more used for ampliersin base stations.

3.1.4 The RF Power Amplier and LinearityFigure 3.5 shows a simplied model of a transistor RF power amplier. The PA can be

built with a metal-oxide-semiconductor eld-eect transistor (MOSFET) as well. Thereis a matching circuit at the input and the output of the PA to minimize reections andmaximize the power transfer. A RF choke is at the power supply's input to get rid ofalternating currents (AC) from the DC supply.

The time domain WCDMA base band signal envelope has a large peak to average ratioopposite to the GSM where the envelope is constant. The RF PA is normally designed

9

Figure 3.6: Input to output power transfer function of a power amplier.

and biased so that the peak signals experience no or limited clipping so that it fulllsthe requirements of linearity. When the PA is not working at the signal peaks it has lesseciency. Hence, the PA should be operated in such a way that it has high eciencythroughout the base band signal envelope [26].

Figure 3.6 shows the input to output power transfer function of a power amplierwhere the PA is biased to be linear. The dotted lines represent the minimum and max-imum amplitudes of the signal waveform and the line in between represents the averagesignal power. The peak signal power does not enter the nonlinear region and no clippingoccurs. The PA can be biased so that the peak amplitude enters the nonlinear regionwhich results in clipping of the output signal waveform because the PA gets saturated.This leads to degraded linearity and the output signal contains unwanted harmonics.

Power ampliers can work in Class A, B, AB or C depending on the bias of the device.The bias is a voltage or a current that determines the PA's working point and whetherit amplies over the whole input cycle or part of it. Class A ampliers amplify over thewhole input cycle so that the output signal is an exact scaled up replica of the input withno clipping. The theoretical maximum eciency is 50% which means that the Class Aamplier is not very ecient. The reason for its/this ineciency is that the transistor isalways conducting, even when there is no input, resulting in waste of power.

Class AB transistor is active between half and the whole input cycle and a Class Btransistor is active half of the input cycle. This creates distortion but their eciency ismuch higher than Class A transistor. The theoretical maximum eciency of the Class Bis 78.5%. This is because the amplier is turned o half of the time and does thereforenot dissipate power half of the time.

Class C is when the transistor amplies over less than half the input cycle. This classhas very poor linearity but good eciency and is useful for high power RF amplierswhere linearity is not of importance [36].

There is a linearity and eciency trade-o when selecting the appropriate PA class.Further, when the PA is working at high power its linearity gets less. This is becausethe transistor gets saturated and the amplied signal gets compressed. This results in anAM-AM non linearity and higher amplitude values are amplied less than the mediumand low amplitudes. This can also result in AM-PM distortion where little change in

10

amplitude can cause a considerable phase deviation [26].

It is possible to improve the PA's linearity with signal processing. Many linearizationtechniques have been introduced, for example: direct feedback, feed forward, analog anddigital predistortion, postdistortion, polar loop feedback, Cartesian feedback, envelopeelimination and restoration (EER) and more. Most linearization techniques aim at im-proving the PA's linearity at maximum output power level. The base station is morelikely to operate at the maximum output power than the mobile phone and therefore thelinearization techniques are better suited for the base stations. The linearization requiresalso additional circuitry that increases the overall complexity and cost [26].

The statistics discussed above show that the CDMA/WCDMA RF PA operates atpower levels around +8dBm most of the time. It is possible to reduce the PA collectorbias considerably at those power levels and still fulll the requirement of linearity. Thiswill reduce the power loss from excessive collector-bias headroom and therefore increaseeciency. The PA collector bias can be lowered down to 0.4V and still fulll the linearityrequirement [18]. Manufacturers recommend a minimum supply voltage to the RF PAof Vout = 3.4V when delivering the maximum power of Pout = 28dBm = 631mW . Themaximum current was estimated to be Ioutmax = 0.701A in equation 2.1 using a RF PAwith a power added eciency PAE = 0.3 and a supply voltage of Vout = 3.6V .

The RF PA used in transmitters require very high linearity to preserve the signaldelity and to minimize interference with adjacent channels. This makes the RF PA avery important component because it determines the nal quality of the signal. It isusually the most power consuming circuit block in mobile phones.The RF PA is therefore a key block, as far as cost, power consumption, reliability, andsystem performance requirements are concerned [8].

3.1.5 EciencyTo calculate the eciency of the RF PA we have to consider its eciency over wide

output power range and compare to the PDF. This will give us the average eciencywhich is dened as the ratio of the average output power to the average input power [12]

ηavg =

∫ 28dBm−50dBmPPAoutPDF (PPAout)dPPAout∫ 28dBm

−50dBm PPSPPAoutPDF (PPAout)dPPAout

(3.1)

where PPAout is the output power level, PDF (PPAout) is the probability of the outputpower PPAout , and PPS is the input supply power. This is probably the most suitablemeasure of the eciency of the system because it takes the PDF into account.

The are other measures of eciency and one of them is the drain/collector eciencyof the RF PA, dened as the ratio of the output power level to the input supply power

11

ηdrain =PPAout

PPS

(3.2)

The power added eciency (PAE) is an eciency measure that RF PA producersoften use. It is dened as the ratio of the dierence of the output power and input powerto the input supply power

ηPAE =PPAout − PPAin

PPS

(3.3)

From this equation the advantage of using a DC-DC converter to supply the RF PAcan be easily seen. If the RF PA is supplied directly from the battery the supply powerwill be PPSbat

= VbatIbat but when it is supplied by a DC-DC converter the supply powerwill be PPS = VoutIout. To increase the PAE the Vout and Iout have to be low comparedto Vbat and Ibat. By lowering Vout when the RF PA is transmitting at low output powerlevels the current drawn by the PA is reduced. Hence, lower current is drawn from thebattery and PAE is increased.

3.2 ProposalsThis section discusses ideas and proposals for the DC-DC converter design that already

have been published. Many papers inuenced the project in some way or another andsome more than others.All researchers are seeking improved eciency of the RF PA and many have reportedsuccessful designs.

3.2.1 TopologiesEngineers typically stick to the basic converter topologies like Buck and Boost. The

low drop-out regulator (LDO) is cheap and is often used in combination with the basicswitched mode converters. Then there are researchers that think out of the box and tryto develop new topologies or methods to solve the problem [9]. Those methods are oftennot practical for the task but are good ideas none the less.

A Buck converter associated with a bypass circuit or a LDO regulator is probablythe best solution today when considering simplicity and cost [17] [9] [21]. It is impor-tant to be able to lower the output voltage at low power levels since the most eciencygain is achieved there. However, this solution is not good when the battery supply is low,Vbatmin

= 2.7V and the converter has to deliver full output power which is estimated to bearound Voutmax = 3.6V to fulll the linearity requirements. These linearity requirementscan be met by designing a Boost converter with a LDO regulator [11]. The opportunityto gain eciency at low output voltage is wasted because the LDO has very low eciency.

12

Furthermore, there is also the option to use a Buck-Boost [27] and combine the benetsof the two. A Buck-Boost can supply voltage to fulll the linearity requirement at highoutput power levels and improve the eciency at low power levels by lowering the supplyvoltage. This solution is more complicated than the solutions mentioned above.

Researchers have moreover proposed new architectures for DC-DC conversion like aVernier-regulated converter and cell-modulation-regulated converter [19]. These architec-tures introduce higher switching frequency than seen before (>100MHz) but seems to berather complicated and expensive for the application. These types of converters could beuseful in the future when the WCDMA is improved further to have a wider bandwidth.

3.2.2 Switching FrequencySwitching frequency is a crucial topic in this thesis. Many proposed solutions with

dierent frequencies have been tried ranging from 0.5MHz to 100MHz. A switchingfrequency of 500kHz with a 20kHz bandwidth [5] is enough to fulll the requirementof 50µs slew rate and settling following the RF PA power level changes. 2MHz switch-ing frequency helps the use of smaller sized components and to meet spectral emissionrequirements [17] but with degraded converter eciency.

Higher switching frequencies like 5MHz [33], 10MHz [11][16] and 16MHz [21] havebeen proposed debating that smaller sized components and less spectral emission are ofinterest. Because of less spectral emission and higher bandwidth the converters can op-erate the RF PA in lower power back-o. This possibly enables them to achieve betteroverall eciency of the RF PA even though the converter itself has lesser eciency.

With improved semiconductor devices and new methods there come ambitious pro-posals of converters that operate with a higher switching frequency. A Buck converterwith a switching frequency of 89MHz has for example been introduced [9]. The frequencywas selected so that the converter does not have any switching frequency harmonic in theWCDMA transmission band at all. The converter does not change the output voltagedynamically but in ve steps which means that it operates in power back-o most of thetime.

Converters with higher switching frequencies require more complicated architecture.Attempts at using conventional architectures with considerable higher switching frequen-cies have not met the requirement of eciency and ability to regulate the output voltage.New approach that incorporates circuit structures and principles that are employed intuned RF PA have been applied to the DC-DC converter to reach a switching frequencyof 100MHz [19]. If this idea turns out to be useful it will allow signicant improvementsin the converter size and possibly permit its integration.

3.2.3 Envelope DetectionThe DC-DC converter is supposed to change its supply voltage to the RF PA according

to the signal being transmitted. This calls for an envelope detection of some kind thateventually controls the converter. Converters operating at lower switching frequency

13

usually change their output voltage according to the power level of the transmitted signal[27][33][21]. The information of the envelope can be sensed with an envelope detectioncircuit but most solutions rely on receiving information of the power level directly fromthe DSP through a digital to analog converter (DAC) and therefore do not use a envelopedetector.

3.2.4 Controller and ModulationNear all proposals use pulsed width modulation (PWM). A pulsed frequency modu-

lation (PFM) is sometimes used in combination with PWM for the lower power levels toincrease the light load eciency [27][17].

3.2.5 RF Power AmplierSome researchers design their converter together with a RF PA and integrate the

circuits together [21][27]. Others propose converters designed for use with existing orctional RF PA [17][33][9].

Digital pre-distortion helps improving the linearity in power ampliers. The con-cept is to change the modulated signal in the DSP so that it becomes linearized afteramplication. The distortion applied often approximates the inverse complex gain char-acteristics of the power amplier. Simple polynomial based pre-distortion using singleand two coecients shows signicant improvements in the PA's linearity [33].

3.2.6 Eciency ImprovementThe eciency improvements reported range from x1.64 to x5 times improvement in

overall eciency [11][33]. These improvements are compared to a RF PA with a xedsupply. The results should be taken with advance because as they are dependant on thePDF, suburban or urban situations, battery supply and the PA characteristics.A Buck-Boost converter proposal states x4.43 eciency improvement resulting in 88%increase in battery lifetime assuming that the PA consumes 20% of the total transceiverpower [27]. Another proposal claims x1.64 power usage eciency with 64% increase inbattery life for a Boost converter [11].These results are very promising for the future of WCDMA mobile phones but a universalbenchmark is clearly needed in order for the results to be comparable.

3.2.7 BatteryPortable electronic devices are getting smaller and smaller but the batteries are most

generally the limiting factor in further miniaturization [32]. Today, most mobile phonesare powered by a single cell Li-ion single cell rechargeable battery today with a voltagespan of Vbat = 2.7V to 4.2V .Fuel cells are emerging as an alternative power source for portable applications, oeringmuch more energy density than the usual rechargeable batteries. These fuel cells are notrechargeable but rellable. Although the rst fuel cells already appeared on the market

14

in 2004, they have not gained much popularity yet and nearly all portable devices stillrely on the Li-ion battery [32].Most researchers design their converters suited for the Li-ion battery but some make theirdesign more general or "future proof" by accepting an input voltage range suited for fuelcells, NiMH, NiCd and Li-ion batteries [26].

3.2.8 Fixed Levels or Dynamic Output VoltageThe RF PA's supply voltage is controlled by a DC-DC converter so that it supplies

only the voltage needed at each time according to the transmitted power level. Thereare strict rules about linearity in the transmission and the linearity can be increased bysupplying more voltage to the RF PA, i.e. operate in deeper power back-o from thePA's compression point.

There are three dierent ways for the converter to supply the voltage, with a xedvoltage, xed voltage levels or by dynamically changing the supply voltage. The RF PAwith a xed supply has unacceptable eciency but it can be increased dramatically whenchanging between few levels of supply voltage [9][23]. This means that the converteroperates in power back-o most of the time. The eciency can be improved further bysupplying the voltage dynamically according to the power level of the transmitted signal[27][11][21][33].A converter dynamically changing its output voltage according to the transmitted powerlevel usually has a high switching frequency and a PWM control. The switching loss atlight loads becomes a dominant factor ruining the eciency. Therefore, a PFM controlis often incorporated with a PWM controller to work at low xed voltage level at lightloads and thereby increasing the eciency [33][27].

3.2.9 Component SizeThe size of passive components changes with an inverse proportion of the switching

frequency. Hence, higher switching frequency allows smaller components. A Buck con-verter design uses an inductor of L89MHz = 9.1nH and a capacitor C89MHz = 100nFwhich is quite small[9]. By comparing those components with a Buck-Boost converterwith a 500kHz switching frequency that has L500kHz = 2.2µH and C500kHz = 47µF[27] so the components size in this example are close to be inversely proportional to theswitching frequency.

15

Chapter 4

Problem Statement

Taking into consideration the previous work presented, it is desirable to consider thepossibilities of designing a DC-DC converter with high switching frequency to improvethe RF PA eciency. It was stated that high switching frequency allows the use ofsmall components and introduces less spectral emission. Small compenents in portableapplications are always preferable and in best case they are small enough to be integrated.A converter with less spectral emission allows the RF PA to operate more eciently dueto the eciency-linearity trade o. These are the key advantages of higher switchingfrequency.

Therefore, it is of main interest to know if high switching frequency and modernsemiconductor devices can oer better improvement in the overall eciency of the RFPA than existing solutions and if so, what frequency is the optimal?

In order to nd an answer to this question, a converter that can step up and downwith a switching frequency of 20MHz will be designed and implemented.

The DC-DC converter has to be able to convert the input voltage to higher (step up)or lower (step down) voltage and it has to operate eciently over wide output voltageand load range.

The converter performance goals are as follows:

• Input voltage range, Vbat = 2.7V to 4.2V

• Output voltage, Vout = 0.6V to 3.6V

• Output current, Iout = 50mA to 0.7A

• Output ripple voltage, ∆v ≤ 50mV

• Operating frequency fs = 20MHz

• Output slew rate and settling < 30µs

The main restriction for the prototype is that it can probably not be tested thoroughlywith a real RF PA because of limited time. Therefore, the results will be mostly basedon theoretical simulations and calculations instead of actual measurements. This limitsthe design to the rst phase of testing and it will not be improved further.

16

Chapter 5

Topologies and Control Circuitry

The chapter starts with a comprehensive comparison and discussion of dierent topolo-gies to perform the step up and step down voltage conversion. The most suitable topologyfor the task is selected. The possibilities in controlling circuitry are then discussed withemphasis on the switching frequency selection.

5.1 Regulator TopologiesThe supply voltage required for the linear RF PA can be higher or lower than the

Li-ion battery voltage, depending on the transmitting power level. Thus, a step up andstep down power conversion is required.

In mobile phone applications, low cost and small size are the key design requirements.External components, like a lter inductor, input and output capacitors should be as fewas possible to minimize cost and printed circuit board (PCB) space.

Several circuit topologies can be used to accomplish the step up and step down powerconversion. The following sections will discuss briey some well known topologies con-sidering the overall eciency, complexity and number of external components. The ref-erences for this chapter are [10] [26] and [7].

5.2 Boost/LDOThe Boost with a LDO is the topology that is commonly used today, see gure 5.1.

It consists of a Boost converter followed by a low drop-out (LDO) regulator. The LDOregulator is very common in mobile applications. It is a linear regulator that is cheap andeasy to implement. It has low noise and low ripple compared to the switching convertersand has excellent transient response [15]. It uses a feedback to adjust the conductanceof the passing element (preferably a MOSFET). The passing element conduction is lin-early related to an error signal from an error amplier. This is equivalent to havingan adjustable resistor instead of a MOSFET. LDOs are often used in combination withother converters in battery powered applications where the input voltage changes. Thecombined converter uses LDO when the input voltage gets close to the regulated outputvoltage.

The combined Boost/LDO solution is simple and cheap. The big drawback is thatthe LDO has very poor eciency. By looking at the probability density function ofWCDMA power levels and comparing it to the required supply voltage as in gure 3.1,

17

Figure 5.1: Boost and LDO converter

Figure 5.2: Boost converter followed by a Buck converter.

we see that the converter works in step-down mode most of the time so the eciency ofthis setup depends heavily on the LDO. The supply voltage curve on gure 3.1 is therequired voltage for a Buck-Boost application to fulll the ACLR requirements at thecorresponding power level for a typical RF PA [17].

It is therefore important to get good eciency for the step-down power conversion.In order to achieve that, the LDO could be replaced with a Buck converter to get greatereciency for step-down conversions. This topology uses one inductor, two capacitors andthree switches.

5.3 Boost Followed by a BuckThe simplest improvement of the Boost/LDO would be a Boost followed by a Buck,

see gure 5.2. The Boost would supply a constant voltage to the Buck with high ef-ciency. The Buck would be more advanced and could dynamically adjust its outputaccording the RF signal.This solution requires four external components and two controllers making this an expen-sive, bulky and complex solution. The eciency could be really good though, especiallywith intelligent control of a bypass circuit that is on when the battery voltage does notneed a step-up conversion.

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Figure 5.3: Inverting Buck-Boost

5.4 Inverting Buck-BoostThe Buck-Boost is the simplest topology discussed here, see gure 5.3. The polarity

of the output is opposite to the input supply voltage so an inverter is required. Invertercircuit will increase the complexity of the circuit and decrease the eciency.

The circuit only has one inductor and one capacitor but the inverter makes this nota feasible solution.

5.5 Non-Inverting Buck-BoostA non-inverting Buck-Boost is a cascade combination of a buck converter and a boost

converter where a single inductor and a single capacitor are used, see gure 5.4. The factthat it uses only one inductor and one capacitor makes this topology an attractive choice.The control scheme is complex because the circuit uses four switches in synchronous modeand the eciency degrades with the number of switches, especially in this high frequencyapplication.

Since the input and output capacitor currents are square waves in nature, they intro-duce much ripple and electromagnetic interference (EMI). Capacitor with low equivalentseries resistance (ESR) and equivalent series inductance (ESL) is needed to minimizeswitching ripple. An extra LC lter could be needed in order to fulll the output ripplerequirements and therefore doubling the external components.The maximum voltage stresses of all switching devices do not exceed Vinmax and the max-imum current stress is approximately Iinmax . Hence, high eciency can be achieved withlow loss switching devices. The converter should be operated at three modes, changingat the optimum voltage levels; buck, buck-boost and boost. The fourth mode could beimplemented for light loads, for example a PFM control instead of PWM to achieve bettereciency.

5.6 CukThe Cuk converter would need an inverter because the polarity of the output is nega-

tive, see gure 5.5. The converter uses current capacitive energy transfer from the inputto the output, this introduces extra power loss in the extra capacitor. An extra inductoris also used at the input. Number of components and the need for an inverter makes this

19

Figure 5.4: Non inverting Buck-Boost

Figure 5.5: Cuk converter

topology unattractive but it has one interesting advantage, the currents drawn from boththe input decoupling capacitor and output capacitor are not sharp square waves whichresults in lower noise and lower EMI.

5.7 SEPICThe SEPIC converter is similar to Cuk as it uses current capacitive energy transfer

from the input to the output, see gure 5.6. Two capacitors and two inductors makethis topology bulky and expensive but its simplicity makes it deserve a second look. Thevoltage and current stress on the switching devices are fairly high. Both switches have tosustain a voltage stress of at least V inmax +Vout and the switch current of Iinmax +Ioutmax .As a result, the eciency suers and the cost increases. Another drawback is high outputswitching noise due to the pulsating output current.

5.8 ZetaZeta is similar to the SEPIC except it overcomes the drawback of pulsating output

current by producing continuous output current, see gure 5.7. This will reduce theoutput voltage ripple. The high voltage stress and current stress in switching devices alsoresult in lower eciency, large size and high cost.The controller required is quite simple since the Zeta converter has only one switch.

20

Figure 5.6: Sepic converter

Figure 5.7: Zeta converter

5.9 Topology SummaryEvery topology has its drawback; high cost, low eciency or complexity. No topology

seems to be the ultimate solution to the problem after this brief overview. The complexitydepends on the number of switches and the control complexity. Moreover, the eciencydepends on many factors but the estimations are made with a high switching, low powerapplication in mind.

The topologies that need a polarity inversion will not be considered further becausethey would require an inverting circuit whitch increases cost, lowers eciency and in-creases complexity. Isolated topologies require a transformer which is not convenient forportable applications.

The non inverting Buck-Boost is a good candidate for the application using only twoexternal components and giving good eciency. The SEPIC also seems to be a goodchoice giving high eciency and simplicity. The inverse SEPIC, the Zeta, would be bet-ter for the application because it has an inductor on the output suppressing the outputripple.This narrows down the selection to two topologies: Non inverting Buck-Boost and Zeta.The Buck-Boost needs more complex controlling scheme than the Zeta because it hasfour switches in total. The Zeta has only two switches. The Buck-Boost only uses twoexternal components wile the Zeta uses four.

In few words, the Buck-Boost is cheaper and more complex while the Zeta is simpler

21

but more expensive. The main dierence between the two can be noticed by examining thevoltage and current stress in the switching devices. High voltage stress and current stressin switching devices result in a lower eciency, large size and high cost. Both switchesin the Zeta converter have to sustain a voltage stresses of at least Vinmax + Voutmax and aswitching current of Iinmax + Ioutmax . The voltage stress of the switches in the Buck-Booston the other hand do not exceed Vinmax and the maximum current stress is approximatelyIinmax .

The non inverting Buck-Boost with a single inductor and capacitor minimizes thevoltage and current stresses in all switches, thus optimizing eciency [7]. Therefore, thenon inverting Buck-Boost topology is chosen for further development.

5.10 ControllerHaving chosen a suitable topology the appropriate control circuitry can be examined.

The main design topics of a controller will be briey discussed in the following sections.

5.11 Modulation SchemesPWM is a popular modulation and can be found in many commercial controllers. This

control system regulates the output voltage by changing the duty cycle D of the switchwith pulse width modulation. The switching frequency is xed so the eciency at lightloads is low because the switching loss is so high compared to the output power. Pulsedfrequency modulation (PFM) could be used in combination with PWM to achieve goodeciency at light loads. The duty cycle in PFM is xed but with changing frequencydepending on the feedback signal.

Another option to accompany PWM at light loads is to skip pulses in a Pulse SkippingModulation.

5.12 Comparison Signal - Triangle/SawtoothThe measured output voltage is compared with a triangle or a sawtooth wave with

a comparator to generate a PWM signal. The sawtooth wave rises quickly upwards andslowly descends downwards. The triangle wave ramps upwards and then downwards athalf the cycle.

The sawtooth wave is better because of the steep ank. It gives better accuracy whencomparing the wave to the feedback signal. Slow ramp is subject to deviation errors inPWM of the duty cycle leading to errors in the output voltage.

5.13 Envelope SensingThe transmitted signal has a base band envelope that indicates the signal power level

that is being transmitted. The DC-DC converter has to sense the transmitted signalto adjust its output accordingly. This can be done in several ways and three optionsare considered here; envelope following, envelope tracking and power level following. The

22

envelope following setup follows the envelope completely to adjust the output power. Peakload eciency is improved but higher bandwidth and switching frequency requirementresult in lower eciency at light loads. The setup needs an RF delay line.

Envelope tracking does not follow the envelope completely. The root mean square(RMS) value of the envelope signal is measured and the converter adjusts its outputvoltage accordingly. This results in lower peak power eciency but higher light loadeciency because of lower switching frequency. No RF delay line is needed.

In a WCDMA architecture, transmitted power is adjusted by 1dBm every 666µs asrequested by the base station. This change is much slower than the base band envelopesignal which has a bandwidth of 3.84MHz. Power level following requires less switchingfrequency than the two other methods but still the converter has to be able to change itsoutput voltage and settle in less than 50µs.

5.14 Switching FrequencyThe switching frequency is an important factor for the converter design. The switching

frequency has to be enough to give the converter a bandwidth so it is able to change thesupply voltage in 50µs when the RF PA has to change its power level every 666µs asrequested by the base station. There is a 50µ window in the beginning of every transmitcycle in which the voltage adjustments have to be completed. [17].

High switching frequency helps the use of smaller sized external components and tomeet the spectral emission requirements but the converter eciency degrades becauseof more switching losses. The switching frequency should be selected carefully so thatharmonics fall outside the transmission bandwidth, which is 1920MHz − 1980MHz forWCDMA applications. It can be shown that for a PWM signal of any duty cycle, onlyodd harmonic components exist [9]. A switching frequency of fs = 20MHz will thereforeresult in a harmonic distortion at the 97th harmonic at 1940MHz and on both sides of thetransmission frequency ft, fsideband1 = ft−fs and fsideband2 = ft+fs. This means that therecan be three switching harmonics in the WCDMA transmission bandwidth. In order toprevent the harmonics in the WCDMA transmit bandwidth, a switching frequency largerthan the WCDMA bandwidth is required. A switching frequency of 65MHz, for example,would introduce harmonics at 65MHz = 1885MHz and at 65MHz = 2015MHz. More-over, the harmonics in the signal sidebands would fall outside the bandwidth. Therefore,no harmonics exist in the transmission frequency at. Figure 5.8 depicts the switchingfrequencies that do not have switching harmonics in the WCDMA transmit bandwidth.A switching frequency larger than 60MHz is needed to prevent sideband harmonics andhence, all interference.

5.15 Controller SummaryPWM seems to be the best solution for this application according to previous research.

A PWM is therefore chosen. A switching frequency of 20MHz is chosen to examine theadvantages of high swithing frequency. Commercial controller solutions oer PWM con-trollers with a switching frequency up to 4MHz. It is possible to buy controllers withhigher switching frequency but they are constructed with two or more phases which does

23

Figure 5.8: Switching frequencies that do not introduce switching harmonics from thefundamental frequency at the 1920MHz - 1980MHz WCDMA transmission bandwidth.

not increase the control bandwidth. Therefore a controller has to be designed from scratchto achieve a 20MHz switching frequency operation. A sawtooth signal will be used forthe PWM generation because it oers better precision than the triangular signal. Thecontroller should also be able to operate with PFM at light loads to improve the lightload eciency.

A non-inverting Buck-Boost converter requires a complex controller circuit. In addi-tion, the propagation delay in the controller's components becomes a limiting factor at20MHz frequency levels resulting in smaller overall control bandwidth of the converter.

24

Chapter 6

Dynamically Adaptive Buck-BoostConverter

This chapter describes the design of a non inverting Buck-Boost converter that candynamically adjust its output voltage according to the base band envelope signal. Thisconverter is going to operate at 20MHz and is supposed to shed some light on theestimation if it is of interest to operate at higher switching frequency than actually neededto solve the problem.

6.1 The TopologyThe non inverting Buck-Boost1 converter with one inductor and one capacitor was

chosen in the previous chapter because it uses very few components and minimizes thevoltage and current stresses in all switches and thereby optimizing the eciency [7].

The Buck-Boost converter combines the step-down and step-up abilities of the Buckand Boost converters. Detailed derivation of the theory behind the Buck and Boostconverters is found in appendix A. The Buck-Boost is, like explained above, a cascadecombination of a Buck converter and a Boost converter where a single inductor and singlecapacitor is used for both, see gure 6.1. The diode is often replaced with a MOSFETto lower the voltage drop over the component when conducting. The MOSFET thatreplaced the diode is then driven with inverse control signal of the other MOSFET.

This is the converter of interest that will now be designed.1Hereafter mentioned only as Buck-Boost

Figure 6.1: Buck-Boost circuit with four switches.

25

Figure 6.2: Buck-Boost converter when in state 1.

6.2 Buck-Boost StatesThe Buck-Boost has four switches and four dierent possible states. These dierent

states that have to considered are

State Q1 Q31 ON ON2 ON OFF3 OFF OFF4 OFF ON

Where Q1 and Q2 are the switches for the Buck stage and Q3 and Q4 are the switchesfor the Boost stage.

In state 1 the main switches in the Buck and Boost stages, Q1 and Q3 respectively,are turned on. This means that Q1 connects Vbat directly to the inductor L and Q3connects the other end of the inductor to ground like on gure 6.2. The voltage over theinductor and capacitor current in state 1 are

vL1 = Vg iC1 = −V

R(6.1)

This is the same as the Boost converter in equation A.28 when the switch is on.In state 2 the switch Q3 turns o and the circuit is as shown in gure 6.3. This is

the same circuit as when the Buck converter switch is turned on. The voltage over theinductor and current through the capacitor is

vL2 = Vbat − Vout iC2 = iL − Vout

Rload

(6.2)

where Vout is the same as the output voltage when neglecting the voltage drop overQ4. State 2 can be found in both the Buck converter and the Boost converter.

Both switches Q1 and Q3 are turned o in state 3 which gives a negative voltage overthe inductor

26

Figure 6.3: Buck-Boost converter in state 2.

Figure 6.4: Buck-Boost converter in state 3.

vL3 = −Vout iC3 = iL − Vout

Rload

(6.3)

where iL is negative. Figure 6.4 shows the Buck-Boost converter in state 3. Thisequation is the same as equation A.10 for the Buck converter when the switch is o.

In state 4 the Q1 is o and Q3 on, this means that the voltage over the inductor wouldbe 0V because the inductor would be connected to ground at each side. By observingthe PWM modulation in gure 6.10 it can be seen that this state is not possible. If Q1is o then Q3 can not be on because Voffset > 0 and therefore FBBuck > FBBoost. Thecomparators compare if FB > Sawtooth.

An updated table for the states with the voltage values gives

State Q1 Q3 vL

1 ON ON Vbat

2 ON OFF Vbat − Vout

3 OFF OFF −Vout

4 OFF ON Not possibleBy observing the table it can be seen the converter's three modes. When Q3 is con-

stantly o we have a regular Buck converter switching with Q1 and Q2 with two states.When Q1 is constantly on we get a Boost converter switching Q3 and Q4 with two states.

27

In between we have the Buck-Boost mode that can enter all three states.

The converter is controlled with two dierent PWM signals. PWMBuck controls Q1and Q2 while PWMBoost controls Q3 and Q4. The converter conversion ratio from inputto output is

M(D) =DBuck

1−DBoost

(6.4)

When DBuck = 1 we get the same conversion ratio as for the Boost converter inequation A.30 and when DBoost = 0 we get the conversion ratio as for a Buck converterin equation A.3.

6.3 Power Stage DesignThe power stage of the Buck-Boost converter consists of an LC lter and four MOS-

FET switches. The converter is shown in gure 6.1 and its transfer function dependson the operating mode. The transfer functions in the s-domain for the converter [10]operating in Buck mode is

GBuck(s) =Vout

D

1 + s√

L

Rload

√1L

+ s2 1LC

(6.5)

The transfer function for the Buck-Boost mode is

GBuck−Boost(s) =

Vout

(1−D)− s VoutL

(1−D)3Rload

1 + s√

L

(1−D)2Rload

√1L

+ s2 LC(1−D)2

(6.6)

and the Boost transfer function is

GBoost(s) =

Vout

D(1−D)− s VoutL

D2(1−D)3Rload

1 + s√

L

(1−D)2Rload

√1L

+ s2 LC(1−D)2

(6.7)

The goal of the project is to switch at high frequency to minimize the component sizein the LC lter and to minimize switching harmonics in the WCDMA bandwidth. Highswitching loss comes with high switching frequency so MOSFETs with good switchingperformance are desired for the application.

The lter inductor and capacitor were chosen to get a certain inductor ripple current.The LC lter was designed for the worst case situation when the converter is workingat its maximum power delivering maximum current to the load with minimum batteryvoltage. This happens in Boost mode when the duty cycle is at its maximum. Theconverter's maximum duty cycle in Boost mode is

28

DmaxBoost= 1− Vbat − 2Vswi

Voutmax + 2Vswi

= 0.35 (6.8)

where Vswi is the voltage drop over the switches when conducting. The voltage dropis assumed to be around 0.1V . The inductor size was chosen to cope with a peak-to-peakcurrent ripple of ∆IL = 1A [26]. The inductor size is estimated to be

L =(Vbatmin

− 2Vswi)Dmax

fs∆IL

= 43nH (6.9)

The minimum capacitor needed to limit the output voltage ripple to ∆Vout = 30mVwith an estimated ESR of ESRC = 10mΩ and a peak inductor current of ILpeak

= 2A is[26]

Cmin =∆IoutmaxDmax

fs(∆Vout − ILpeakESRC)

= 1.25µF (6.10)

It is recommended to select a capacitor that is larger than the calculated minimumto be sure to get the desired voltage ripple [14]. A capacitor of C = 15µF was chosen tobe on the safe side. This yields an output voltage ripple of ∆Vout = 20mV .

High switching frequency leads to high switching loss so the switches must have goodswitching performance to keep it at minimum. Switching performance of a MOSFET isdependent on its gate charge and capacitance. The conduction loss is also important sothe switch must also have low on resistance.

A P-channel MOSFET (PMOS) switch has three times the resistance of an N-chanelMOSFET (NMOS) device of equal dimensions because electrons have three times themobility of holes in silicon [35].

6.4 Compensation NetworkThe compensation network stabilizes the DC-DC converter's feedback control loop by

shaping the error amplier's frequency response with external components.The frequency response of the converter's power stage is shown in gure 6.5. Note

that the horizontal axis is in rad/s and not in Hz. A widely used compensation networkwith 3 poles and 2 zeros, type III, shown on gure 6.6, is used for compensation [14].

The transfer function for this compensation network is

H(s) = −(

1

sR1(C2 + C1)

)(s(R1 + R3)C3 + 1)(sR4C2 + 1)

(sR3C3 + 1)(sR4( (C1C2)(C1+C2)

) + 1)

(6.11)

29

105

106

107

108

109

1010

90

180

270

360

P.M.: −1.61 degFreq: 2.09e+06 rad/sec

Frequency (rad/sec)

Pha

se (

deg)

−100

−50

0

50

100

G.M.: −14.7 dBFreq: 1.16e+06 rad/secUnstable loop

Open−Loop Bode Editor (C)

Mag

nitu

de (

dB)

Figure 6.5: Bode plot of the open loop converter in Boost mode with maximum dutycycle.

Figure 6.6: 3-pole, 2-zero Compensation network

30

The two zeros in the compensation network are to compensate for the gain reduc-tion and phase shift of the output lter poles. The rst pole at the origin,

(1

sR1(C2+C1)

),

sets the open loop crossover frequency. The second pole at 1/(2πR3C3) was positionedclose to the zero in the output lter in order to keep the 20dB/decade roll-o in thegain response at high frequencies. The third pole, 1

2πR4(C1C2)

(C1+C2)), was placed at a frequency

between fs/2 and fs to minimize high frequency noise at the PWM input.

The LC lter designed in section 6.3 has two poles located at

f0 =1−DmaxBoost

2π√

LC= 129kHz (6.12)

These poles can be seen on gure 6.5 marked with an X. The zero is located at

fRHP =(1−D)2Rload

L= 9.7MHz (6.13)

This zero is often called the right half plane (RHP) zero. When a RHP zero ispresent, like in Buck-Boost and Boost mode, it is dicult to obtain good phase marginin conventional single loop feedback systems having wide bandwidth [10].

The compensator network integrator gain needs to be −39dB in order to achieve acrossover frequency of 2MHz. This can be seen from gure 6.5. In volts the gain is11.2mV , hence

1

2πfsR1(C1 + C2)= 0.0112 (6.14)

In practice, C2 C1,

C2 =1

2πR1(0.0112)= 0.7pF (6.15)

A capacitor C2 = 0.7pF is used. R4 was chosen to position a zero at fz = 38.7kHzto compensate for the LC lter poles

R4 =1

2π(19.1× 106)C2= 5.8kΩ (6.16)

A resistor R4 = 5.6kΩ was used. R3 and C3 were chosen to provide a zero at fz anda pole at fp = 16MHz to compensate for the RHP zero

fz =1

2π(R1 + R3)C3(6.17)

31

fp =1

2πR3C3(6.18)

By solving for C3 in equation 6.17 and substituting fp for (2πR3C3) we get thefollowing results

C3 =

1fz− 1

fp

2πR1= 41nF (6.19)

A capacitor C3 = 42nF was used. Now we can solve R3 easily using equation 6.18

R3 =1

2πfpC3= 24Ω (6.20)

C1 is chosen to provide a pole at fp2 = 19.1MHz which is very close to fs. Assumingthat C3 C1 we get

C1 =1

2πfp2R4= 1.45pF (6.21)

Now the compensation network is completed and the closed response is shown in gure6.7. Poles are marked on the gure with an X and the zeros are marked with an O.

6.5 Pulse Width ModulationFigure 6.8 shows the setup for the PWM scheme. There are two comparators, one for

the Buck duty cycle and one for the Boost duty cycle. The Buck comparator comparesa sawtooth signal with the feedback voltage with an oset Voffset.

The Boost comparator compares the sawtooth signal with the unchanged feedbackvoltage. The oset is employed so the converter can work in the three modes and makesmooth transitions from one mode to another [22]. The modes are; Buck, Buck-Boostand Boost. Figure 6.9 shows the three modes. The Boost mode is deliberately madesmaller than the Buck mode because the converter operates only in Boost mode whenthe output voltage is supposed to be higher than the battery voltage and that has lessprobability than the Buck mode.

Equation 6.8 calculates the maximum Boost duty cycle to be 35% so the Boost moderegion is considerable smaller than the Buck mode region which stretches from 10% to100%. The converter is in Buck mode when the feedback voltage is lower than thesawtooth minimum voltage. Then the Boost duty cycle is 0% and the two switches Q1and Q2 are switching.

32

Figure 6.7: Bode plot of the compensated converter in Boost working at maximum dutycycle.

Figure 6.8: PWM stage. Comparators compare feedback voltages with a sawtooth signal.

33

Figure 6.9: The three operating modes of the Buck-Boost converter.

The converter enters Boost mode when the feedback voltage added with the osetvoltage gets larger than the maximum voltage of the sawtooth, i.e. when the Buck dutycycle is 100%. Switches Q3 and Q4 are active in Boost mode. The Buck-Boost mode isin between and its size is dependent on the oset voltage Voffset, sawtooth oset and itspeak-to-peak voltage and the feedback peak-to-peak voltage. All switches are active inBuck-Boost mode. Figure 6.10 shows the waveforms discussed when the converter is inBuck-Boost mode.

6.6 Propagation DelayPropagation delay in the feedback control loop degrades the response of the converter.

Some components in the controller delay the response of the converter by a few nanosec-onds. The biggest factors in limiting the converters response are the comparator in thePWM part and logical gates in the dead time control (DTC). The propagation delay canbe modeled as

Ddelay(s) = e(−tds) (6.22)

in the s-Domain. The td is the propagation delay in the feedback loop. With a switchingfrequency of 20MHz we get a period of 50ns so the propagation delay can be a bigproportion of the switching period. Considerable delay of 20ns was assumed in thecalculations.

6.7 Sawtooth SignalGenerating a 20MHz sawtooth signal or a triangle wave was considered a challenging

and time consuming task. It was therefore decided to use an external sawtooth generatorbased on an existing design [13].

34

Figure 6.10: PWM waveforms in Buck-Boost mode.

6.8 Oset CircuitFigure 6.11 shows an adder circuit that can add and subtract.The output voltage from the circuit on the gure is

Vout =n∑

i=a

ViMi −m∑

j=1

VjMj (6.23)

where Va to Vc are negative inputs and V1 to V3 are positive inputs. Each signal canhave a gain of M which is determined by the resistor value. All resistors are calculatedfrom the feedback resistor Rf except the resistor connected to ground which depends onS. S is calculated from all the gains

S = 1 + (n∑

i=a

Mi −m∑

j=1

Mj) (6.24)

In our case we just want to add two values together and therefore we get a negative Svalue and a negative resistor value. This can be avoided by selecting one negative inputthat is in fact zero. Figure 6.12 shows the oset circuit designed to give the feedbackerror signal an oset. It adds the feedback signal Vfb with a reference voltage Vref to getan oset of Vref .

The gain of the resistor R1 can be selected in such a way that the S value will get veryhigh. That will make the resistor R2 on the gure small compared to the other two, Rref

and Rfb. This is good because then smaller current will ow back to the error amplierin the compensation network and steadier oset circuit operation will be achieved.

35

Figure 6.11: Adder circuit used for the oset circuit.

Figure 6.12: Oset circuit (adder) for the Buck feedback error signal.

36

Figure 6.13: Dead-time control for the Buck stage.

6.9 Dead Time ControlA dead-time control (DTC) provides a small period of time during each cycle when

both MOSFETs in Buck or Boost mode are turned o. This is done to limit the duty cycleto some value and to prevent shoot through current when both MOSFETs are turnedon. For example, if both Q1 and Q2 are turned on at the same time the battery will beshort-circuited directly to ground.

Figure 6.13 shows a simple DTC for the Buck stage. It consists of three logicalgates; AND, NAND and NOR. The signal VL1 is the voltage at the inductor input andit indicates that the Q1 switching transition has been processed. The Vq2 signal doesnot turn o before VL1 has gone low. This acts as the dead time between the switchingtransitions. Each gate has some propagation delay and it will add on to the dead time.When the PWM signal goes high the Vq2 goes low after d0 seconds which is equal tothe propagation delay in the NOR gate, d0 = dNOR. The Vq1 control signal goes lowd1 = dNAND + dAND seconds after the Vq2 has gone low. When the PWM signal goeslow the VQ1 goes high after d1 seconds and Vq2 goes high d0 seconds after that when VL1

goes low following Vq1 change. Figure 6.14 depicts the transitions of the DTC logic forthe Buck stage.

The DTC for the Boost stage is very similar to the Buck DTC. The Boost DTC usesthe voltage on the other end of the inductor, VL2 to measure the transitions. Figure 6.15shows the circuit for the Boost DTC. It uses a NAND, AND and an OR gate and thedead-time between transitions is similar to the Buck DTC.

Figure 6.16 shows the waveform of the DTC logic for the Boost stage.The propagation delay in the logical gates is typically between 1ns and 5ns. This is

quite a large proportion of the total period of 50ns for the 20MHz switching frequency.The propagation delay in the feedback loop will degrade the converter's control bandwidthso the DTC should have as little propagation delay as possible.

6.10 Soft Start-Up CircuitA soft start-up circuit is necessary in order for the converter not to go immediately

into Boost mode with a 100% duty cycle. This would result in too much inductor currentthat can destroy the MOSFETs. It is desirable to employ a circuit that limits the duty

37

Figure 6.14: Waveform presentation of the DTC logic for the Buck stage.

Figure 6.15: Dead-time control for the Boost stage.

38

Figure 6.16: Waveform presentation of the DTC logic for the Boost stage.

cycle.A simple solution is to use a RC circuit connected to Vbat and a diode. The RC circuit

is connected to the feedback signal by the diode. This circuit is shown in gure 6.17.This has the eect that the feedback voltage rises according to the RC circuit's time

constant

Vfbsoft= Vfb(1− e

−tRC ) (6.25)

or in the s-Domain

Figure 6.17: Soft-start circuit to limit the converter's duty cycle.

39

Figure 6.18: Illustration of the PWM signal when soft start-up circuit is used.

Vfbsoft=

Vfb

1 + RCs(6.26)

And when Vfbsoftrises above the feedback voltage Vfb, the diode has the aect that

the RC circuit does not aect the circuit any more.The RC values should be chosen according to

RC = − t

ln(Vfb−Vfbsoft

Vfb)

(6.27)

The maximum feedback voltage is Vfb = 0.9V and given a minimum start-up time of44µs a R = 1k8Ω resistor and a C = 100nF is needed. The start-up time is highest whenVbat = 4.2V but the start-up time is 75µs when Vbat = 2.7V . Figure 6.18 demonstrateshow the soft start-up circuit limits the duty cycle when the converter starts up.

One problem is that the current in the soft start-up circuit has to be considerablelarger than the current coming from the error amplier in the feedback loop. In a lowpower environment like this it is not feasable to waste current and the error ampliercould be damaged when it tries to supply all the current it can. Hence, this seems to bean elegant solution but as it turns out, it is not practical for this application.

6.11 Duty Cycle LimitingInstead of applying a soft start-up circuit, like proposed in the previous section, a

duty cycle limiter could be implemented. The maximum current can be restricted bylimiting the maximum duty cycle of the converter. One way to do this is to add onecomparator that compares the sawtooth signal with a reference voltage which determines

40

Figure 6.19: Duty cycle limiting circuit for the Boost PWM.

the maximum duty cycle. The output is the maximum allowable duty cycle PWM signalwhich is put through an AND gate with the regular PWM Boost signal. Hence, a PWMsignal for the Boost stage that never exceeds the maximum duty cycle is generated.Figure 6.19 shows the duty cycle limiting circuit.

The upper comparator has two inputs, the sawtooth signal and a reference voltagethat determines the maximum duty cycle. The output is a maximum duty cycle PWMthat is put through an AND gate with the regular Boost PWM signal.

6.12 Design SummaryFigure 6.20 shows the complete circuit for the Buck-Boost converter with a feedback

compensation network, oset circuit, duty cycle limiting, PWM and logic.The Buck-Boost converter has now been designed and the next step is to simulate

and calculate its frequency responce and eciency.

41

Figure 6.20: The Buck-Boost with feedback and control circuitry.

42

Chapter 7

Simulations and Calculations

It is always good to check out the functionality of the design by simulating it beforeimplementation as this often makes it possible to detect minor errors in advance thatotherwise might become critical.

The following chapter deals with the simulation process and discusses Bode plots ofthe open and closed-loop response of the Buck-Boost converter. The converter and con-troller were simulated in Matlab Simulink when it experiences a worst-case 1dBm changein the RF PA output power and the slew rate and settling was observed. Finally, theswitching loss of a MOSFET and the converter eciency will be calculated when it op-erates in Buck mode.

All Matlab programs are available in appendix B.

7.1 Bode PlotsThe Bode plot shows the magnitude and phase response of the converter which indi-

cates important characteristics of the converter like the stability and bandwidth.In order to keep constant output voltage under all conditions a feedback is needed.

In the voltage mode controller the output voltage is feed back and the controller adjuststhe duty cycle accordingly. Adding a feedback loop can cause a stable system to becomeunstable. The feedback loop then fails to regulate the system at the desired quiescentoperating point, and oscillations are usually observed. This is undesirable and shouldbe avoided. Even though the feedback system is stable, there is a possibility that thetransient response has ringing and overshoot [10].

One way to estimate stability is using the phase margin test which is sucient fordesigning most voltage regulators. The phase margin ϕm is dened as the phase loop gainat the frequency when the magnitude of the loop gain is unity (0dB) added with 180 ora whole multiple of 180. The frequency when the magnitude of the loop gain is unityis called the crossover frequency fc and it is a measure of the bandwidth of the controlsystem. The phase margin should be positive in order to ensure stability and preferablybe between 30 and 60 (as a rule of thumb). A positive phase margin indicates thatthere are no right half-plane poles in the transfer function of the closed loop system.This phase margin test is easy to make while there is only one crossover frequency.

It is generally desirable to achieve very high gain at low frequencies to minimize errorin the output voltage. The crossover frequency should be in the range of 1/6 to 1/10 of

43

Figure 7.1: Bode plot of the uncompensated Buck-Boost converter in the worst casescenario.

the converter switching frequency [10].

Figure 7.1 shows a Bode plot of the uncompensated converter for the case when thebattery is supplying the minimum voltage of Vbat = 2.7V and the converter has to deliverits maximum voltage of Vout = 3.6V . This is the worst case scenario.

Figure 7.2 depicts the worst case scenario for the closed loop operation. The circuithas a phase margin ϕm = 55 and gain margin of 9dB. The bandwidth is in rad/secin the gure but when transferred into Hz a bandwidth of 1.6MHz is obtained. TheBuck-Boost converter designed in chapter 6 is designed to have a phase margin ϕm > 45

for all possible situations with a 20ns propagation delay. The bandwidth goes down to200kHz in some situations and sometimes it is more than 2MHz, it all depends on thevoltage conversion at each time.

Figure 7.3 shows a Bode plot of the Buck-Boost converter when working in a moretypical environment. The battery supply is Vbat = 3.5V and the converter is supplyingVout = 0.85V . From the probability density function in chapter 3 we know that thisoutput voltage has high probability. When the output voltage gets lower the convertershifts to a control method with a better light load eciency.

Figure 7.4 shows a Bode plot of the converter when Vout = Vbat = 3.6V . The converterhas a bandwidth of 2.13MHz in this situation which is as high as it gets.

44

−100

−80

−60

−40

−20

0

20

40

60

80

100

Mag

nitu

de (

dB)

103

104

105

106

107

108

109

1010

−180

0

180

360

540

720

900

Pha

se (

deg)

Bode DiagramGm = 9.04 dB (at 2.82e+007 rad/sec) , Pm = 55 deg (at 1.01e+007 rad/sec)

Boost mode: Vbat = 2.7V, Vout =3.6V, Iout = 0.6A w/Prop.delay (rad/sec)

Figure 7.2: Bode plot for the worst case scenario when the Buck-Boost converter isoperating at full output power with minimum battery supply.

−200

−150

−100

−50

0

50

Mag

nitu

de (

dB)

103

104

105

106

107

108

109

1010

−180

0

180

360

540

720

900

Pha

se (

deg)

Bode DiagramGm = 34.5 dB (at 3.66e+007 rad/sec) , Pm = 69.8 deg (at 1.7e+006 rad/sec)

Buck mode: Vbat = 3.5V, Vout =0.85V, Iout = 0.06A w/Prop.delay (rad/sec)

Figure 7.3: Bode plot of the Buck-Boost in a typical working environment.

45

−100

−80

−60

−40

−20

0

20

40

60

80

100

Mag

nitu

de (

dB)

103

104

105

106

107

108

109

1010

−180

0

180

360

540

720

900

Pha

se (

deg)

Bode DiagramGm = 6.19 dB (at 2.75e+007 rad/sec) , Pm = 44 deg (at 1.34e+007 rad/sec)

Buck−Boost mode: Vbat = 3.6V, Vout =3.6V, Iout = 0.6A w/Prop.delay (rad/sec)

Figure 7.4: Bode plot of the Buck-Boost converter when Vout = Vbat = 3.6V .

7.2 Matlab SimulinkMatlab Simulink was used to simulate the Buck-Boost converter mathematically and

it gives a simplied insight into the circuits functionality. Simulink oers a library ofpower electronic components that look good but have strange behavior so it was decidedto keep it simple and stick to the basic mathematical transfer functions for the compo-nents. Figure 7.5 shows the Buck-Boost converter with four switches.

One way to simulate the circuit is to model the inductor L and capacitor C asimpedances in the s-Domain. This gives an inductor transfer function of

tf(L) = Ls (7.1)and a capacitor transfer function of

tf(C) =1

Cs(7.2)

where the initial current and voltage over the components is assumed to be zero. Itis hard to simulate the actual switching transitions and ow of current so it is best tocalculate the voltage over the inductor at each state. Then the current owing throughthe inductor and through the capacitor are known.

46

Figure 7.5: A Buck-Boost converter with four switches.

There are four switches Q1, Q2, Q3 and Q4 in the synchronous Buck-Boost converterbut it can be assumed that two of them, Q2 and Q4, are at the inverse position of theother two. In section 6.1 it was found that the converter has three dierent modes andthree dierent states. The three states are

State Q1 Q3 VL

1 ON ON Vin

2 ON OFF Vin − VL2

3 OFF OFF −V4 OFF ON Not possible

The states and modes are related as

Mode State 1 State 2 State 3Buck X XBuck-Boost X X XBoost X X

On gure 7.6 depicts the simulation setup in Matlab Simulink.Figure 7.7 then shows the Buck-Boost converter block from gure 7.6. The gure

shows the logic used to dene the state. The three switches determine whether the stateis on or o and only one state can be active each time. The voltage at the inductorsinput is multiplied by the s-Domain conductance of the inductor

VL1

1

Ls= IL (7.3)

this gives the current owing through the inductor. The current is then multiplied bythe s-Domain resistance of the capacitor to get the output voltage Vout

47

Figure 7.6: Simulation setup for Matlab Simulink.

Figure 7.7: The Buck-Boost converter simulation block in Matlab Simulink.

IL1

Cs= Vout (7.4)

Figure 7.6 shows the setup when simulating worst case 1dBm change in output power.This happens when the battery supply is as low as it gets and when the converter has tosupply the maximum output power when the RF PA transmitting power level is 28dBm.The RF PA has to change the output power level by 1dBm every 667µs by demand fromthe base station. The converter has to have 30µs output slew rate and settling. There isa 50µ window in the beginning of every transmit cycle in which the voltage adjustmentshave to be completed [17].

The minimum supply voltage for RF PA transmitting at 28dBm is estimated to beVout = 3.6V with a load current of Iload = 650mA. This means that in these calculationsthe RF PA has an eciency of 27% at full output power, which is lower than expectedfrom a commercial RF PA. Most RF PAs for WCDMA solutions have more than 30%

48

Figure 7.8: Simulated output voltage when RF PA changes output power level from27dBm to 28dBm.

eciency at 28dBm. The estimated supply voltage for a 27dBm output power level is3.55V with Iout = 523mA.

Figure 7.8 shows the change in the output voltage of the converter when the RF PApower level changes from 27dBm to 28dBm.

The voltage is able to settle easily within 10µs of the change which is inside the 50µsframe discussed above. The simulated output voltage rise and voltage fall is shown ingure 7.9 and in gure 7.10.

The output voltage ripple at 3.6V output voltage when changing between 3.55V and3.6V as is shown on gure 7.11. The voltage ripple is only 1.5mV but the waveform hasa downswing that makes the total ripple 3.5mV . In reality, output voltage ripple willprobably be larger.

When the converter is turned on it goes quickly into Boost mode with high duty cycleuntil it achieves the desired output. The rise time from Vout = 0V to Voutmax = 3.6Vis typically less than 15µs but too high duty cycle in Boost mode results in too highinductor current. This could harm the components and therefore a soft turn on circuit isrequired that limits the start up current and hence the start up time.

7.3 Switching Loss and EciencySome estimations of the switching performance of a MOSFET are necessary to assist

with the component selection. Three dierent calculations, based on a well known simpleestimation [14][10], more advanced calculation from the book Grundlæggende Eektelek-tronik [20] and calculations from an article by Jess Brown [6], were made to nd theswitching loss in a MOSFET switching at 20MHz and 33.6MHz. A switching frequencyof 33.6MHz was chosen because it is among those frequencies that only introduce oneswitching harmonic in the WCDMA transmission bandwidth. It also shows the switchingperformance of the MOSFET for higher switching frequency.

49

Figure 7.9: Simulated output voltage rise when RF PA changes output power level from27dBm to 28dBm.

Figure 7.10: Simulated output voltage fall when RF PA changes output power level from27dBm to 28dBm.

50

Figure 7.11: Simulated output voltage ripple when RF PA changes output power levelfrom 27dBm to 28dBm.

The MOSFET used for the calculations is a N-channel PowerTrench MOSFET fromFairchild Semiconductor [29], called FDG6317. It was chosen for the application becauseit has very low gate charge and good switching abilities.

Figure 7.12 shows the eciency of a Buck converter with a switching frequency of20MHz neglecting the diode power dissipation. The input voltage is Vin = 3.6V in allthe eciency calculations. In the gures the horizontal axis shows the load current andit is from Iout = 0.05A to 0.6A which equals an output voltage from Vout = 0.4V to3.6V . From the gure it is can be seen that the two advanced calculations align tightlyto one another while the simple estimation shows much less eciency. This dierenceappears because the simple estimation uses only the rise and fall time of the MOSFETto calculate the switching loss. The other two calculations take into account the gateresistance, gate charge and the capacitance among other characteristics of the MOSFETto calculate the switching loss and divide the switching cycle into six transitions. Hence,giving more accurate results.

These results give an idea of what the eciency of the Buck-Boost converter willbe. The calculations are only for a Buck converter but the Buck-Boost operates mostof the time in Buck mode or in Boost mode where the switching losses are similar.Additional losses will be the power dissipation in the extra switch that acts as a diodeand a conduction loss of the switch that is not switching. The eciency in Buck-Boostmode is harder to calculate but that mode should be as small as possible and is undesired.

Figure 7.13 shows the eciency of a Buck converter with a switching frequency of33.6MHz.

By comparing the graph with gure 7.12 we can see that the eciency dierence isnot that much. This indicates that the switching performance of the MOSFET is verygood and that the conduction loss is a larger factor than the switching loss.

51

0 0.1 0.2 0.3 0.4 0.5 0.60

10

20

30

40

50

60

70

80

90

100

Output Current (A)

Effi

cien

cy

MOSFET FDG6317 Vbat = 3.6V fs = 20000000Hz

SimpleGrund. EffektJess Brown

Figure 7.12: Eciency of a Buck converter with a switching frequency of 20MHz assuminga lossless diode.

0 0.1 0.2 0.3 0.4 0.5 0.60

0.05

0.1

0.15

0.2

0.25

Output Current (A)

Pow

er (

W)

MOSFET FDG6317 Vbat = 3.6V fs = 33600000Hz

SimpleGrund. EffektJess BrownConduction loss

Figure 7.13: Eciency of a Buck converter with a switching frequency of 33.6MHz as-suming a lossless diode.

52

0 0.1 0.2 0.3 0.4 0.5 0.60

0.05

0.1

0.15

0.2

0.25

Output Current (A)

Pow

er (

W)

MOSFET FDG6317 Vbat = 3.6V fs = 20000000Hz

SimpleGrund. EffektJess BrownConduction loss

Figure 7.14: Power dissipation in a Buck converter with a switching frequency of 20MHz.Three dierent calculations of the switching loss and one of the conduction loss.

Figure 7.14 depicts the three dierent calculations of the switching loss and one of theconduction loss. At low output power the switching loss is dominant but at high outputpower the conduction loss is dominant. This is as expected.

At higher switching frequency the switching loss gets larger and can be higher thanthe conduction loss at all times.

Figure 7.15 shows the same calculations as in gure 7.14 but for a converter with aswitching frequency of 33.6MHz. Two calculations agree on that the switching loss ishigher than the conduction loss most of the time. The most complex calculation from thearticle by Jess Brown [6] states that the conduction loss is still larger at high output power.

From these calculations we can estimate the eciency of a Buck-Boost converter inBuck mode. The only dierence from the previous calculations is that the circuit has anextra switch at the output that is closed at all times. It dissipates a bit of power as canbe seen on gure 7.16 which shows the total eciency of a Buck-Boost converter in Buckmode.

53

0 0.1 0.2 0.3 0.4 0.5 0.60

0.05

0.1

0.15

0.2

0.25

Output Current (A)

Pow

er (

W)

MOSFET FDG6317 Vbat = 3.6V fs = 33600000Hz

JBrownTIGrund. EffektConduction loss

Figure 7.15: Power dissipation in a Buck converter with a switching frequency of 33.6MHz.Three dierent calculations of the switching loss and one of the conduction loss.

0 0.1 0.2 0.3 0.4 0.5 0.60

10

20

30

40

50

60

70

80

90

100

Output Current (A)

Effi

cien

cy

Efficiency in Buck mode with MOSFET FDG6317 Vbat = 3.6V fs = 20000000Hz

Figure 7.16: Calculated eciency for the Buck-Boost converter in Buck mode.

54

Chapter 8

Physical Realization

With the knowledge from the simulations, it is time to put the design to a real test.Beneath is a description of the implementation process.

In appendix B are the datasheets for all the components used in the design as well asOrcad les to create the PCB.

8.1 LC FilterA L = 43nH air core inductor was chosen. Air core inductor was chosen because it

does not suer from core loss. The core loss of most power ferrite materials rise rapidlywith frequency in the megahertz range. This means that the component size does notalways decrease with increased frequency, and can even get worse [10]. The air coreinductor can be employed eectively if it is operated at higher frequencies to compensatefor reduced inductance because the core material has higher permeability than air.A ceramic C = 15µF capacitor was chosen for the LC output lter to minimize ripple.

8.2 MOSFETIt was decided to try to drive the MOSFETs directly from the comparators in the

PWM stage. The required gate drive current is derived by simply dividing the gatecharge QG by the required switching time Ts [24]. The LMV7219 [31] comparator cansink and source Igate = 20mA so a MOSFET with a gate charge lower than

QG < IgateTs = 20mA× 50ns = 1.0nC (8.1)would work. The N-MOSFET FDG6317 [29] has a typical gate charge of QG = 0.76nC

and excellent switching abilities. It is specially designed to improve the eciency of smallswitching DC-DC converter providing low on resistance and low gate charge. Its PMOScounterpart FDG6318 [30] has very similar characteristics although it has a little bitlarger gate charge of QG = 0.86nC.

One potential problem could arise. The MOSFETs rise time delay is typically 6.5nsand the rise time itself is 9.0ns. The turn o delay is 14ns and the fall time is 5.5ns.This adds up to a shocking 35ns which makes the feedback loop delay of the DC-DCconverter considerably large compared to the switching period which is only 50ns. Thesecharacteristics from the datasheet are measured under the condition of ID = 1A drain

55

current, RGEN = 6Ω gate resistance, VGS = 4.5V and VDS = 10V . These delays willhopefully improve for the better in lower current and voltage environment.

Another known problem is that the MOSFETs might not tolerate the maximum cur-rent. The MOSFETs were selected considering that they would be working in their abso-lute maximum drain current region when the converter supplies maximum output powerand could therefore possibly fail. The PMOS has a maximum continuous drain currentof IDPcont

= −0.5A and the NMOS has IDNcont= 0.7A. For a maximum pulsed current

with a 300µs long pulse and 2% duty cycle, the PMOS can tolerate IDPpulsed= −1.8A

and the NMOS can tolerate IDNpulsed= 2.1A.

The maximum current stress lands on the PMOS connecting the battery to the induc-tor when the converter supplies maximum output power in Boost mode. The maximumoutput power from the converter is PDCmax = 3.6V.7A = 2.52W so with a convertereciency of 80% the input power would have to be PBatmax = 2.52/0.8 = 3.15W . Thisleads to a maximum DC current of 1.17A plus inductor ripple which is more than theMOSFET can tolerate in continuous conduction. This could be solved with a bypassMOSFET that tolerates more current but this was not included in this rst version ofthe prototype.

Because of the power control, the phone will not transmit at maximum output powerfor a long time except in data mode. Still, the MOSFET will have a hard time conductingthe maximum current.

The MOSFETs were selected for the prototype despite the fact that they are not ratedfor the needed current. The FDG6317 and FDG6318 MOSFETs were selected becausethey are superior compared to other MOSFETs regarding switching abilities and willhopefully give better eciency.

8.3 ComparatorThe LMV7219 [31] is designed for the single cell Li-ion battery supply and has a

propagation delay of 7ns. It can supply rail-to-rail output. The 7ns propagation delayis a big proportion of the 50ns period but no better integrated circuit (IC) was found forthe task. The comparators with less propagation delay usually had some problems withthe supply range.

8.4 Error AmplierAn operational amplier AD8656 [1] with a high bandwidth of 28MHz and low noise

was chosen for an error amplier and for the error signal oset circuit.

8.5 Logic GatesThree types of logical gates were used, AND gates [2], NOR gates [3] and one OR

gate [4]. The gates with as low propagation delay as possible were chosen so that thelogic would have minimum eect on the feedback propagation delay.The design used also a NAND logical gate for inverting the signal which could also be

56

solved with a NOR gate. Three AND gates were used, one for the duty cycle limitingcircuit and two for the DTC. The AND gate used has three inputs where the third inputcould be used for some kind of light load modulation. Three NOR gates and one ORgate were also used in the DTC circuitry.

8.6 SnubberBuck-Boost converters experience often ringing at the input of the inductor VL1. The

ringing is generated because of parasitic inductance and capacitance in the switchingdevices and PCB. Its frequency is

fring =1

2π√

LparCpar

(8.2)

To compress the ringing, a capacitor was selected so that the resonant frequency wouldbe halved. This indicates that the added capacitor is three times bigger than the parasiticcapacitance Csnub = Cpar/3. The resistor was selected to be equal to the characteristicimpedance of

Rsnub =1

2πCparfring

(8.3)

8.7 PCB RealizationThe circuit board was made by printing the circuit on a transparent paper and de-

veloping it on a two layer copper plate with ultra violet light. The plate was put intodeveloping liquid NaHO until the circuit lines were clearly visible. The board was thenwashed in water and put into etching acid that removed all copper that was not underthe circuit lines. When the acid had removed all the unwanted copper the board was putin acetone and sandpapered with a very ne pad. Finally the PCB was put in a tin bathso the tin would stick with the circuit lines.

Figure 8.1 shows the Buck-Boost PCB. The layout was deliberately made so thatthere was enough space between each component. This made all soldering work andalternations easier but introduced a lot of parasitic inductances and capacitances.

Parasitic inductance of 15nH can be expected from each centimeter of connectingroute. Hence, the L = 43nH inductor value was hard to realize because an equivalentinductance comes from a 3cm wire.

Figure 8.2 shows the sawtooth PCB.

57

Figure 8.1: The Buck-Boost PCB.

58

Figure 8.2: The 20MHz sawtooth signal generator PCB.

59

Chapter 9

Measurements

The prototype Buck-Boost converter designed in chapter 6 was assembled in a PCBand tested for functionality and performance. This chapter presents and discusses theresults from the performance measurements.

The measurements were made with a LeCroy waverunner LT584L digital oscilloscopewith Lecroy probes.

9.1 Noise ProblemThe converter was rst tested with an open loop and the oset voltage to the Buck

PWM set to produce a certain duty cycle. The battery supply was Vbat = 3.6V and thesawtooth circuit was connected to the Buck-Boost circuit by a short coax cable.

Figure 9.1 shows the sawtooth signal (red) where it is measured on the Buck-BoostPCB and the green signal is the sawtooth measured from the sawtooth PCB.

Considerable noise can be seen in the sawtooth signal on the Buck-Boost PCB. Thefeedback signal from the compensation network was very noisy and the voltage oset Opamp made it even worse. The feedback signal that the Buck comparator had to comparethe sawtooth with to generate the Buck PWM was plagued with noise as can be seen ingure 9.2.

The signal has more than 2V peak to peak jumps as can be seen in the gure. Thesawtooth signal operates at 0.4V to 1.2V so the comparator produces a PWM signal thatis jumping from 0% to 100% duty cycle all the time. It is clear that the Buck-Boostconverter design is far from being able to operate in its original state.

9.2 PCB Layout ConsiderationsA lot of noise was experienced in the circuit to begin with. This was due to long

routes between components and from the components to the bottom ground plane. De-graded signal integrity was seen on the same line measured few centimeters apart. Morethought should have been put in designing the layout of the PCB to avoid the noise.Shorter connections and ground plane on both sides of the PCB would have helped withthe noise problem. Furthermore, the ground for the power stage and the control circuitrycould also have been separated and only connected in one place to minimize interferencebetween the two parts.

60

Figure 9.1: Sawtooth signal measured at the sawtooth PCB (Green) and at the Buck-Boost PCB (red).

Figure 9.2: Feedback signal from the oset circuit to the Buck comparator.

61

Figure 9.3: Ringing at the inductor's input.

As an attempt to improve the performance, additional ground connections were addedin all places where possible and existing ground connections fortied. Capacitors werealso added on the Vbat supply lines that were far from the supply voltage and low passlters were added on the input to the comparators. This made a remarkable dierenceand the converter's functionality improved dramatically.

Considerable ringing of 160MHz was experienced at the inductor's input as can beseen on gure 9.3.

A RC snubber with Rsnub = 6.8Ω and Csnub = 147pF was added to suppress theringing. Figure 9.4 shows the resulting waveform. The snubber was actually added whilethe circuit was still very noisy and it can be noticed on the varying duty cycle on thegure.

9.3 DTCFigure 9.5 shows a gate signal of a MOSFET operating in Buck mode. The rise and

fall times are around 4ns which is satisfactory.The gate signals for Q1(blue) and Q2(red) are shown in gure 9.6. There is a consid-

erable dead time between the transitions, around 6ns in the rising ank and 4ns in thefalling ank.

62

Figure 9.4: Voltage waveform at the inductor with a RC snubber.

Figure 9.5: Rise and fall time measurements of a MOSFET gate signal.

63

Figure 9.6: DTC in Buck mode.

9.4 Stability ProblemAfter securing an open loop operation the loop was closed. The converter could

regulate to some extent but was clearly unstable. The converter could supply voltage upto around 3V where it entered the Buck-Boost mode and there it lost regulation aftersome while. The instability resulted in a regulation swing at frequencies around 10kHzthat could easily be heard. Figure 9.7 shows the output voltage swing of 0.5V .

Regardless of the control method, unstable operating point can generally be stabilizedby either increasing the output capacitance, decreasing output capacitance, or increasingthe ESR of the output capacitor [37]. The capacitor value was made larger without muchsuccess but after trying a 1µF capacitor the converter started to function in a stablemanner. Some unstability was noticed at high output levels but nothing like before.

9.5 Output Voltage RippleThe output voltage ripple was expected to be lower than 50mV . In open loop opera-

tion with a duty cycle of around 35% in Buck mode the converter has a maximum outputvoltage ripple of 42mV . The ripple waveform is shown in gure 9.8.

After lowering the output capacitor and closing the control loop the ripple got larger.This was due to smaller capacitance and to minor stability problem that aected theoutput voltage in a way that it was swinging a little bit at high output voltages.

64

Figure 9.7: Unstable output voltage.

Figure 9.8: Output voltage ripple in Buck mode.

65

Figure 9.9: The Buck PMOS gate signal(blue) and the resulting switching transition(red)at half duty cycle.

9.6 Switching ProblemFor some reason the Q3 NMOS did not switch even though the gate signal was correct.

Moreover, the PMOS Q4 did not switch because it is dependant on the Q3 transition.This restricted the converter to the Buck mode. With time and patience the matterwould surely be solved but neither was left.Figure 9.9 shows the Q1 Buck PMOS switching transition (red) and its gate signal (blue).This shows how the transitions are supposed to be. The average rise and fall times are3.92ns and 1.86ns respectively. The rise time delay is not noticable but the fall timedelay is around 2− 3ns.

Figure 9.10 shows the same measurement but for a duty cycle of 20%. At this dutycycle the MOSFET is just able to nish its rising transition before it has to fall again.The rise time is similar as before but the fall time is a bit longer. The transition cycleis approximately 12ns. This indicates that the MOSFET could possibly switch normallyat a switching frequency of 80MHz.

9.7 EciencyThe converter was tested briey for eciency in Buck mode. A constant Rload = 15

was used while the output voltage was changed from 0.63V to 3.15V with a batterysupply of Vbat = 3.6V . Figure 9.11 shows the results.

The measured eciency is much lower than estimated in gure 7.16 on page 54. Bycomparing the values at Iout = 0.1A and at Iout = 0.2A the estimated eciency is 50%and 73% respectively but the measured eciency is 26% and 54% respectively. Hence,

66

Figure 9.10: The Buck PMOS gate signal(blue) and the resulting switching transi-tion(red) at small duty cycle.

Figure 9.11: Eciency of the Buck-Boost converter in Buck mode.

67

the Buck-Boost converter has at least 20% less eciency than estimated. The reasonfor this low eciency can be many things. The last value in gure 9.11 is particularlyinteresting. At that point the converter is not switching at all. This means that theconduction loss is almost 34%.

Two things can be done to improve the performance. Firstly, the converter showedsome signs of instability when the output voltage got closer to the maximum output volt-age. This aects the converter operation and leads to increased power dissipation. Withsome alternations in the LC lter a stable operation at all condition should be achievable.Secondly, the dead-time shown on gure 9.6 could be made smaller to improve eciencyand there is room for that, especially at the rising anks.

The maximum output voltage was Vout = 3.15V with a Vbat = 3.6V supply. Thismeans that when the converter is operating at 100% duty cycle a 0.5V drop is over thetwo PMOSFETs Q1 and Q4 and over the inductor. This results in a conduction loss of34% which indicates that the switches are a big bottleneck preventing the converter fromattaining better eciency. The MOSFETs have a resistance of RDS(ON) = 0.6Ω whenthey are turned on with a gate to source voltage of −VGS = 3.15V . This leads to a voltagedrop of 0.27V which means that much power is dissipated in Q1 and Q4. The remainingvoltage drop of 0.18V and the assosiated power dissipation must come from the inductorand the circuit routes unless the RDS(ON) value for the MOSFETs is far from being right.

9.8 SummaryThe Buck-Boost converter is limited to the Buck mode operations. Many things could

not be tested because of this restriction, for example the output voltage span over all theinput voltage span, output current range, eciency in Buck-Boost or Boost mode andoutput slew rate for the worst case scenario.

The converter has small output voltage ripple < 50mV when operated under stableconditions and uses fairly small components in the LC lter, L = 43nH and C = 1µF . Itregulates the output nicely when the battery supply changes but has still some indicationof instability seen at high output voltages. This could be optimized with dierent valuesof the LC lter.

The MOSFETs seem to dissipate much more power when conducting than estimated.They were selected because of their switching abilities but their downside is the conduc-tion power loss. A bypass MOSFET over Q1 with low on resistance should be imple-mented to improve the eciency when the Buck duty cycle is 100%.

68

Chapter 10

Conclusion

A design of a Buck-Boost converter intended to improve the linearity-eciency tradeo in WCDMA mobile phones has been presented. Although showing good signs of per-formance abilities on the drawing board it failed to impress after physical realization.Because of time constraints the converter could not be improved further for optimizationor thoroughly tested for its performance.

The converter displayed good switching abilities and low output voltage ripple (<50mV ). It uses fairly small components in the LC lter, L = 43nH and C = 1µF andthe DTC logic, PWM, oset circuit and compensation network worked ne except forminor stability problems.

One unsolved problem remains, the Boost NMOS switch (Q3) was constantly o anddenied to switch. This limits the converter to Buck mode operation. Many things couldnot be tested because of this restriction, for example the output voltage span over allthe input voltage span, output current range, eciency in Buck-Boost or Boost modeand output slew rate for the worst case scenario. It would also have been interestingto measure the transmission bandwidth and measure the spectral emission due to theswitching harmonics. High switching frequency should introduce less distortion in thetransmission bandwidth and hence, allowing the RF PA to operate more eciently withless linearity.

The eciency was tested for the converter in Buck mode and showed a maximumeciency of 66% when the converter was not switching at all. This indicates a lot ofunpredicted conduction losses. When delivering 0.2A in Buck mode the converter hadan eciency of 54% but the calculations stated an eciency of 73%. It is unlikely thatthe converter can improve the PAE of the RF PA signicantly in its current state butthere is room for improvements. The converter's stability could be optimized with carefulselection of the output lter and the dead time between switching transitions could beshortened.

The PCB layout was not good enough. Shorter connections and ground plane on bothsides of the PCB would have helped with the noise problem that was experienced. Theground for the power stage and the control circuitry could also have been separated andonly connected in one place to minimize interference between the two parts.

A MOSFET has generally a trade o between the on resistance and switching per-formance. MOSFETs with extremely good switching performance and high on resistancewere selected which resulted in too much conduction loss. Some compromise should havebeen done between the two extremes.

69

It is hard to answer the main question of the problem statement, if it is of interestto use a DC-DC converter with high switching frequency to improve the RF PA's e-ciency, since the example prototype did not work properly. From the obtained results,it can though be concluded that a DC-DC converter operating at 20MHz is very di-cult to build and the existing MOSFETs do not oer enough quality for ecient DC-DCconversion.

The output lter components are not small enough to be integrated and the trans-mission bandwidth is not free from spectral emissions from the switching harmonics. Theswitching frequency has to be closer to 100MHz so that the components are integratableand the switching harmonics do not interfere with the transmission bandwidth.

The answer to the question is therefore no. It is not of interest to use a switchingfrequency in the region of 20MHz using commercial semiconductor devices to improvethe RF PA eciency. Simpler and cheaper solutions can obtain better average eciencyof the RF PA. Remarkably lower spectral emission is not likely to account for the loweciency associated with high switching frequency converter.

70

Appendix A

Appendix

This appendix covers the basic theory of the two basic DC-DC converter topologiesBuck and Boost from which the non-inverting Buck-Boost is based on. Buck converterwill be discussed rst and then related to Boost converter. The theory is necessary forthe discussion in chapter 6 where a non-inverting Buck-Boost is designed.These basic converters consist of a power stage and a control circuit. The power stageperforms the basic power conversion from the input voltage to the output voltage andincludes switches and an output lter [25].The reference for the analysis in this chapter is mainly from the book Fundamentals ofPower Electronics [10] unless other stated. This summary is based on previous work ofmine [34]. General expressions from reference [10] will be used throughout the chapter.

A.1 BuckThe most common and simple converter is the Buck converter, sometimes called the

step-down converter. The output voltage is always less than the input voltage in thesame polarity and is not isolated from the input.The simplest DC-DC conversion is obtained by a simple voltage divider as seen on gureA.1.

The desired output voltage is adjusted with a variable resistor. This method is obvi-ously low ecient. The eciency would be for example 50% if an output voltage of halfthe input voltage was desired.

Figure A.2 shows another approach with an ideal switch. The switch output voltagevs(t) is equal to the converter input voltage Vg when the switch is in position 1, and isequal to zero when the switch is in position 2. The dissipated power in the switch is

Figure A.1: Voltage divider. The input voltage is divided between two resistors.

71

Figure A.2: Insertion of a switch can change the DC component of the voltage.

Figure A.3: A low pass LC lter added to remove the switching harmonics.

ideally zero. The switch position is varied periodically such that vs(t) is a rectangularwaveform having frequency fs and period Ts = 1/fs. The duty cycle D is dened as thetime when the switch is in position 1. Hence, 0 ≤ D ≤ 1.The switch changes the DC component of the voltage. The DC component of a periodicwaveform is equal to its average value given by Fourier analysis

Vs =1

Ts

∫ Ts

0vs(t)dt = DVg (A.1)

Vs =1

Ts

∫ Ts

0vs(t)dt = DVg (A.2)

From this equation we can see that the DC output voltage is directly proportional tothe duty cycle D and hence

D =Vs

Vg

(A.3)

A Buck converter with a duty cycle of D = 0.5 would produce an output voltage of halfthe input voltage magnitude with 100% eciency given ideal conditions. In practice theoutput voltage waveform vs(t) contains undesirable harmonics of the switching frequency.These harmonics are removed by using a LC low-pass lter as seen in gure A.3.

If the lter corner frequency f0 is less than the switching frequency fs then the lterpasses only the DC component of vs(t). The LC lter corner frequency is dened as

72

Figure A.4: A control system with a feedback adjusts the duty cycle to regulate theoutput voltage.

f0 =1

2π√

LCHz (A.4)

The ideal switch in gure A.2 is replaced by a diode and a switched mode semicon-ductor device (e.g. MOSFET) in practice which is controlled with a control system, seegure A.4. The diode is used to conduct current when the MOSFET is not conductingand stopping current from owing backwards through the inductor. This is equivalentto a switch in position 2. The control system regulates the output voltage by changingthe duty cycle D of the switch. It determines the duty cycle by measuring the outputvoltage or current and comparing it to a reference signal.

Given ideal lossless switch, diode, inductor and capacitor then this DC-DC convertercan have eciency close to 100%.

It is impossible to build a perfect low-pass lter that rejects all the components atthe switching frequency and its harmonics. There is always some amount of the highfrequency harmonics that reaches the output. Hence, the output voltage is a sum of theDC component and this high frequency AC component

v(t) = V + vripple(t) (A.5)

The output voltage switching ripple should be as small as possible and it is often agood approximation to assume that the switching ripple is much smaller than the DCcomponent

73

Figure A.5: Buck converter circuit when the switch is in position 1.

v(t) ≈ V (A.6)

This approximation simplies the analysis of the converter waveforms. It is possibleto solve converters exactly without using this approximation but it gives very similarresults. It is not of interest to describe the ripple exactly since it is small and undesired.

By integrating the inductor voltage we can nd the inductor current. When the switchis in position 1 the circuit is equal to gure A.5

The inductor voltage is then

vL = Vg − V (A.7)

by using approximation in equation A.6. Now we can nd the inductor current byuse of the denition

vL = LdiL(t)

dt(A.8)

The slope of the inductor current waveform during the interval when the switch is inposition 1 is

diL(t)

dt=

vL(t)

L≈ Vg − V

L(A.9)

The slope is constant and therefore we can conclude that with the switch in position1, the inductor current increases linearly.

Now we take a look at what happens when the switch is in position 2 as in gure A.6.

74

Figure A.6: Buck converter switch when the switch is in position 2.

Here the voltage source Vg is bypassed and the left side of the inductor is connectedto ground. This means that Vg = 0 in our calculations. The voltage over the inductor isnow

vL(t) = −V (A.10)

as seen from equation A.7 when Vg = 0. The inductor voltage is constant when theswitch is in position 2 as well as in position 1. The slope can be found by substitutingequation A.8 for vL(t) in equation A.10

diL(t)

dt≈ −V

L(A.11)

Hence, the inductor current has a negative constant slope when the switch is in posi-tion 2.

The inductors current waveform will look like a triangle when looking at a steady-state waveform over a switch transition from position 1 to position 2. The waveform willrst rise with a slope from equation. A.9 for a time interval of DTs and then fall with aslope from equation A.11 for a time (1−D)Ts. The inductors current ripple ∆iL is equalto half the peak-to-peak value of the inductor current waveform or more precisely

∆iL =Vg − V

2LDTs (A.12)

Typical values of the inductor current ripple lie in the range of 10% to 20% of thefull load value of the DC component I. It is desirable to have small ripple. If the rippleis large the peak currents of the inductor and of the semiconductor devices will increase.This results in increased size and cost of the components. The inductor value can bechosen by solving equation A.12 to fulll certain ripple requirements

L =Vg − V

2∆iLDTs (A.13)

75

In steady-state the net change in inductor current over one switching period Ts iszero. By using the voltage relation over an inductor from equation A.8 and integratingover one switching period we get

iL(Ts)− iL(0) =1

L

∫ Ts

0vL(t)dt (A.14)

This equation says that the net change in inductor current over one switching periodis proportional to the integral of the voltage over the inductor. But because the converteris in steady-state we get that iL(0) = iL(Ts) and therefore

0 =∫ Ts

0vL(t)dt (A.15)

By dividing each side with Ts in equation A.15 we get that the average value of theapplied inductor voltage is equal to zero in steady-state, that is, it has no DC component.We can relate this result to the duty-cycle by

1

Ts

∫ Ts

0vL(t)dt = D(Vg − V ) + D′(−V ) (A.16)

Where D′ is the the fraction of the time Ts the switch spends in position 2, it isdened as (1−D). Solving for V in equation A.16 using equation A.15 and noting thatD + D′ = 1 gives

V = DVg (A.17)

which is the same result as we got previously in equation A.1. Equation A.17 is oftenwritten in the form

M(D) =V

Vg

= D (A.18)

where M(D) is called the voltage conversion ratio of the output to the input voltageof a DC-DC converter.

If we now take a look at the capacitor and apply the same arguments. The currentthrough a capacitor is dened as

iC(t) = CdvC(t)

dt(A.19)

76

and integrating over one switching period gives

vC(Ts)− vC(0) =1

C

∫ Ts

0iC(t)dt (A.20)

The net change of the voltage over the capacitor over one switching period must bezero in steady-state. Hence, the integral of the capacitor current should be zero, i.e. theaverage value, or the DC component, of the capacitor current must be zero in steady-state. This result is similar to that for the inductor except for that the average value ofthe applied inductor voltage was equal to zero instead of the current for the capacitor.

Finding the output voltage ripple is not as easy as nding the inductor current ripple.The capacitor current can be expresses as follows

iC(t) = iL(t)− V

R(A.21)

It is assumed that the capacitor gets charged when the switch is in position 1 anddischarged when it is in position 2. There is no net change in the capacitor current overone period and its DC value is zero as mentioned above. If the the peak-to-peak changein the capacitor current during the switching period is ∆I then we get

iC(0) = iC(Ts) = −∆I

2iC(DTs) =

∆I

2(A.22)

which states that when the capacitor is fully discharged its value is −∆I2

and when itis fully charged its value is ∆I

2.

Since the current through the capacitor varies linearly, the average charging currentis half of its peak value of the triangular waveform. If a periodic signal has zero DC valueover its cycle period, its average is dened based only on its positive part. Hence

IC,avg =∆I

4(A.23)

The capacitor charge (Ampére-seconds) is

q = It = CV (A.24)

By assuming that the capacitor charging time is half the cycle period, Ts

2, and using

the average charging current from eq. A.23 we can dene the output voltage ripple fromequation A.24

77

Figure A.7: Boost converter circuit with an ideal switch.

Figure A.8: Boost converter circuit when the switch is in position 1.

∆v =IC,avg(Ts/2)

C=

∆ITs

8C(A.25)

This equation can be used to select appropriate capacitor for the output LC lter tolimit the output voltage ripple

C =∆ITs

8∆v(A.26)

A.2 BoostThe Boost converter is similar to the Buck converter except that it produces an output

voltage of greater magnitude than the input. The ideal switch model is shown in gureA.7 but in practice it is replaced by a MOSFET and a diode like in the Buck example.

Let us now apply the principles from the previous analysis about the Buck converterto nd the steady-state output voltage and inductor current for this converter. Thesmall-ripple approximation is applied like before.

When the switch is in position 1 we get the circuit shown in gure A.8.The inductor voltage and capacitor current for this setup, using that v ≈ V , are given

by

78

Figure A.9: Boost converter circuit when the switch is in position 2.

vL = Vg iC = −V

R(A.27)

When the switch is in position 2 like in gure A.9 the values change to

vL = Vg − V iC = iL − V

R(A.28)

and then we get that

1

Ts

∫ Ts

0vL(t)dt = D(Vg) + D′(Vg − V ) = 0 (A.29)

From equation A.29 we can derive the desired expression of the relation between theinput and output voltage

V =Vg

1−D⇒ M(D) =

V

Vg

=1

1−D(A.30)

where M(D) is the voltage conversion ratio as mentioned before.

Lets take a look at the inductor ripple current and output voltage ripple using thesame method as for the Buck converter. When the switch is in position 1 like in gureA.8 the slope of the inductor current is

diL(t)

dt=

vL(t)

L=

Vg

L(A.31)

and the slope of the capacitor voltage waveform is

dvC(t)

dt=

iC(t)

C=−V

RC(A.32)

79

It is enough to look at the slopes when the switch is in position 1 because there is nonet change over one period. The change over the time DTs is equal to the slope, when inposition 1, multiplied by DTs. Hence, the inductor current ripple is

2∆iL =Vg

LDTs ⇒ ∆iL =

Vg

2LDTs (A.33)

and the output voltage ripple is

−2∆v =−V

RCDTs ⇒ ∆v =

V

2RCDTs (A.34)

These equations can be used to select the appropriate values for the LC output lterto obtain a given inductor ripple and output voltage ripple magnitude.

80

Appendix B

Appendix

A DVD with various les and programs made is attached to the thesis. These lesare intended for the curious reader and for further development.

B.1 Matlab• Power stage design

• Feedback compensation

• Simulink simulation

• Eciency Calculations

• Oset circuit calculation

• Hysteresis calculation in the sawtooth circuit

• Slow start-up circuit

• MOSFET switching loss

• Bode plots for all operation modes

B.2 PSpice• Buck-Boost circuit layout to make the PCB

• Sawtooth circuit layout to make the PCB

B.3 DatasheetsDatasheets for all the components used in the project are also included on the DVD.

B.4 ThesisThe thesis is available in PDF and PS format.

81

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