Technical University Tallinn, ESTONIA 1 Overview: Fault Modelling • Faults, errors and defects • Stuck-at-faults (SAF) • Fault equivalence and fault dominance • Redundant faults • Transistor level physical defects • Mapping transistor defects to logic level • Fault modelling by Boolean differential equations • Functional fault modelling • Faults and test generation hierarchy • High-level fault modelling • Fault modelling with DDs
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Technical University Tallinn, ESTONIA 1 Overview: Fault Modelling Faults, errors and defects Stuck-at-faults (SAF) Fault equivalence and fault dominance.
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Technical University Tallinn, ESTONIA 1
Overview: Fault Modelling
• Faults, errors and defects• Stuck-at-faults (SAF)• Fault equivalence and fault dominance• Redundant faults• Transistor level physical defects• Mapping transistor defects to logic level• Fault modelling by Boolean differential equations• Functional fault modelling• Faults and test generation hierarchy• High-level fault modelling• Fault modelling with DDs
Technical University Tallinn, ESTONIA 2
Fault Modeling in Digital Systems
• An instance of an incorrect operation of the system being tested is referred to as an error
• The causes of the observed errors may be design errors or physical faults (defects)
• Physical defects do not allow a direct mathematical treatment of testing and diagnosis
• The solution is to deal with logical fault models
System
Component
Defect
Error
Fault (model)
Defects, faults and errors
Technical University Tallinn, ESTONIA 3
Physical Defects as Fault Causes
Physical defects may occur:
• Manufacturing process: missing contacts , parasitic transistors, gate oxide shorts, oxide break-down, metal-to silicon shorts, missing or wrong components, broken or shorted tracks (board design), etc.
• Process fabrication marginalities: line width variation, etc.• Material and age defects: bulk defects (cracks, crystal
imperfections), surface impurities, dielectric breakdown, electromigration, etc.
• Packaging: contact degradation, seal leaks, etc.• Enviromental infuence: temperature related defects, high
humidity, vibration, electrical stress, crosstalk, radiation, etc.
Technical University Tallinn, ESTONIA 4
Soft and Hard Defects
Defects can be divided roughly into two basic groups :
• Soft defects – defects which cause speed fault– show up at high speed or produce some temperature – they need two or more test patterns for their activation and error
observation (require carefully constructed transitions for defect activation);
– require tests to be applied at speed. – examples: “high resistance” bridges, x-coupling, “tunneling break”
• Hard defects – defects observated at all frequencies – a test can be applied at slow speed– they need only one-pattern test set – example: “low resistance” bridge
Technical University Tallinn, ESTONIA 5
Defect Manifestation and Test Methods
Defects have to be measured and modeled into the faultsThey are manifested in different measurable manners:
• by changing a logical value on a circuit node (Boolean testing, or testing at the logical level)
• by increasing the steady state supply current (IDDQ testing)• by changing time specifications (At-speed testing)• by variation in one or a set of parameters such that their
specific distribution in a circuit makes it fall out of specifications
The test methods listed are not replacableThey all have to be used for achieving high quality of testing
Technical University Tallinn, ESTONIA 6
Why We Need Fault Models?
• Fault models are needed for – test generation, – test quality evaluation and – fault diagnosis
• To handle real physical defects is too difficult• The fault model should
– reflect accurately the behaviour of defects, and– be computationably efficient
• Usually combination of different fault models is used• Fault model free approaches (!)
Theorem 1: A set of test vectors that detects all single SAFs on all primary inputs of a fanout-free combinational logic circuit will detect all single SAFs in that circuit
Theorem 2: A set of test vectors that detects all single SAFs on all primary inputs and all fanout branches of a combinational logic circuit will detect all single SAFs in that circuit
The idea of N-detect single SAF test vectors was proposed to detect more defects not covered by the SAF model
Technical University Tallinn, ESTONIA 17
Fault Collapsing with SSBDDs
&
&
&
1
&
x1x2
x3x4
y
x11
x21
x12x31
x13
x22x32
x5
x6
x7
x8
x11y x21
x12 x31 x4
x13x22 x32
0
1
0
1
Each node in SSBDD represents a signal path:
Theorem 2: A set of test vectors that detects all single SAFs on all primary inputs and all fanout branches of a combinational logic circuit will detect all single SAFs in that circuit
Technical University Tallinn, ESTONIA 18
Fault Redundancy
1
&
&
&
1&
x1
x2
&x4
x3
y
0
)(
2
434211
x
y
xxxxxxy
Internal signal dependencies:
1
&
&1
11
1
1
Impossible pattern,OR XOR not testableFaults at x2 not testable
Optimized function: 341 xxxy
Redundant gates (bad design):
Technical University Tallinn, ESTONIA 19
Fault Redundancy
1
&
&
&
1
1
01
10
01
1
1
Hazard control circuitry:
Redundant AND-gateFault 0 is not testable
0
Error control circuitry:
Decoder
1
E 1 if decoder is fault-free Fault 0 is not testable
E
Technical University Tallinn, ESTONIA 20
Transistor Level Faults
Stuck-at-1Broken (change of the function)BridgingStuck-open
(change of the number of states)Stuck-on (change of the function)
The two branches of a and three branches of b could be interpreted by the driven gates to be any one of the 32 combinations
One corresponds to fault free situation, 31 correspond to faulty situations – 31 MLSFs
Method of implicit fault simulation: assign one branch with faulty value, and let other branches with unknown values
Constrained Multiple Line SAF Model
Technical University Tallinn, ESTONIA 24
Delay Faults
• Studies of the electrical properties of defects have shown that most of the random CMOS defects cause a timing (delay) effect rather than a other catastrophic defects (e.g. resistive bridges above a critical resistance cause delay)
• Delay fault means that a good CUT may perform correctly its function in a system, but it fails in designed timing specifications
• Delay faults could be caused by:
– subtle manufacturing process defects, – transistor threshold voltage shifts, – increased parasitic capacitance, – improper timing design, etc.
Technical University Tallinn, ESTONIA 25
Delay Fault Models
Delay faults are tested by test pattern pairs: - the first test pattern initializes the circuit, and - the second pattern sensitizes the fault
&
&
&00
&A
D
C
Bx1
x2
x3
10
11
01
11
110
001
y
Delay fault models: - Gate delay fault (delay fault is lumped at a single gate, quantitative model)- Transition fault (qualitative model, gross delay fault model, independent of the activated path)- Path delay fault (sum of the delays of gates along a given path)- Line delay fault (is propagated through the longest senzitizable path)- Segment delay fault (tradeoff between the transition and the path delay fault models)
Technical University Tallinn, ESTONIA 26
Delay Fault Models
&x1
x2
&x3
1y
11
11
11x4
x5
&x1
x2
&x3
1 y
11
11
x4
x5
Non-robustly tested TDF
Functionally sensitized TDFs
Different conditions of detecting transition delay faults (TDF):
Technical University Tallinn, ESTONIA 27
Delay Fault Models
x1
&x1
x2
yx2
yNot
detectedDetected
Robust test (R)
11
x1
&x1
x2
yx2
yNot
detectedDetected
Non-robust test (N)
00
x1
&x1
x2
yx2
yNot
detectedDetected
Functionally sensitized test
(F)
x1
&x1
x2y
x2
Not detected
Detected
Non-robust functionally
sensitized test (X)
00
x3y
x3
Technical University Tallinn, ESTONIA 28
Transistor Level Faults
Stuck-at-1Broken (change of the function)BridgingStuck-open
(change of the number of states)Stuck-on (change of the function)
Short (change of the function)
Stuck-off (change of the function)
Stuck-at-0
Logic level interpretations:
Technical University Tallinn, ESTONIA 29
Transistor Level Stuck-on Faults
x1 x2
Y
VDD
VSS
x1
x2
x1 x2 y yd
0 0 1 1
0 1 0 0
1 0 0 VY/IDDQ
1 1 0 0
NOR gate
)( NP
PDDY RR
RVV
Stuck-on
x1 x2
Y
VDD
VSS
x1
x2
Conducting path for “10”
RN
RP
Technical University Tallinn, ESTONIA 30
Transistor Level Stuck-off Faults
x1 x2
Y
VDD
VSS
x1
x2
x1 x2 y yd
0 0 1 1
0 1 0 0
1 0 0 Y’
1 1 0 0
NOR gate
Stuck-off (open)
x1 x2
Y
VDD
VSS
x2
No conducting path from VDD to VSS for “10”
x1
Test sequence is needed:
00,10
Technical University Tallinn, ESTONIA 31
Mapping Transistor Faults to Logic Level
Shortx1
x2
x3
x4
x5
y
)()(* dydyy d
))(( 53241 xxxxxyd 54321 xxxxxy
Generic function with defect:
Function:
Faulty function:
A transistor fault causes a change in a logic function not representable by SAF model
Defect variable: d =0 – defect d is missing
1 – defect d is present
Mapping the physical defect onto the logic level by solving the equation:
1*
d
y
Technical University Tallinn, ESTONIA 32
Mapping Transistor Faults to Logic Level
Shortx1
x2
x3
x4
x5
y )()(* dydyy d
))(( 53241 xxxxxyd 54321 xxxxxy
Test calculation by Boolean derivative:
1
))(()(*
5432154315421
5324154321
xxxxxxxxxxxxx
d
dxxxxxdxxxxx
d
y
Generic function with defect:
Function:
Faulty function:
Technical University Tallinn, ESTONIA 33
Functional Fault Model for Stuck-ON
Stuck-on
x1 x2
Y
VDD
VSS
x1
x2
NOR gate
Conducting path for “10”
)( NP
NDDY RR
RVV
RN
RP
dZxxxx
Zxxxxdxxdy
2121
212121 )()(*
1/* 21 ZxxdyW d
x1 x2 y yd
0 0 1 1
0 1 0 0
1 0 0 Z: VY/IDDQ
1 1 0 0
Condition of the fault potential detecting:
Technical University Tallinn, ESTONIA 34
Functional Fault Model for Stuck-Open
Stuck-off (open)
x1 x2
Y
VDD
VSS
x2
NOR gate
No conducting path from VDD to VSS for “10”
x1
Test sequence is needed: 00,10
x1 x2 y yd
0 0 1 1
0 1 0 0
1 0 0 Y’
1 1 0 0
)'(
)'()(*
12
212121
dyxx
yxxxxdxxdy
1'/* 21 yxxdyW d
t x1 x2 y1 0 0 1
2 1 0 1
Technical University Tallinn, ESTONIA 35
Functional Fault Model
Example:
Bridging fault between leads xk and xl
The condition means that
in order to detect the short between leads xk and xl on the lead xk we have to assign to xk the value 1 and to xl the value 0.
lkkd
lklkkd
kkk
xxd
xW
xdxxdxxddxxdx
*
)(*
1 lkd xxW
xk
xl
x*k
d
Wired-AND model
xk*= f(xk,xl,d)
Technical University Tallinn, ESTONIA 36
Functional Fault Model
Example:
x1
x2
x3
y&&
x1
x2 x3
y&&
&
321
321321
)'(
)()(*
xydxx
xyxxdxxxdy
Equivalent faulty circuit:
Bridging fault causes a feedback loop:
1'/* 321 yxxxdyW d
Sequential constraints:
A short between leads xk and xl changes the combinational circuit into sequential one
t x1 x2 x3 y
1 0 1 02 1 1 1 1
Technical University Tallinn, ESTONIA 37
Generalization: Functional Fault Model
d = 1, if the defect is present
yComponent F(x1,x2,…,xn)
Defect
Wd
Component with defect:
Logical constraints
Fault model: (dy,Wd), (dy,{Wk
d})
1*
d
yW d
Constraints:
Fault-free Faulty
dn dFFddxxxFy ),,...,,(** 21
Constraints calculation:
Technical University Tallinn, ESTONIA 38
Fault Table: Mapping Defects to Faults
Input patterns tji Fault di Erroneous function f di pi