Team M1 Enigma Machine Milestone 5 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Zavo Gabriel (M13) Mike Sokolsky (M14) Design Manager: Prateek Goenka.

Team M1Enigma Machine

Milestone 5

Adithya Attawar (M11)Shilpi Chakrabarti (M12)

Zavo Gabriel (M13)Mike Sokolsky (M14)

Design Manager: Prateek Goenka

Status Finished

- Behavioral Verilog and C simulation- Structural Verilog- Spice Delay Diagrams- Optimization of logic and modules

In Progress- Verification of Schematic

- Floorplan To do

- Layout- Testing- Simulation

Design Decisions Optimized logic to use minimum number of

transistors and decrease critical path Chose a TSPC flipflop to implement

registers and flip flops Changed RippleCarry adder to a

chained 3-bit Carry Lookahead

FSM

Schematic

Operation time varies, 17 cycles for a typical 3-rotor machine.– 1 cycle load– 1 cycle steckerboard swap– 6 cycles for 3 wheels -> 8 cycles for 4 wheels– 1 cycle for reflector– 6 cycles for 3 wheels -> 8 cycles for 4 wheels– 1 cycle output

FSM Operation

Choosing a flipflop for the registers... HL flipflop NAND flipflop N-pass flipflop TSPC flipflop (True Single Phase Clock) We chose the TSPC flipflop because it

was the fastest and reasonably smaller

Choosing a flipflop for the registers...

Type of Flip Flop

Delay (ps)

# of Trans

Notes

NAND ff 210 40 Not fast enough

N-Pass ff 53 (200+)

12 Any capacitance load on output (incl small inverters greatly) increases delay

TSPC ff 120 16 Fast and relatively small

HL ff 135 20 Too big; Used 20 big transistors: 2.7 um

REGISTER SCHEMATIC

DELAY TIME: 68 ps

PROPAGATION DELAY FOR REGISTER

Propagation Delay between A

and Y is: 111 picoseconds

Propagation Delay for Mux

Critical Path Through Adder Worst Case Scenario would be:

11001 + 00111 11001 00111 11110

11100 110..

10… 10..

Ripples through five times…

Propagation Delay for Adder

Delay Time between A

and Cout is: 930 picoseconds

PROPAGATION DELAY FOR OLD ADDER

DELAY: 930 ps

3-bit Carry Lookahead Adder

PROPAGATION DELAY FOR THE NEW ADDER

DELAY: 608 ps

Transistor Count Old Adders: (2 * 168) + 110 = 446 Optimized Adders: (2 * 230) + 110 = 570 Number of Increased Gates: 124 Delay time decreased by: 322 ps

Transistor Count (cont) Old Registers: 160 trans/reg * 4 reg = 640 Optimized Registers: 80 trans/reg * 4 reg =

320 gates Number of Saved Gates: 320 gates

Old Counters: 1250 gates (estimated) New Counters: 3680 gates

Transistor Count (cont) Original FSM: 600 gates Optimized FSM: 420 gates Number of Saved Gates: 180 gates

New Revised Total: FSM + Adders + Regs + Counters+Muxes+RAM+ROM = 420 + 570 + 320 + 3680 + 550 + 1150 + 4700 = 11390 transistors

Problems/Concerns

Bad rise and fall times in optimized adder Verify the schematic of entire design Implementation of new module (asymmetric

key encryption) ?

Any Questions?