Team LDPC, SoC Lab. Gradu Team LDPC, SoC Lab. Gradu ate Institute of CSIE, NT ate Institute of CSIE, NT U Implementing LDPC Decoding Implementing LDPC Decoding on Network-On-Chip on Network-On-Chip T. Theocharides, G. Link, N. Vijay krishnan, M. J. Irwin Penn State U niversity International Conference on VLSI D esign 2005
25
Embed
Team LDPC, SoC Lab. Graduate Institute of CSIE, NTU Implementing LDPC Decoding on Network-On-Chip T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin.
Team LDPC, SoC Lab. Graduate Institute of CSIE, NTU Intro Addressing problem are either limited in the types of LDPC codes, or constrained by hardware. Reconfigurable for different block sizes and code rates.
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
Implementing LDPC Implementing LDPC Decoding on Network-On-Decoding on Network-On-
ChipChipT. Theocharides, G. Link, N. Vijaykrishnan, M.
J. Irwin Penn State UniversityInternational Conference on VLSI Design 200
5
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
OutlineOutline• Intro• Message Passing• Iterative Decoding• Word length• Processing Elements• Virtual & Physical nodes• Network on Chip• Packets• Message Decoding Behavior• Bit node PE & Check node PE• Power Optimization• Conclusion & Comparison
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
IntroIntro• Addressing problem are either limited in
the types of LDPC codes, or constrained by hardware.
• Reconfigurable for different block sizes and code rates.
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
Message PassingMessage Passing• Start from bit function unit• Message passing iterations are performed
by the two computation units.
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
where– This function is implemented by using a ROM
based look-up table (LUT).
oldioldnoldold
newi
llrBllrBllrBllrBB
llr
___1_0
_
oldi
oldi
llr
llr
newieellrB
_
_
11ln_
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
Iterative DecodingIterative Decoding• Bit node operation
• stored_llr describes the previously stored logarithmic likelihood ration for the bit.
newininewi llrllrllrllrllrstoredllr _10_ _
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
Word lengthWord length• Word length is critical parameter.
– Performance– Power consumption
• A large data word results in a lower BER even in noisy channels.– Sign-magnitude representation– 16 bit word length
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU
Processing element (PE)Processing element (PE)• Bit and check nodes act as PEs.• PEs communicate via on-chip routers.• Each PE has a dedicated memory to store
configuration information.
Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU