TEAM “EPA” ELECTRONIC PIN ART Jonathan Persinger Jonathan Snyder Henry Au-Yeung Devon Dallmann Khushboo Verma Preliminary Design Review Spring 2006.

TEAM “EPA”ELECTRONIC PIN ART

Jonathan Persinger

Jonathan Snyder

Henry Au-Yeung

Devon Dallmann

Khushboo Verma

Preliminary Design ReviewPreliminary Design ReviewSpring 2006Spring 2006

Project Description

• An array of pins to display a variety of 3-D images such as:– Pictures

– Drawing

– Text/Braille

– Movies

– Games

– Integration with topography software (i.e. Google Earth)

Implementation• Solenoid actuation

– PWM Control– 256pin Resolution

• Software Algorithms and Programming– Image Processing– Embedded Interface communications

• Electronic Hardware– Solenoid controller/selection– Compact Flash interface– External Memory– Power regulation

Power Requirements

• Each Solenoid requires a maximum of 400mA to set. (~1-2W)

• Maximum Current will occur at column reset where 16 solenoids will be activated at once => 16 x 0.400A x 5V=32watts

• Several voltage rails will be needed to run the logic cores and solenoids.

System Overview

GoalsGoals

FallbackFallback• Braille/TextBraille/Text

• LEDsLEDs

• Total Grid ResetTotal Grid Reset

• Image Processing Image Processing in MATLABin MATLAB

• Hand ResetHand Reset

• 4x4 Matrix4x4 Matrix

GoalsGoals 16x16 pin matrix16x16 pin matrix 4 Levels of pin 4 Levels of pin

heightheight Static imagesStatic images Single pic in Single pic in

memorymemory One column reset One column reset

resolutionresolution Joystick drawingJoystick drawing

ExtraExtra Moving picturesMoving pictures Joystick gamingJoystick gaming LCD/picture LCD/picture

menumenu USB transceiverUSB transceiver DSP filtersDSP filters

Processor

TMS470R1A256•32-bit ARM7TDMI core (industrial applications)

•64 KB to 1MB flash memory

•12 KB static ram

•Clock speed up to 24 MHz

•14 High-resolution I/O channels

•I2C/SPI capable

CPLD Requirements

• Clock Standard bus interface (IIC, SPI, etc.)– SPI allows for full duplex

and any length instructions

• Counters and/or timers are critical for pin height resolutions. – CPLDs offers consistent

delays.

• Pin for pin compatibility with a CPLD with more Function blocks

• 4 function blocks

• 21 GPIOs

• One function block must have at least 16 Macrocells & 16 I/Os.

• +5v tolerance for compatibility with hardware logic and drivers.

CPLD Design

Decoder

Instruction Packet19

SPI State machine

uProc

Increment Instruction

4bit X8bit Inst# 3bit Z 2bit OPParity

Error Checking Timer Decoder

Logic Gates (ANDs ORs etc.)

Inst# | Row 16b | inc Clmn | RST Clmn | PWM | HW-Busy

ERROR W/ Inst#

4

Driver Circuit

• Control of 256 individual solenoids• Minimal part count per pin (cost control!)• Must have the ability to switch polarity on

Solenoids• EMI / ESD / EMF suppression & protection• Critical Routing, isolation of current carrying

grounds and signal grounds• Design in manual control and circuit isolation for

easier debugging.

Objectives:Objectives:

Proof of Concept:

Pin Selection

Proof of Concept:

Solenoid Physics

2

22

2L

SBINF mag

R

L

R

L

Solenoid Physics

• Pulse duration controls height

• Trade offs: larger N, less current needed, larger L, larger time constant

Image Processing• Process BMP, JPEG images• Use MATLAB for image processing

– Obtain color matrix– Algorithm to calculate height of the pin– Obtain x and y location for each pixel along with the height

• Store post-processed image to Compact flash• Compile the image to MSP470 assembly• Communicate between CPLD and Microprocessor via

Standard Peripheral/Bus Interface • Read information from compact flash

– Determine memory mapping to locate pictures on card

CPLD Verilog

• State machine to fix PWM & frequency

• Translation of post-processed image to one column at a time versus PWM Duration

• Miscellaneous Logic– Pin reset– Column select– Multiplexing/Decoding

Division of Labor

• Henry—Power management; PCB layout; mechanical design

• Khushboo—Image processing

• Jonathan S.—Solenoid control; System integration

• Devon—Solenoid design; programming

• Jon P—Programming; PCB layout

Gantt Chart

Parts/Costs

Item cost Total costPCB 1st and 2nd run $100/run $200.00Processor/Programmer $200.00Misc. Electronics $100.00Pin Rig $200.00Solenoids w/ pins 0.30/pin $300.00Power Supply Materials $100.00Spartan III FPGA $100.00Misc. Hardware $100.00Connectors $50.00TOTAL $1,350.00

Projected Costs

Risks• Processor/CPLD implementation

– Prior experience limited– IC Communication problems

• SPI integration complexity• Flash memory access (proprietary?)

• Cost/Availability– Manufactured solenoids: Cost? Turn around? Many parts are multiplied by

256 (runaway costs). Coil and pin manufacture as of now is difficult.

• Coils– High switched currents could cause re-triggering– Pin height tolerance (all or nothing could result)

• Mechanical– Tolerance of solenoid diameter and Rig spacing– Longevity of moving parts

Marketability

• Visually impaired via. Braille coding

• Novelty item—place on mantel with wave motion for relaxation

• USGS/Boy scout elevation profiles

• Automated tattooer

• Back massager

Questions & Comments

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