TDTS01 Computer Aided Design of Electronics 3rd Lab presentationTDTS01/labs/TDTS01_Lesson3... · 2014-02-19 · Computer Aided Design of Electronics 3rd Lab presentation Nima Aghaee

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TDTS01

Computer Aided Design of Electronics3rd Lab presentation

Nima Aghaee

Embedded Systems Laboratory (ESLAB)

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QUESTIONS ?3rd Lab presentation

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Previous Assignments• Project specification (1st assignment)

– Most general view of a design

• Compilable design and testbench (2nd assignment)– Formalization of the functionality

– Developing a testbench for the design• Also used in the following steps

– Simulation and validation

• Synthesizable design (3rd assignment)– Accepted by the synthesis tool

– Area vs. delay considerations and optimization

– Simulation (validation) of the design using testbench

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Manufacturing

Synthesizable design

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Further design steps

Manufacturing

Final product

Will all of the ICs work as expected?

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Manufacturing Defects• Example:

– Inconsistencies with expected layout outcome

• Opens

• Shorts

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• A method to filter out bad ICs is necessary

Assignments

• Project specification and tool set experience[deadline: 13-Feb]

• Compilable design and testbench[deadline: 25-Feb]

• Synthesizable design[deadline: 07-Mar]

• Manufacturing test[deadline: 14-Mar]

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Manufacturing Test

• Test pattern

– What to apply to the IC’s input pins?

– What to expect from the IC’s output pins?

• It takes time to

– Generate the patterns

– Apply the inputs

– Analyze the outputs

• Should be fast!

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Automatic Test Pattern Generation

• ATPG generator is a computer-aided tool – For test pattern generation

– Evaluation of test patterns• How much of the possible defects are tested for?

• How many potential defects are there?

• In what locations?

• With what behavior?

• Defect model should be defined– A usual one is Stuck-at model

• Each node in the circuit– Stuck-at 0 or stuck-at 1

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Design For Testability• A better design yields more effective testing

– ATPG works faster

– A better fault coverage is achieved

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• Example for stuck-at model

– C & D should make F = 1

• Fault activation/Controllability

– E should be 1 so that a 0 on F could be recognized on G

• Fault propagation/Observability

Controllability• Controllability

– Combinatorial circuit

• If achievable, happens very fast. Faster than a typical clock cycle

– Sequential circuit

• Many clock cycles might be required

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Scan Based Methods

• Structural method– Applicable in lower levels, when flip-flops are visible

• Convert the design flip-flops to a scan chain– Example:

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Automatic Scan Chain Insertion

• Computer-aided tool

– Inserts scan chain automatically

– Evaluation of the design enhanced for testability

• Use ATPG tool

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Example Design• Available at

TDTS01/exampleTestable

• Two new input ports– FFS: Fast Forward the States

• Improves the controllability

• Skip an state to arrive quickly at the next state

– STO: Select Test Output• Improves the observability

• Intermediate signals (partial sums) could selectively be connected to the output

• Small change in Testbench – Accommodate new ports

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Example Design Discussions

• Open the files in text editor …

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Coffee Break

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QUESTIONS ?3rd Lab presentation

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Design For Testability

Manual and ad hoc modifications

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Behavioral Design Test Improvements

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Less_States Design Test Improvements

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Improvements• Reduction in

– Uncontrolled faults– Unobservable faults– Untested faults

• Increase in– Test coverage– Fault coverage– Number of test patterns

• Other parameters (e.g., det_simulation, …)– Not crucial for this Lab– Might be tool dependent– Their explanation can be found in:

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/home/TDTS01/TessentDocumentation/atpg_gd.pdf

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Behavioral Design Area Changes

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Increase in Area

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Behavioral Design Delay Changes

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Increase in Delay

Less_States Design Area Changes

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Increase in Area

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Less_States Design Delay Changes

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Increase in Delay

Design For Testability

Automatic Scan Chain Insertion

ASCI

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Behavioral ACSI Test Improvements

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Less_States ACSI Test Improvements

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Improvements

• Removal of

– Uncontrolled faults

– Unobservable faults

– Untested faults

• Increase in

– Test coverage

– Fault coverage

– Number of test patterns

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Behavioral ASCI Area Changes

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Increase in Area

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Behavioral ASCI Delay Changes

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Increase in Delay

Less_States ASCI Area Changes

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Increase in Area

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Less_States Design Delay Changes

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Increase in Delay

Assignment 4 – Manufacturing Test (1)• Obtain the testability data for your current design

– Analyze the design from testability perspective– Save the original design and testability data separately

• Apply changes to the original design• Compile and simulate

– Compiles with ModelSim w/o errors/warnings– Testbench may need modifications, do it! (save the old test bench separately)

• Simulation and validation must complete successfully

• Synthesis– LeonadroSpectrum synthesizes it

• Gate-level netlist is generated successfully

– Save area/delay reports• How they have changed?

• Obtain the testability data for the improved design– Explain the improvement, how it is achieved?

• The amount of improvement is not crucial• Explaining and arguing is crucial

– Save the design and testability data separately

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Assignment 4 – Manufacturing Test (2)• Perform automatic scan chain insertion

– On the original design– On the design manually modified for testability

• Obtain the area and delay reports– LeonadroSpectrum area/delay reports

• Save them separately• How they have changed?

• Obtain the testability data– Fastscan testability data

• Save them separately• How they have changed?

• Explain the improvements, and the trade offs– Compare the scan chained versions

• Design that you modified manually for testability • Original design

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Assignment 4 - Demo

• Manufacturing Test [deadline: 14-Mar]• Explain, briefly, how testability has improved

– The original testability and why it is not good– What you have done to improve it– The improved results

• Simulate the manually improved design with the testbench– Correct functional output– Correct timing behavior

• Is there a visible difference between the original and the improved design in wave window?

• How area and delay are affected?• Compare the scan chained versions (testability/delay/area)

– Design that you modified manually for testability – Original design

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Assignment 4 - Report• Manufacturing Test [deadline: 14-Mar]• Should provide proofs that you have successfully completed all parts of

the assignment• Explain, briefly, how testability has improved

– The original testability and why it is not good– What you have done to improve it– The improved results

• How area and delay are affected?• Include shots of wave or transcript window with brief explanation

– Is there a visible difference between the original and the improved design in wave window?

– Correct functional and timing behavior is expected

• Compare the scan chained versions (testability/delay/area)– Design that you modified manually for testability – Original design

• Email the codes and other files (e.g. do file and file that includes validation data)

• Include the explicitly requested material in the report

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Please Fill and Return the Feedback Forms

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QUESTIONS ?3rd Lab presentation

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REVIEW DIFFERENCES BETWEEN BEHAVIORAL AND LESS_STATES

Is any time left?

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