TDC130: High performance Time to Digital Converter in 130 nm Christian MESTER 2008-03-27.

TDC130: High performance Time to Digital Converter in 130 nmChristian MESTER2008-03-27

2

Physics Department

Pico-Second Timing Workshop Chicago, 27-28 March 2008

Christian [email protected]

Index

Introduction:

• What is a TDC and its use

• Application example

• HPTDC implementation

New TDC130

• Expected resolution

• Current state

• Architecture

• Focus on DLL

• Ideas for further improvement of resolution

3

Physics Department



What is a TDC and its use

TDCs are used to measure time (intervals) with high precision

• Start – stop measurement Measurement of time interval between two events:

start signal – stop signal Used to measure relatively short time intervals with high precision Like a stop watch used to measure sport competitions

• Time tagging Measure time of occurrence of events with a given time reference

Time reference (Clock) Events to be measured (Hit)

Used to measure relative occurrence of many events on a defined time scale Like a normal watch

Start

Stop

Time scale (clock)

Hits

4

Physics Department



What is a TDC and its use

Special needs for high energy physics

• Many thousands of channels needed want to use the same time base for many channels

• Rate of measurements can be very high

• Very high resolution

• Triggered mode must be integrated with TDC function: store measurements during a given interval extract only those related to an interesting event, signalled by a trigger

5

Physics Department



ALICE Time of Flight (TOF)

• ≈25 ps resolution

• 160 000 channels

time of flight

≈ speed of light

particle

6

Physics Department



Current Implementation (HPTDC)

• DLL, hit registers, RC delay and PLL implemented as full custom

• 0.25 µm CMOS technology

• 6.5 x 6.5 mm²

• ≈ 1 million transistors

• 225 ball grid array package

7

Physics Department



Index

Introduction:

• What is a TDC and its use

• Application example

• HPTDC implementation

New TDC130

• Expected resolution

• Current state

• Architecture

• Focus on DLL

• Ideas for further improvement of resolution

8

Physics Department



Current HPTDC

• ≈ 100 ps bin size on 32 channels or≈ 25 ps bin size on 8 channels

• 780 ps bin size in low resolution mode

• 102 µs dynamic range (15 bit)

• Max. hit rate on channels depend on other channels’ activity

• Double pulse resolution: 5 ns to 10 ns (depending on mode)

New TDC130 vs. current HPTDC

New TDC130

• ≈ 25 ps bin size on 32 channels

• ≈ 800 ps bin size in low resolution mode

• ≈ 840 µs dynamic range (20 bit)(possibly more)

• Higher hit rates, channels are independent

• Minimum double pulse resolution ≤ 2 ns

• Lower power consumption

• Lower cost

9

Physics Department



Timing part

To be submitted in May 2008

• PLL

• DLL

• Hit registers

• 24.4 ps bin size in “32” channels

• If time allows:additional interpolation function

TDC130: Current state

10

Physics Department



Core architecture of TDC130

Clock(40 MHz,

or 80 MHz)

Hit[31:0]LVDS

Readout

PLL 1.28 GHz Phase detector, Charge pump, Filter

32

32

× 32

Hit register

32 delay elements+dummies

11

Physics Department



DLL

Loop filter

Phase detector

Clock input

4 dummies 1 dummy32 DLL elements

Charge Pump

Timing part

• Phase detector: bang-bang type

• Loop filter: Capacitor to ground

• Control voltage for dummies is separated using mirrors not to inject noise on the main elements’ control voltage

• Not shown: Differential to single-ended conversion between delay line and phase detector Differential to single-ended conversion before hit registers and buffers

Note that the load seen by each delay element has to be the same.

12

Physics Department



Differential delay elements• With local fine adjustment to compensate

mismatch effects

DLL: Delay cell

Low Vt

Control voltage

D

RFP

Q

Bandgap

Select<2:0>

Low Vt

Low VtLow Vt

This works like an inductor (within a limited frequency range)

Local fine adjustment to compensate for mismatch

13

Physics Department



Monte Carlo Simulation: INL/DNL (TDC130)

0 5 10 15 20 25 30 35-0.06

-0.05

-0.04

-0.03

-0.02

-0.01

0

INL(

dela

y)/L

SB

Delay element nr.

Monte carlo: 25 runs, process variation only, 25 C, 1.5 V

0 5 10 15 20 25 30 35-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

DN

L(de

lay)

/LS

B

Delay element nr.

Monte carlo: 25 runs, process variation only, 25 C, 1.5 V

25 runs, process variations only

VCDL, differential-to-single-ended converters and buffers

14

Physics Department



Monte Carlo Simulation: INL/DNL (TDC130)

0 5 10 15 20 25 30 35-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

DN

L(de

lay)

/LS

B

Delay element nr.

Monte carlo: 25 runs, mismatch variation only, 25 C, 1.5 V

0 5 10 15 20 25 30 35-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

INL(

dela

y)/L

SB

Delay element nr.

Monte carlo: 25 runs, mismatch variation only, 25 C, 1.5 V

25 runs, mismatch variations only

VCDL, differential-to-single-ended converters and buffers

15

Physics Department



Measurement of HPTDC: INL correction

INL in 25 ps mode

-6

-4

-2

0

2

4

6

0

2.5 5

7.5 10

12

.5 15

17

.5 20

22

.5 25

time/ns

INL

/bin

Without INL compensationAfter INL compensation

Measurements from ALICE-TOF

Effective RMS resolution:

• 40 ps without INL correction

• 17 ps with look-up table INL correction (as a fixed 40 MHz pattern has been observed)

16

Physics Department



How to improve the resolution?

HPTDC’s very high resolution mode:

• Interpolation using R-C delay elements and 4 normal channels per very high resolution channel ( only 8 instead of 32 channels available in very high resolution mode)

TDC130:

• Interpolation — without reducing the number of channels?

• Ideas: R-C networks: attenuation, low pass: slew rate deteriorates Transmission lines: potentially long, less attenuation Delay elements (like in the DLL)

– Use a second DLL with slightly less (e.g. 26) delay elements than the main DLL– Let the clock signal propagate in both DLLs– Distribute the second DLL’s control voltage to delay elements in the channels

• Interpolation factor 4 ≈6 ps bin size

17

Physics Department



Final chip

• General architecture (channel organization, 1 buffer per channel) fixed

• Will support triggered mode

• Readout: to be discussed

Future of the development

• “Client” expectations

• “Client” involvement

• “Availability” of manpower

• “Maintain” expertise

TDC130: Outlook

TDC130: High performance Time to Digital Converter in 130 nm Christian MESTER 2008-03-27.

Documents

timing workshop chicago

dll timing

nm christian mester

mismatch slide

ps resolution

current state slide

trigger slide

time base