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Circuit description for the PFC AC-DC converter Please refer to the NCP1654 datasheet and AND8324-D application note from ON Semiconductor. A generic
NCP1654 application schematic (Figure 4) and parameters of the PFC controller (Table 2) and the inductor (Table 3)
follow.
Figure 4. Generic NCP1654 application schematic
Table 2. PFC controller parameters
Parameter Unit Value Description
fac Hz 60 Ac line frequency VacLL V 90 Ac line rms lowest level (generally 85V or 90V in wide mains applications) VacHL V 265 Ac line rms highest level (generally 265V in wide or European mains
applications) Vac,on V 75 Ac line rms voltage to start up (generally 75Vac in wide mains applications)
Vout V 385 Wished regulation level for the output voltage (generally 390V or 400V in wide mains applications)
VoutLL V 385 Minimum output voltage you can accept in normal operation – use VoutLL = Vout as a default value if you don't know
eff % 95 Expected efficiency at low line, full load Pout W 216 Maximum output power
ΔIpk-pk % 30 Targeted peak to peak ripple of the coil current at low line and full load RdsON Ω 0.29 MOSFET on-time resistance @ 25°C Thold-up ms 20 Hold-up time – put 0 if no hold-up time is specified or if you don't know (Vout)min V 310 Minimum output voltage you can accept at the end of the hold-up time %DVpk-pk % 3 Peak to peak low frequency ripple that is acceptable across the bulk
capacitor as a percentage of the regulation output voltage ("Vout") Bulk capacitor and coil specifications Cbulk cal. µF 166 Minimum Cbulk capacitance meeting the low frequency ripple and hold-up
time constraints* Cbulk selected µF 240 Choose higher standard value ESR of Cbulk mΩ 150 The ESR of Cbulk Lcalc µH 397 Proposed coil inductance L selected µH 480 Your inductance choice (Icoil)max A 4.02 Max peak coil current resulting from your inductance choice (Icoil)rms A 2.53 Maximum rms coil current Conduction losses Input bridge W 4.5 Assuming the forward voltage of each diode is 1V MOSFET W 2.9 Assuming RdsON doubles at the highest junction temperature of your
application Diode W 0.6 Assuming RdsON doubles at the highest junction temperature of your
application and assuming the diode forward voltage is 1V Feedback arrangement RfbL kΩ 23.2 Choose a standard value RfbU1 + RfbU2 kΩ 3,550 (RfbU1 + RfbU2) calculated based on RfbL and Vout Cfb pF 100
Input voltage sensing - choose high accuracy resistors for RboU1, RboU2 and RboL RboL kΩ 24.7 Choose a standard value < 140kΩ RboU1 + RboU2 kΩ 2,007 (RboU1 + RboU2) calculated based on RboL and Vac,on Cbo cal. µF 1.69 Cbo calculated based on RboL and line frequency Cbo selected µF 2.20 Choose the closest standard value Current sense network Rsense cal. Ω 0.17 Value that makes the Rsense dissipation = (0.5% * Pout) Rsense selected Ω 0.06 Your " Rsense " choice PRsense Ω 0.4 Losses resulting from your Rsense choice Rcs cal. kΩ 1.3 Value resulting from your Rsense choice Rcs selected kΩ 3.3 Choose higher standard value Rm kΩ 110 Value resulting from your Rsense choice Cm nF 2.2 Value resulting from your Rm choice Compensation arrangement Fc Hz 20 The desired crossover frequency at high line Cz cal. µF 2.0 The calculated Cz based on (G0)dB and fc Cz µF 2.2 Choose closest standard value Rz cal. (kΩ 25 The calculated Rz based on fz1 Rz kΩ 11 Choose closest standard value Cp cal. nF 1.5 The calculated Cp based on fp1
* Do not forget to check that the ESR is low enough to avoid any over-heating of the bulk capacitor. You can use 1.8A as a starting value for the bulk capacitor rms current (rough estimation based on the figures you entered). Double check on the bench that the bulk capacitor heating is not excessive.
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Table 3. PFC inductor parameters
Item Value Comments
Inductance 480µH ~25% ΔIpk_pk Core type CC30/19 Height < 20mm Core material A-core JPP-95 Similar to 3C95 Wire 40/38 Litz wire ~0.11Ω DCR Winding turns 38 < 10pF winding capacitance Air gap ~0.42mm Not considered fringing effect
Circuit description for the LLC DC-DC converter Figure 5 illustrates the topology of the LLC DC-DC converter portion of the evaluation board, which is based on the NCP1397
and NCP4304 controllers. The series capacitor forms the series-parallel resonant tank with leakage and magnetic inductances
in the primary side of the transformer. From this configuration, the resonant tank and the load on the secondary side act as a
voltage divider. By changing the frequency of input voltage, the impedance of resonant tank will change; this impedance will
divide the input voltage with load. The primary-side switches, Q1 and Q2, are the GaN FETs. Transistors SD1 and SD2 on the
secondary side are synchronous rectifiers to improve the performance and efficiency. As can be seen in Figure 5, there is no
need for special gate drivers for the GaN FETs. For further reading: information and discussion on the fundamental circuit
schematics and the characteristics of LLC DC-DC converters [1], [2], [3].
Figure 5. Circuit topology for LLC DC-DC converter using Si MOSFETs for line rectification
Although the LLC is a resonant topology, characterized by soft switching, hard switching does nevertheless occur during start-up.
During this phase, the large reverse recovery charge (Qrr) of typical Si MOSFETs causes problematic overshoot, ringing, and loss.
Transphorm’s TPH3202PS GaN power devices show a low on-resistance of 0.29Ω (typical) and are capable of reverse
conduction during dead time, with a low Qrr of 29nC, more than 20 times lower than state-of-the-art Si counterpart as seen in
Figure 6. These features can remarkably improve the performance and efficiency of hard-switch circuits and are also important
for hard starting in resonant circuits such as the LLC topology.
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Figure 6. Reverse recovery charge test result for a Si MOSFET and a GaN FET: Similar on-resistance and a 20x reduction of Qrr for GaN
Startup sequence 1. Connect a load – the load should be resistive and maximum of 240W at 12VDC
2. Connect an AC power source and set to the desired voltage, higher than 90V
3. Place a cooling fan facing the GaN FETs’ heat sinks of the PFC and LLC, providing a minimum of 30 CFM air flow
4. Turn on the cooling fan if output power is higher than 200W
Probing
To minimize additional inductance during measurement, the tip and the ground of the probe should be directly attached to the
sensing points to minimize the sensing loop, while the typical long ground lead should be avoided since it will form a sensing
loop and could pick up the noise. An example of low inductance probing is shown in Figure 7. The differential probes are not
recommended for the GaN signal measurement.
Figure 7. Low inductance probing of fast, high-voltage signals
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Power-up waveforms
The power-up waveforms were measured in different conditions. Figure 8 shows the no-load LLC power-up at 115V input. As
shown in Figure 8(a), the DC bus voltage increases to 360V, the LLC converter starts to operate, and the output voltage (CH4)
gradually increases to 12V. In Figure 8(b), when the LLC half-bridge starts switching, the initial switching frequency is 471kHz in
the beginning and the peak transformer current is around 7.5A. Figure 9 shows the full-load LLC power-up. In the current
waveforms, the peak current appeared after 3-4 line cycles in both no-load and full-load conditions. This is because, when the
output voltage increases to around 10V, the SR driver is engaged and the MOSFET will run in synchronized rectified mode and
the voltage drop on body diode will be eliminated.
(a)
(b)
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(c)
Figure 8. Power-up at no-load condition at 115V input (a) LLC power-up waveforms: CH1 – VDS voltage of LLC, CH2 – input current,
CH3 – LLC primary side transformer, CH4 – output voltage (b) LLC start-up frequency – fsw=471.6kHz, IL_pk=7.5A
(c) Burst mode at startup with no load
(a)
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(b)
Figure 9. Power-up at 240W condition at 115V input (a) LLC power-up waveforms: CH1 – VDS voltage of LLC, CH2 – input current,
CH3 – LLC primary side transformer current, CH4 – output voltage (b) LLC startup frequency – fsw=409.8kHz, IL_pk=8.65A
Performance
Efficiency and power factor have been measured at low line (115VAC) and high line (230VAC) input for a range of loads on the
12VDC output using the Yokogawa WT1800 precision power analyzer. The results are shown in Figures 10-12 for the complete
power supply and for the individual LLC circuits. The mid-load efficiency is more than 94% at low line and about 95.4% at high
line, which is noticeably better than commercial boards with Si switches.
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Figure 10. Efficiency for the power supply at 115V and 230V input
Figure 11. Power factor vs. output power at 115V and 230V input
0
5
10
15
20
25
91
91.5
92
92.5
93
93.5
94
94.5
95
95.5
96
25 75 125 175 225 275
PowerLo
ss(W
)
Efficiency(%
)
OutputPower(W)
Eff(115V) Eff(230V) Ploss(115V) Ploss(W)
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
0 25 50 75 100 125 150 175 200 225
PF_115V PF_230V
Ploss(230V)
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Figure 12. Efficiency results for the LLC DC-DC converter circuit at 390VDC input to 12VDC output
Conducted emissions have also been measured for the TDAIO250P200 board, using an LIN-115A LISN by Com-Power, and the
results compared to EN55022B limits (Figure 13.)
Figure 13. Conducted emissions at 115VAC and 240W load
In this design, standby power consumption is not optimized to show the superior performance over Si-based devices. Current
Controlled Frequency Foldback (CCFF) and burst mode methods can be applied for very low power loss requirement at zero and
light load using corresponding controllers and circuits.
0
2
4
6
8
10
12
94
95
95
96
96
97
97
98
0 50 100 150 200 250
Efficiency(%) Loss(W)
0
10
20
30
40
50
60
70
100 1000 10000
All-in-one EN55022BQuasiPk
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The temperature rising was measured with natural air convection at 23°C ambient temperature. At 240W load and 115V input,
the transformer temperature went to 105°C (a) and the TPH3202PS (Q1) went to 98.2°C (b) in one hour (Figure 14.) It is
suggested to add a moderate air flow when the load is over 200W.
(a)
(b)
Figure 14. Temperature measurement at full load, 115V input TA=23°C
Warnings There is no specific current or voltage protection on this board. Users should carefully follow the test procedure and operation
limits. The TDAIO250P200 board is for evaluation purposes only.
Further reading
[1] B. Lu, W. Liu, Y. Liang, F. Lee and J. VanWyk, "Optimal design methodology for LLC resonant converter," Proc. IEEE APEC '06,
pp. 19-23, 2006.
[2] R. Steigerwald, "A comparison of half-bridge resonant converter topologies," IEEE Transactions on Power Electronics, vol. 3,
no. 2, pp. 174-182, 1988.
[3] B. Yang, F. Lee, A. Zhang and H. Guisong, "LLC resonant converter for front end DC/DC conversion," Proc. IEEE APEC '02, pp.