© NUS 2005 TD5102 Embedded System in Silicon FPGA Architecture and EDA Dr. Ha Yajun (E1-08-17, e [email protected] ) http://courses.nus.edu.sg/course/eleh y/TD5102/
Feb 10, 2016
© NUS 2005
TD5102 Embedded System in Silicon
FPGA Architecture and EDA
Dr. Ha Yajun(E1-08-17, [email protected])
http://courses.nus.edu.sg/course/elehy/TD5102/
© NUS 2005 Yajun Ha / ECE, NUS
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Embedded Systems
An embedded system is nearly any computing system (other than a general-purpose computer) with the following characteristics
Single-functionedTypically, is designed to perform predefined function
Tightly constrainedTuned for low cost Single-to-fewer components based Performs functions fast enoughConsumes minimum power
Reactive and real-timeMust continually monitor the desired environment and
react to changes Hardware and software co-existence
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Embedded Systems
Examples: Communication devices
Wired and wireless routers and switches Automotive applications
Braking systems, traction control, airbag release systems, and cruise-control applications
Aerospace applicationsFlight-control systems, engine controllers, auto-pilots
and passenger in-flight entertainment systems Defense systems
Radar systems, fighter aircraft flight-control systems, radio systems, and missile guidance systems
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Simplified and General Embedded System Design Methodology
SW/HW Interface
Algorithm Functional Modeling
Problem Partitioning
Software Func. Model
SW/HWInterface
Hardware Func. Model
Architectural synthesisSoftware Development
Structural RTL HDLApplication Source Code
ProcessorsApplication Specific
Hardware(ASIC/FPGA)
Platforms
Algorithms
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Three Kinds of Embedded SystemImplementation Platform Choices
RfD$
I$Sw
ID
+|-|*|>|+
- *
>
ConfigurationSw
Processor Reconfigurable FPGA Hardwired ASIC
ProgrammableSequentialInstruction flow (cycle) Transfer bottleneck
ConfigurableParallel wired algorithm“Program” flow (occasionally)Distributed data
+-
* >
No wiringNo configurationOverhead
+- * >
Power: 100 10 1
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Why Use Reconfigurable Hardware?
Processor Processor-ASIC
Processor-FPGA
Performance Low High MediumFlexibility High Low HighPower High Low Medium
• Combine flexibility with performance.• Shorter time-to-market and longer time-in-market.• #FPGA gates/USD: 2004 1 M/10$.• FPGA capacity: now 2004 50Mgates => FPGAs get used as functional part of a design (<-> prototyping)
Why FPGAs ?
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Embedded Software Tools
CPU
Logic Design Tools
I/O
FPGA
Memory
Logic Design Tools
FPGA + Memory + IP +High Speed IO
(4K & Virtex)
Embedded Software Tools
CPU
Inte
grat
ion
of F
unct
ions
Time
Logic Design Tools
Embedded Software Tools
Logic + Memory + IP +
Processors + RocketIO
(Virtex-II Pro)
Programmable Systemsusher in a new era of system
design integration possibilities
Integration in System Design
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FPGA Based Reconfigurable Platform
Reconfigurable Platforms Architectures EDA for Reconfigurable Architectures Applications of Reconfigurable Platforms Lab Sessions on FPGA Board
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Simplified FPGA Architecture
Functional Block
I/O BlockRouting Network
All the three components can be re-programmed with configurations to implement application-specific digital circuits.
For example, each functional block can be programmed to implement a small amount of digital logic of a design; the routing network can be programmed to implement the design specific interconnection pattern; I/O blocks can be programmed to implement the input and output ports according to design requirements.
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FPGA Reconfiguration
All the programming information for the three programmable RA components is stored in a configuration file. The configuration file for a RA is often called a bitstream compared to a binary executable for a processor. Once a bitstream for a digital logic design is downloaded to a RA, the RA is programmed to implement the design. By providing different bitstreams, a single RA can be re-programmed to implement different designs at different times.
BitstreamFile 1
BitstreamFile 2
Time 1
Time 2
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FPGA Functional Block
LE
LE
LE
LocalInter-
connect
….
.
Functional B
lockInputs
Functional B
lockO
utputs
Functional Block Internals
Our target RAs use the Look-Up Table (LUT) type of functional block. Such a functional block is normally made of one or several logic elements (LE). They differentiate from each other mainly in terms of the input size of a LE and the number of LEs in a functional block. State-of-the-art RAs normally use 4-input LEs.
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Logic Element
LE Internals
The LE consists of a 16 SRAM cell Look-Up Table (LUT), and a flip flop (FF). The 16 SRAM cells LUT stores the truth table of any 4-input logic function, thus it can implement any 4-input logic function. The FF implements the storage element in a sequential circuit.
© NUS 2005 Yajun Ha / ECE, NUS
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LUT Content
F = A*B+C*D
A B C D F0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1
ABCD
F
The 16 SRAM cell LUT stores the output column of the truth table of the F function. The 4 inputs A, B, C and D will determine which bit the F value is for the current values of A, B, C and D.
© NUS 2005 Yajun Ha / ECE, NUS
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Additional Computational Resources
Memory blocks
Microprocessor blocks
• Besides the LEs present in previous slide, some functional blocks in different target RAs have architecture specific features to improve the performance when implementing arithmetic functions.
• These architecture specific features include carry logic, embedded memory blocks, multiplier and other hard cores.
• Hard cores generally implement functions efficiently compared to FPGA functional blocks.
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Routing Architecture
A logic block input or output pin can connect to some or all of the wiring segments in the channel adjacent to it via a connection block of programmable switches. At every intersection of a horizontal channel and a vertical channel, there is a switch block. It is a set of programmable switches that allow some of the wire segments incident to the switch block to be connected to others. By turning on the appropriate switches, short wire segments can be connected together to form longer connections.
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Routing Wires
• Some target RAs contain routing architectures that include different lengths of wires.
• The length of a wire is the number of functional blocks it spans.
• Left figures show wires of length 1, 2 and 4.
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XC4000 Routing Architecture Example
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Commercial FPGA Architecture Comparison
© NUS 2005 Yajun Ha / ECE, NUS
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PowerPC405 Core
Dedicated Hard IPFlexible Soft IP
RocketIO
PowerPC-based Embedded Design
Full system customization to meet
performance, functionality, and cost goals
DCR Bus
UART GPIO On-ChipPeripheral
Hi-SpeedPeripheral
GB E-Net
e.g.Memory
Controller
ArbiterOn-Chip Peripheral Bus
OPB
Arb
iter
Processor Local Bus
Instruction Data
PLB
DSOCMBRAM
ISOCMBRAM
Off-ChipMemory
ZBT SRAMDDR SDRAM
SDRAM
BusBridge
IBM CoreConnect™on-chip bus standardPLB, OPB, and DCR
© NUS 2005 Yajun Ha / ECE, NUS
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MicroBlaze-based Embedded Design
Flexible Soft IPMicroBlaze32-Bit RISC Core
UART 10/100E-Net
On-ChipPeripheral
Off-ChipMemory
FLASH/SRAM
LocalLink™FIFO Channels
0,1…….32
CustomFunctions
CustomFunctions
BRAM Local Memory
BusD-CacheBRAM
I-CacheBRAM
ConfigurableSizes
Arb
iter
Processor Local Bus
Instruction Data
PLBBus
Bridge
PowerPC405 Core
Dedicated Hard IP
Arb
iter
Processor Local Bus
Instruction Data
PLBBus
BridgeBus
Bridge
PowerPC405 Core
Dedicated Hard IP
PowerPC405 Core
Dedicated Hard IP
PowerPC405 Core
Dedicated Hard IPPossible inVirtex-II Pro
Hi-SpeedPeripheral
GB E-Net
e.g.Memory
ControllerHi-Speed
PeripheralHi-Speed
PeripheralGB
E-NetGB
E-Net
e.g.Memory
Controller
e.g.Memory
Controller
Arb
iter OPB
On-Chip Peripheral Bus
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Based Reconfigurable Platform
Reconfigurable Platforms ArchitecturesEDA for Reconfigurable Architectures Applications of Reconfigurable Platforms Lab Sessions on FPGA Board
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FPGA Design Flow
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Time Profile for Design Flow Steps
Logic Optimization and routing steps normally consume the major part of the design flow time.
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FPGA Technology Mapping
Technology step restructures the primitive logic gates, generated from the logic optimization step, into sets of 4-input functional blocks.
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FPGA Placement and Routing
The placement step finds physical locations for functional blocks, while the routing step finds physical routes for logic connections.
© NUS 2005 Yajun Ha / ECE, NUS
Embedded Design in an FPGA
Embedded design in an FPGA consists of the following:
FPGA hardware design
C drivers for hardware
Software design
RTOS versus Main + ISR
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Embedded DevelopmentTool Flow Overview
Compiler/Linker
(Simulator)
C Code
Debugger
Standard Embedded SWDevelopment Flow
CPU code in on-chip memory
?CPU code in
off-chip memory
Download to Board & FPGA
Object Code
Standard FPGA HWDevelopment Flow
Synthesizer
Place & Route
Simulator
VHDL/Verilog
?
Download to FPGA
© NUS 2005 Yajun Ha / ECE, NUS
Embedded Development KitThe Embedded Development Kit (EDK) consists of the following:
Xilinx Platform Studio – XPS Base System Builder – BSB Create and Import Peripheral Wizard Hardware generation tool – PlatGen Library generation tool – LibGen Simulation generation tool – SimGen GNU software development tools System verification tool – XMD Virtual Platform generation tool - VPgen Software Development Kit (Eclipse) Processor IP Drivers for IP Documentation
Use the GUI or the shell command tool to run EDKDetailed data sheet of Xilinx FPGA devices and user manuals of ISE
and EDK tools are available online at http://www.xilinx.com/support/library.htm
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Based Reconfigurable Platform
Reconfigurable Platforms Architectures EDA for Reconfigurable ArchitecturesApplications of Reconfigurable Platforms Lab Sessions on FPGA Board
© NUS 2005 Yajun Ha / ECE, NUS
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Why Networked Hardware?
But one day Cindy cried and told me that our talk had been disclosed. I laughed and said “Baby, never mind, I will change the encryption instantly through the network!!!”
Cindy Crawford asked me to encrypt our mobile phone talk!!! It is not an easy job!!!So I resort to hardware.
--- Quoted from Cindy’s Boy Friend!!!
© NUS 2005 Yajun Ha / ECE, NUS
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Future Networked Applications Need Client Platforms with Flexible Hardware Acceleration
Future networked applications can require high computing power up to 1000 Giga Ops [Nakatsuka, ISSCC’99], thus hardware acceleration is generally needed, and networked applications will contain both software and hardware components.
Different networked applications may use different industry standards to support new services, and require the client platforms to be flexible.
Networked applications usually work with a server-client model, and require the client platforms to be connected to the network.
© NUS 2005 Yajun Ha / ECE, NUS
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Target Client Platform: Networked Reconfigurable Platform
Dowloading
SW PartHW Part
Application Description
ISP1 ISP2 ISPN
Distr.memory
arch.
ASIC ReconfigurableHardware
static interconnect network
Both ISP and reconfigurable HW can be programmed to adapt changing standards. Reconfigurable HW can provide a better than ISP energy efficiency of high processing power vs. power consumption. Configurations for both ISP and reconfigurable HW can be network downloaded.
flexible!
High computing power!
networked!
© NUS 2005 Yajun Ha / ECE, NUS
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Commercial FPGA Platform
Dowloading
SW PartHW Part
Application Description
ISP1 ISP2 ISPN
Distr.memory
arch.
ASIC ReconfigurableHardware
static interconnect network
Both ISP and reconfigurable HW can be programmed to adapt changing standards. Reconfigurable HW can provide a better than ISP energy efficiency of high processing power vs. power consumption. Configurations for both ISP and reconfigurable HW can be network downloaded.
flexible!
High computing power!
networked!
ReConfig.
logic
Up to 16 serial transceivers
PowerPCs
Courtesy of Xilinx (Virtex II Pro)
© NUS 2005 Yajun Ha / ECE, NUS
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Networked SW/HW Reconfiguration of Networked Information Appliance
Web Page
User Downloads
App
User Selects App
Advertise App on Web Page
Dowloading
Java FileHW File
Description ISP1 ISP2 ISPN
Distr.memory
arch.
ASIC Re-configurableHardware
static interconnect network
© NUS 2005 Yajun Ha / ECE, NUS
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Web MPEG Video Player
Client Web Page
Server Side Client Side
Java MPEG Player+
IDCT bitstream
CPU+
FPGA
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Networked Reconfiguration is Better
Service Provider
Service Client
Service Request
network
Service I Reconfig
Info
Service I Data
Streams
Service II Data
Streams…...
Service II Reconfig
Info
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Based Reconfigurable Platform
Reconfigurable Platforms Architectures EDA for Reconfigurable Architectures Applications of Reconfigurable PlatformsLab Sessions on FPGA Board
Lab Session 1: Reconfigurable fabric based hardware design Lab Session 2: Processor+Reconfig Fabric based system design
© NUS 2005 Yajun Ha / ECE, NUS
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MEMEC Virtex-4 LC FPGA Board
More FPGA board related documentations have been put online at http://courses.nus.edu.sg/course/elehy/EE4218/projects.htm
FPGA
Push Buttons
LEDs
DIP Switches
Serial Port
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Board Demo
When PUSH2 (SW5) is not held down, the 7-segment display (DD1) does a binary-to-hex conversion of the binary number represented by the 4-bit DIP switch (SW3).
When PUSH2 (SW5) is held down, the 7-segment display (DD1) counts from 0-9.
LED1, LED2, LED3, and LED4 count in binary from 0-9 (matching what is on DD1 when PUSH2 is pressed).
Pushing PUSH1 resets the counter.
SW5 PUSH2
7-segment Display
© NUS 2005 Yajun Ha / ECE, NUS
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FPGA Lab 1 & 2Please print relevant docs by yourself and bring to labs!Watch the FPGA board demo closely
Lab 1: Try to re-implement the demo with Xilinx ISE on your FPGA board and do the assignment
Design files for the demo will be installed on your PC. You need to use Xilinx ISE tool to generate and download
the bitstream. Get familiar with Xilinx ISE environment and link the
various FPGA design flow steps to the tool. Browse and understand the design files for the demo.
Lab 2: Follow the Xilinx EDK tutorial that can be found in the TD5102 course web site under project page.
Lab session in Signal Processing and VLSI Lab (E4-08-34) 2:00-5:00pm on 13 & 14 Dec!
© NUS 2005 Yajun Ha / ECE, NUS
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Summary
FPGA architectures have been introduced.
EDA tools for FPGAs have been introduced.
Applications of FPGA for networked platforms have been introduced.
Lab introduction.