TCAD for reliability - Semantic Scholar · PDF fileTCAD for reliability ... opsys Sentaurus TCAD [1], are well established for modeling semi-conductor fabrication process, and device

Microelectronics Reliability 52 (2012) 1761–1768

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Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

TCAD for reliability

P. Pfäffli a,⇑, P. Tikhomirov a, X. Xu b, I. Avci b, Y.-S. Oh b, P. Balasingam b, S. Krishnamoorthy b, T. Ma b

a Synopsys Switzerland LLC, Thurgauerstrasse 40, CH-8050 Zürich, Switzerlandb Synopsys Inc, 700 East Middlefield Road, 94043 Mountain View, CA, USA

a r t i c l e i n f o a b s t r a c t

Article history:Received 30 May 2012Accepted 14 June 2012Available online 7 July 2012

0026-2714/$ - see front matter � 2012 Elsevier Ltd. Ahttp://dx.doi.org/10.1016/j.microrel.2012.06.025

⇑ Corresponding author. Tel.: +41 567 1525; fax: +4E-mail address: [email protected] (P. Pfäffli).

Using TCAD tools, many reliability issues can be studied quantitatively. Examples are hot carrier degra-dation of interfaces, threshold voltage shifts during NBTI stress, radiation effects and soft errors, ESD andlatch-up, thermo-mechanical issues, electro-migration and stress-voiding.

� 2012 Elsevier Ltd. All rights reserved.

1. Introduction

Technology Computer Aided Design (TCAD) tools, such as Syn-opsys Sentaurus TCAD [1], are well established for modeling semi-conductor fabrication process, and device operation. Processsimulation includes the modeling of process steps, such as implan-tation, diffusion, oxidation, etching, deposition, and mechanicalstress distribution. Device simulation considers the electrical andthermal behavior of devices, such as current flow and heat gener-ation in a transistor. Using TCAD, many reliability aspects can bemodeled. In the following article, we illustrate how TCAD is usedto model reliability issues.

2. Hot carriers and interface degradation

The quality of the silicon/silicon-dioxide interface in a MOStransistor directly influences the current flow through the device.High electrical current and high electric fields can create additionalinterface traps which lead to a threshold voltage shift and mobilitydegradation through additional scattering at trapped interfacecharges.

Especially, non-volatile memory cells with floating gates havebecome very sensitive to those effects since the demand for everhigher storage densities has led to continuous cell scaling, and areduction in the number of stored electrons per floating gate,which causes an increased sensitivity to charges trapped in thedielectrics. The effect of trapped charge can be well predicted byTCAD [2]. However, interface degradation is not only relevant forultra-short channel and for non-volatile memory devices, but alsofor smart power technologies used for automotive applications [3].

Since hot carriers are one of the main root causes of interfacedegradation, the simulation of the carrier energy distribution is

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very relevant in a degradation simulation. In Sentaurus Devicethe Spherical Harmonic Expansion (SHE) method can be used tosimulate the carrier energies and predict additional interface trapsgeneration [4].

The SHE model was used to simulate the degradation of anLDMOS device: Fig. 1 shows the current density distribution ofthe virgin (left) and degraded (right) device. It is clearly visible thatthe additional interface traps in the degraded device push the cur-rent further away from the interface and also lower it, which re-sults in a higher on-resistance (Ron). The degradation of Ron isshown in Fig. 2.

As mentioned before, hot carrier degradation is an importantreliability issue in floating gate memory cells. Program/erase(P/E) cycles can create interface and bulk traps via tunnelingcurrent and channel hot electron injection (CHE). Fig. 3 showsthe interface traps density along the channel of a NAND flash de-vice stressed with various P/E cycles. As a result of the additionalinterface traps, the threshold voltage degrades and the Ion de-creases because of remote Coulomb scattering (RCS) on chargedtrap centers, see Fig. 4.

3. Bias temperature instability

Negative bias temperature instability (NBTI) in p-MOSFETs andpositive bias temperature instability (PBTI) in n-MOSFETs areimportant reliability concerns in scaled CMOS technologies [5].Several models have been presented in the literature; the two-stage model described in [6] is implemented in Sentaurus Device.

The modeling approach considers device degradation underhigh gate bias and high temperature conditions due to the meta-stable charged oxygen vacancies (E

0centers in oxide) and poorly

recovering dangling bonds at silicon/oxide interface, both actingas fixed charged trap centers. Under certain bias conditions, thebond inside the E

0center can be passivated by acquiring hydrogen

dislodged from a Si dangling bond at the interface.

Fig. 1. Current density distribution before (left) and after (right) the degradation ofa LDMOS. The location of additional traps is also shown in the right picture (the redcolor indicates a higher interface trap density). (For interpretation of the referencesto color in this figure legend, the reader is referred to the web version of thisarticle.)

Fig. 2. LDMOS off-state Ron degradation versus stress time.

Fig. 3. Interface traps density along the channel after P/E cycle stress. The lightbrown contours represent part of the structure, which corresponds to the dottedpart of the structure shown in the insert.(For interpretation of the references tocolur in this figure legend, the reader is referred to the web version of this article.)

Fig. 4. Transfer characteristics after different number of P/E cycles.

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Using a 32 nm technology template [7], NBTI was simulatedwith Sentaurus Device, see Fig. 5. Details of this example are de-scribed in a SolvNet article, see [8].

4. Soft errors

Extrinsic ionizing radiation is as important to integrated circuitreliability as intrinsic failure modes. Heavy ions, alpha particles,muons or neutron-induced single event upset (SEU) can lead to softand hard errors in SRAM memory cells [9]. Due to scaling of mem-ory cells, the region of influence of ionizing radiation can be quitelarge, which has led to a number of new soft error mechanisms[10].

The effect of radiation and SEU can be studied with SentaurusDevice. As an example, Fig. 6 shows the flipping of the logic stateof the six-transistor SRAM cell due to the impact of a heavy ion.In the example, a heavy ion hits the node with logic ‘‘1’’, which isthe drain of the NMOS transistor in off-state. Electrons generatedalong the path of the heavy ion flood the logic ‘‘1’’ node and letthe flip–flop switch.

Fig. 7 shows the electron density distribution in the SRAM cellafter the heavy ion hits the cell near the drain of the NMOS transis-tor (only silicon is depicted, the shallow trench isolation oxide isnot shown). More details of this example are described in a SolvNetarticle [11].

5. Substrate currents

Substrate effects due to carrier injection are a major riskfor smart power IC. 3D device simulation can help to study theinjection of majority and minority carriers through parasitic tran-sistors into the substrate, their distribution in the substrate andpossible effects on other remote circuit elements [12].

Fig. 8 shows a model of a H-bridge switching an inductive load.During the switching, electrons and holes are injected through par-asitic structures into the substrate and change there the substratepotential. With the model, the effect of barrier structures and ofbackside contacts on the carrier distribution in the substrate canbe studied.

Fig. 5. NBTI degradation shows threshold voltage degradation for different bias stresses (left) and relaxation of threshold voltage after stress voltage is removed.

Fig. 6. Node voltages versus time as a result of a heavy ion hitting a SRAM cell.

Fig. 7. Electron density distribution after a heavy ion

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6. Oxide breakdown

With continuous scaling, gate oxides become thinner and theelectric fields grow larger, which makes transistors more vulner-able to oxide breakdown. Breakdown of a gate oxide is usuallydefined as the time when a conduction path through the oxideforms. At the beginning of the process isolated defects (traps) ex-ist in the oxide. Continuous stress with high electric fields andhot carrier injection creates additional defects (traps) in theoxide. After some time defects start to overlap and form a con-duction path [13]. Current flowing through the path generatesheat, which creates further defects, more current starts to flow,etc. Although standard TCAD tools cannot model the oxide bulktrap generation process, some of the root causes like high electricfields, tunneling currents and hot carrier injections can still bestudied.

particle hits the SRAM cell at the arrow position.

Fig. 8. Potential distribution after injection of majority and minority carriers into the substrate of a smart power chip during switching of a H-bridge.

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7. Junction breakdown

Feature scaling applies not only to CMOS and memory devices,but also to power semiconductors. Material properties combinedwith the required high voltage and high current requirementsmake it a difficult task, however. In order to increase the break-down voltage (BV), the electric field should be kept lower thanthe critical field at breakdown (in silicon about 2 � 105 V/cm)everywhere in the structure. TCAD simulations of the off-statebreakdown voltage and the specific on-resistance of power transis-tors allow great insight into the physical mechanisms and help findbetter device architectures.

Fig. 9 shows an example of breakdown voltage characteristics ofa SiC n-IGBT device. The Okuto model [14] was used for modelingthe avalanche process. Further details of the example are describedin an application note [15].

8. ESD and latch-up

Electrostatic discharge (ESD) protection for high voltage applica-tions is challenging. The main problem is the current filamentation,

Fig. 10. ESD triggered latch-up.

Fig. 9. Breakdown voltage characteristics of a 4H–SiC n-IGBT device.

which leads to non-uniform conduction and localized heating caus-ing thermal failure. TCAD simulations of devices under ESD stressconditions have a long tradition and are generally accepted as avery important step in designing robust devices and ICs [16–18].

In addition to ESD protection, the I/O cells should also offer goodlatch-up immunity. Protection devices act under ESD stress as car-rier injectors into the substrate, which could trigger parasitic SCR(thyristors) structures [19].

As an example Fig. 10 shows a latch-up of a CMOS structuretriggered by injection of holes into the substrate by an ESD protec-tion diode under stress. As soon as the applied voltage is largerthan 20.5 V, the parasitic SRC structure switches on and the currentincreases rapidly.

9. Electromigration and stress voiding

Electromigration (EM), in which atoms within metallic inter-connects drift under the influence of strong electron winds, is a

Fig. 11. Vacancy distribution near via.

Fig. 13. Vacancy concentration change for electron flow upstream (left) anddownstream (right).

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reliability problem of longstanding interest in microelectronics.Since current densities and therefore electron winds increase inaggressively scaled technologies, there is now a renewed interestin using simulation technologies to study, and mitigate problemscaused by EM-induced void nucleation and growth. In the litera-ture, EM has been modeled at several levels of sophistication,ranging from fundamental atomic level models to compact semi-empirical relations, such as Black’s equation. In TCAD an interme-diate framework based on vacancy fluxes [20] has been selectedbecause it achieves a suitable compromise between physics-basedpredictive power, and simulation turnaround time.

In Sentaurus Interconnect vacancy agglomeration, which leadsto void formation, is modeled using a mass transport equation withgradients of vacancy concentration, mechanical stress, electrical

Fig. 12. Time evolution of vacancy distribution, and hydrostatic pressure along a 1Dcutline taken over the lower metal line in Fig. 11.

Fig. 14. Resistance ratio change due to electromigration for different current sourceconditions. (For interpretation of the references to color in this figure legend, thereader is referred to the web version of this article.)

potential, and temperature as driving forces [21]. The tool alsomodels vacancy-induced stress evolution, which results from volu-metric strain caused by differences in the effective volumes ofatoms and vacancies. Once a void is nucleated it will grow byaccepting additional free vacancies. Since the number of vacanciesin a perfect metal is too small to nucleate voids, it is assumed thatthe main source of vacancies is grain-boundaries or materialinterfaces.

The redistribution of these vacancies occurs via two parallel dif-fusion mechanisms: (a) through the interiors of grains and (b)along grain boundaries and interfaces. The tool offers two alterna-tive methods to capture these diffusion mechanisms, depending onhow the grain boundaries are described. The first method, which isgenerally faster, is a continuum approach in which the grainboundaries are assumed to be described by an effective field-likequantity that permeates the whole metal layer. The other, compu-tationally more burdensome, method is to place discrete grainboundaries at specific locations within the interconnect. Once thegrains and grain boundaries are described using either method, va-cancy exchange between these entities is modeled by treatinggrain boundaries and interfaces as trap sites for vacancies.

In EM reliability studies it is often of interest to learn how va-cancy accumulation under a via evolves in time. Fig. 11 shows asnapshot of the vacancy distribution at a particular point in time.Fig. 12a shows the time evolution of the vacancy profile startingfrom time = 0. The profile is taken along a longitudinal 1D cut madeinside the lower metal line, shown in Fig. 11. Vacancies move to-ward the via end as time increases. The rate of vacancy accumula-tion is a function of the current density and the wire length.Fig. 12b shows the time evolution of the pressure, the average nor-mal stress, profile at the same cut location as in Fig. 12a. The pres-sure in the structure is affected by the vacancy movement since itintroduces volumetric strain in the wire.

Fig. 15. An interconnect structure with copper metal wires, low k dielectrics, and nitride cap layers.

Fig. 16. The first principal stress distributions in dielectrics surrounding Level 2metals after annealing. Pattern A: Regular fill pattern with small blocks. Pattern B:Fill pattern with large blocks. Stress distributions in metal lines and fills are notshown for better clarity.

(a) (b)

(c) (d)Fig. 17. (a) A TSV structure. (b) Shear stress distribution for an interface crackbetween metal and insulator. (c) Peeling stress distribution for an interface crack.(d) J-integral and safety factor for the crack with different insulators/barrier layers.

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Vacancy migration in interconnects is also a function of thedirection of current flow, and Fig. 13 shows two sets of results cor-responding to electron flow being imposed in the upstream ordownstream directions. The red regions show where the voidsare most likely to form. The flow direction dependent differencesseen in these simulations are consistent with experimental obser-vations [22].

The practical consequence of vacancy migration and the even-tual formation of voids is the significant change in resistance thatsignals interconnect failure. Sentaurus Interconnect simulates theresistance change using a void-dependent electrical conductivitymodel. In this model, as the fraction of monovacancies increases,the conductivity of the material decreases proportionally. In addi-tion, the model includes an abrupt decrease in conductivity whenthe vacancy concentration in the voids exceeds a critical valueindicating empty space. Fig. 14 shows the change in the resistanceratio with time for different current source conditions. This graphshows that the resistance change is more abrupt for the down-stream case, compared with the upstream case. As the current den-sity increases the abrupt change occurs earlier, showing thedependence of lifetime on operating conditions.

10. Thermo-mechanical

Advanced technologies use multi-level copper metallizationembedded in low-k dielectrics, as shown in Fig. 15. Due to the largedifference in thermal expansion coefficients, thermal mismatchstresses are generated during the manufacturing process as wellas during operation. Thermal mismatch stress distribution dependson the layout pattern. High stress concentrations in some local re-gions can lead to material cracking and impose reliability concerns.

In Fig. 16, two dummy fill patterns for Level 2 metal layer areevaluated [23]. Both patterns satisfy the requirement to attain ametal density of 42% in the region between a terminating wireand a jogged wire. Pattern A employs 15 small cubic blocks whilePattern B uses three large blocks. From a performance consider-ation, Pattern B is preferred since it represents a 16% reduction incoupling capacitance. However, from a reliability consideration,Pattern B should be avoided since it introduces high stress concen-tration as marked in [16]. Generally speaking, the geometricdependence of stress distribution is different from that of electricfield. TCAD simulation can identify high stress concentration hot-spots, and help to optimize interconnection layout designs thatmeet both performance and reliability requirements.

Three dimensional integration uses through-silicon via (TSV) toprovide the required integration densities along with the improve-ment in system performance, as shown in Fig. 17a. The distributionof shear stress (SZX) and peeling stress (SXX) around the tip of an ini-tial crack for metal/insulator interface are shown in Fig. 17b and c.Clearly, these stresses around the interfacial crack tip serve as the

Fig. 18. (a) Schematic of package structure. (b) Effective stress (MPa) before under-fill relaxation. (c) Effective stress after under-fill relaxation. (d) Effective stressbefore and after under-fill relaxation.

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damage driving force. The energy release rate is evaluated usingJ-integral and compared in Fig. 17d, together with the safety factor,which is the difference between the material cohesive strength andthe calculated J-integral. Although interface cracks between metaland oxide insulator show �30% higher J-integral, the interfaceswith oxide insulator possess larger safety factors than the interfacewith low-k insulator. Larger safety factor corresponds to strongerinterfacial adhesion and strength. This plot illustrates the greateradhesion and better reliability for metal/oxide interface as com-pared to the metal/low-k interface. For both insulation materials,TaN metal barrier shows slightly reduced J-integral as comparedto a barrier with Cu-like material properties, thus improved reli-ability. These simulation findings are consistent with recent mea-surements [24].

11. Chip-package interaction

Flip-chip technology utilizes solder bumps and surrounding un-der-fills to package the silicon chip. The chip-package interaction(CPI) is a major reliability concern for flip-chip packages especiallywith fragile low-k or ultra-low-k dielectrics that are adjacent to thebumps and under-fills. Near bump and die edge delamination arethe primary failure modes. It has been observed that under-fillmaterials exhibit non-negligible viscoelastic stress relaxation atoperation temperatures. Viscoelastic relaxation in the under-fill

material may lead to stress redistribution and cause overloadingand failure in the surrounding structures [25].

The dimensions of the simulated package structure are shownin Fig. 18a. The mechanical stresses at the chip edge and the firstbump are examined in greater detail with refined local analysis.Fig. 18b and c show the effective stress in the first solder bumpand the surrounding region before and after stress relaxation at125 �C, respectively. Fig. 18d shows the effective stress beforeand after stress relaxation along a cut-line normal to the xz-planeand situated at the center of the solder bumps. These results illus-trate that stress relaxation occurs in under-fill materials due to vis-coelastic deformation at the operation temperature. However, thestress relaxation in the under-fill material leads to the loss of loadcarrying capability and in turn subjects the solder bumps to higherloading. The highest stress concentration increase occurs in andaround the first bump close to the die edge. It is also interestingto note that the stresses are lower at die edge after stress relaxa-tion. This increased stress concentration at the first bump and re-duced stress concentration at die corner indicates a shift ofprimary failure modes from the die edge failure to the first bumpfailure.

12. Summary

In the article we have reviewed some of the main reliability is-sues which can be studied with TCAD. Simulation of these issuesgives qualitative as well as qualitative insight about the physicalprocesses which can degrade an electronic device and alsohelp optimize the robustness of the technology against reliabilityissues.

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