Task 1091.001: Highly Scalable Task 1091.001: Highly Scalable Placement by Multilevel Placement by Multilevel Optimization Optimization •Task Leaders: Jason Cong (UCLA CS) and Tony Chan (UCLA Math) •Students with Graduation Dates: •Michalis Romesis (UCLA CS, March 2005 --- graduated) •Kenton Sze (UCLA Math, July 2006 --- graduated) •Min Xie (UCLA CS, September 2006 --- graduated) •Guojie Luo (UCLA CS, September 2010) •Research Staff: Joe Shinnerl, UCLA CS
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Task 1091.001: Highly Scalable Placement by Multilevel Optimization Task Leaders: Jason Cong (UCLA CS) and Tony Chan (UCLA Math) Students with Graduation.
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•Task Leaders: Jason Cong (UCLA CS) and Tony Chan (UCLA Math)
•Students with Graduation Dates:•Michalis Romesis (UCLA CS, March 2005 ---graduated)•Kenton Sze (UCLA Math, July 2006 --- graduated)•Min Xie (UCLA CS, September 2006 --- graduated)•Guojie Luo (UCLA CS, September 2010)
•Research Staff: Joe Shinnerl, UCLA CS
23/4/18 UCLA VLSICAD LAB 2
Industrial LiaisonsIndustrial Liaisons
Patrick McGuinness, Freescale Semiconductor, Inc.Patrick McGuinness, Freescale Semiconductor, Inc.
Natesan Venkateswaran, IBM CorporationNatesan Venkateswaran, IBM Corporation
Amit Chowdhary, Intel CorporationAmit Chowdhary, Intel Corporation
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Task Description and Anticipated ResultTask Description and Anticipated Result
Highly scalable multilevel, multiheuristic placement algorithms Highly scalable multilevel, multiheuristic placement algorithms that address the critical placement needs of nanometer designs: that address the critical placement needs of nanometer designs: scalabilityscalability multi-constraint optimization multi-constraint optimization
--- timing, routability, power, manufacturability, etc.--- timing, routability, power, manufacturability, etc. support of mixed-sized placement and incremental design.support of mixed-sized placement and incremental design.
Quantitative study of the optimality and scalability of placement Quantitative study of the optimality and scalability of placement algorithmsalgorithms Construction of synthetic benchmarks with known optima to identify the Construction of synthetic benchmarks with known optima to identify the
deficiencies of existing methodsdeficiencies of existing methods
Our goal is to achieve one-process-generation benefit through Our goal is to achieve one-process-generation benefit through innovation of physical-design technologies, especially placement.innovation of physical-design technologies, especially placement.
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Task DeliverablesTask Deliverables Report on new placement benchmarks with known optimal or near optimal Report on new placement benchmarks with known optimal or near optimal
solutions for all major objectives and constraints. Scalability and optimization solutions for all major objectives and constraints. Scalability and optimization studies on existing placement techniques (studies on existing placement techniques (Completed 3-Nov-2003Completed 3-Nov-2003))
Experiments and reports on the applicability of integrated AMG-based weighted Experiments and reports on the applicability of integrated AMG-based weighted aggregation and weighted interpolation. Improvement measured on both PEKO aggregation and weighted interpolation. Improvement measured on both PEKO examples and industrial examples from SRC member companies (examples and industrial examples from SRC member companies (Completed 1-Completed 1-Jun-2004Jun-2004))
Experiments and reports on multiheuristic, multilevel relaxation and the scalable Experiments and reports on multiheuristic, multilevel relaxation and the scalable incorporation of complex constraints into the enhanced multilevel framework. incorporation of complex constraints into the enhanced multilevel framework. Improvement measured on both PEKO and industrial examples (Improvement measured on both PEKO and industrial examples (Completed 1-Completed 1-Jun-2005)Jun-2005)
A highly scalable placement tool that (i) supports multi-constraint optimization, A highly scalable placement tool that (i) supports multi-constraint optimization, mixed-sized placement, and incremental design and (ii) produces best-of-class mixed-sized placement, and incremental design and (ii) produces best-of-class results for both PEKO and industrial examples from SRC member companies results for both PEKO and industrial examples from SRC member companies ((Completed 1-Jun-2006Completed 1-Jun-2006))
Final report summarizing research accomplishments and future direction Final report summarizing research accomplishments and future direction (Planned-Oct-31, 2006)(Planned-Oct-31, 2006)
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Accomplishments in the Past YearAccomplishments in the Past Year
1.1. Improvements in mPL for routing density control Improvements in mPL for routing density control [Best quality, ISPD 2006 contest][Best quality, ISPD 2006 contest]
mPL 1.1• FC clustering• Partitioning addedto legalization mPL 2.0
• RDFL relaxation• Primal-dual netlist pruning
mPL 3.0 [ICCAD03]• QRS relaxation• AMG interpolation• Multiple V cycles
mPL 4.0• Improved DP• BacktrackingV cycle
23/4/18 UCLA VLSICAD LAB 7
mPL: Generalized Force-Directed PlacementmPL: Generalized Force-Directed Placement Use of accurate objective functions [Bertsekas, 82, Naylor et al, 01]Use of accurate objective functions [Bertsekas, 82, Naylor et al, 01]
Multilevel for better runtime and wirelengthMultilevel for better runtime and wirelength
)()(1 kkk
W xλx
)()()(1
ijijkijkλλ
,)( .. xts)( min xW
.),()( where11cxdx
is a generalized force
23/4/18 UCLA VLSICAD LAB 8
Accomplishments in the Past YearAccomplishments in the Past Year
1.1. Improvements in mPL for routing density Improvements in mPL for routing density control [Best quality, ISPD 2006 contest]control [Best quality, ISPD 2006 contest]
MotivationMotivation High power density due to technology scalingHigh power density due to technology scaling
Problems caused by high temperatureProblems caused by high temperature Hot spots become Hot spots become moremore harmful harmful
• Higher temperature Higher temperature Higher leakage power Higher leakage power More heat More heat Previously negligible effects become first-order effectsPreviously negligible effects become first-order effects
• Difficult estimation for power, timing, etcDifficult estimation for power, timing, etc
23/4/18 UCLA VLSICAD LAB 15
Thermal ModelThermal Model One layer mesh to model the One layer mesh to model the
substratesubstrate
ΣΣjj (T (Tii - T - T
jj) C) Cxyxy + (T + (T
ii – T – Tsinksink) C) C
zz = P = Pii
• CCxyxy, C, Czz are the thermal conductance for are the thermal conductance for
the substrate and the heat sinkthe substrate and the heat sink
Solved by Fast DCTSolved by Fast DCT• Solve T from CT = P, given C and PSolve T from CT = P, given C and P• Diagonalize C = Diagonalize C = ΓΓTTΛΓΛΓ
ΓΓ is the discrete cosine matrix is the discrete cosine matrix ΛΛ is a diagonal matrix is a diagonal matrix
• T = T = ΓΓ-1-1ΛΛ-1-1ΓΓ P P
Ti
Tj,1
Tj,2
Tj,3
Tj,4
Tsink
P
Cxy
Cz
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Formulation & SolutionFormulation & Solution
Implement Implement ii(x) and t(x) and tii(x) with filler cells and “filler power” without area(x) with filler cells and “filler power” without area
TTdesdes is a given by user is a given by user
Solved by Uzawa AlgorithmSolved by Uzawa Algorithm
As additional thermal-aware GFD following a WL-driven V-CycleAs additional thermal-aware GFD following a WL-driven V-Cycle
re)(Temperatu)()(
p)(Nonoverla)()(subject to
)(minimize
desii
ii
TxtxT
xx
xWL
))((
))((
0)()()(
)1()()1(
)1()()1(
)1()()1()()1(
desk
iki
ki
ki
ki
ki
i
ki
ki
i
ki
ki
k
TxT
x
xTxxWL
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Experiment Results on IBM-FastPlaceExperiment Results on IBM-FastPlace Quality improvementQuality improvement
TTeveneven is the ideal is the ideal
temperature with the same temperature with the same total powertotal power
Max. on-chip Max. on-chip temperature:temperature:• TTinitinit after Step 1 after Step 1
• TTfinalfinal = T = Tdes des after Stepafter Step
Accomplishments in the Past YearAccomplishments in the Past Year
1.1. Improvements in mPL for routing density control [1Improvements in mPL for routing density control [1stst quality, ISPD 2006 contest]quality, ISPD 2006 contest]
ASPDAC 2006ASPDAC 2006: : J. Cong, M. XieJ. Cong, M. Xie, “, “A Robust Detailed A Robust Detailed Placement for Mixed-size IC DesignsPlacement for Mixed-size IC Designs.”.”
ISPD 2006:ISPD 2006: T. F. Chan, J. Cong, J. Shinnerl, K. Sze and M. T. F. Chan, J. Cong, J. Shinnerl, K. Sze and M. Xie, “Xie, “mPL6: Enhanced Multilevel Mixed-size PlacementmPL6: Enhanced Multilevel Mixed-size Placement.”.”
ThesisThesis
Kenton SzeKenton Sze, “, “Multilevel Optimization for VLSI Circuit Multilevel Optimization for VLSI Circuit Placement.Placement.””
Min Xie,Min Xie, ““Constraint-Driven Large Scale Circuit Placement Constraint-Driven Large Scale Circuit Placement AlgorithmsAlgorithms.”.”
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Room for Further Improvement?Room for Further Improvement?
“Swirls” are difficult to correct with localized refinement