Prob : 1 Design a NMOS transistor with it's drain connected to voltage source V DD in steps of 0.1 volt from 0 volt to 5 volt for each value of gate to source voltage V GS and vary V GS from 0 volt to 5 volt in steps of 1 volt. Vary the gate to source voltage V DS and vary V DS from 0 volt to 5 volt in steps of 1 volt. Circuit Diagram: Circuit Diagram NETLIST for the above Circuit * SPICE netlist written by S-Edit Win32 Demo 9.12 * Written on Mar 12, 2006 at 07:18:05 * Waveform probing commands .probe .options probefilename="File0.dat" + probesdbfile="File0.sdb" + probetopmodule="Module0" .include "C:\Program Files\Tanner EDA\Demo\T- +Spice\models\ml1_typ.md" * Main circuit: Module0 M1 N7 N5 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u v2 N5 Gnd 5.0 v3 N7 Gnd 5.0 .dc v3 0 5 .01 v2 0 5 1 .print i(m1,n7) *End of main circuit: Module0
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Prob : 1Design a NMOS transistor with it's drain connected to voltage source VDD in stepsof 0.1 volt from 0 volt to 5 volt for each value of gate to source voltage VGS andvary VGS from 0 volt to 5 volt in steps of 1 volt. Vary the gate to source voltageVDS and vary VDS from 0 volt to 5 volt in steps of 1 volt.
Circuit Diagram:
Circuit Diagram
NETLIST for the above Circuit* SPICE netlist written by S-Edit Win32 Demo 9.12* Written on Mar 12, 2006 at 07:18:05
+ probesdbfile="File0.sdb"+ probetopmodule="Module0".include "C:\Program Files\Tanner EDA\Demo\T-+Spice\models\ml1_typ.md"* Main circuit: Module0M1 N7 N5 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uv2 N5 Gnd 5.0v3 N7 Gnd 5.0.dc v2 0 5 .01 v3 0 5 1.print i(m1,n7)* End of main circuit: Module0
Prob: 2In figure 1 plot the drain current ID as a function of bulk voltage VBB as VBBis varied from -5 volts to 0 volts. Ashume default level 1 MOS model parameter for TSPICE.
Prob :3In Fig 2. VDD! = +5 V and VDD2 = +6 V. Plot IOUT as a function of Iin. Theaspect ratio of each transistor is 5 um/5um. Repeate the process with VDD@ = +5V. Also plot Vout1 and Vout2 as a function of Iout. Use default level 1 MOS modelparameters for SPICE.
Circuit Diagram in Tanner Spice
NETLIST for the above Circuit* SPICE netlist written by S-Edit Win32 6.00* Written on Mar 9, 2006 at 19:15:15* Waveform probing commands.probe.options probefilename="File0.dat"+ probesdbfile="File0.sdb"+ probetopmodule="Module0"* Main circuit: Module0
Prob:4Design a resistive load nMOS inverter of which the load resistance is 5 KOHM.Observe it's voltage transfer charasteristics. Apply a bit stream of 10101101 to theinput where each bit has a duration of 20 nSec. A rise time and fall time of 0.01nSec. Observe the transient output response. Repeat the process for an activePMOS load inverter, a current source load inverter and a push pull inverter.Compare and comment on your observations with different inverters. Asshume thatthe on voltage is +5 volt and off voltage is 0 volt.
Circuit Diagram for 3 Different MOSFET Digital Inverter Circuit
NETLIST for the above 3 different Inverter Circuit
The Output current with respect to input voltage pulse
In the above output with respect to the pulse (bottommost) it is clear that theresistive and current source inverter circuit consumes current in on state, whereasthe push pull circuit does not consumes any current in no load state. The no loadcurrent drawn in the resistive inverter circuit is less(0.95 mA peak) than the
current source inverter circuit (6.3 mA peak). So, it can be concluded that the pushpull inverter is the best among all.
Prob:5Using CMOS logic design a CMOS 2 input (1) NAND gate (2) NOR Gate (3)XOR Gate. In each case Name the inputs as A and B. Apply a bit stream of A=10101101 and B=10110001 and observe the output of the gate. Take theduration of each bit as 20 nano second. Take rise time and fall time as 0.1 nanosecond.