Tallinn University of Technology Department of Computer Engineering Department of Computer Engineering ati.ttu.ee Jaan Raik DIAMOND: Targeting Verification and Reliability Issues in Systems
Dec 14, 2015
Tallinn University of TechnologyDepartment of Computer Engineering
Department of Computer Engineeringati.ttu.ee
Jaan Raik
DIAMOND: Targeting Verification and Reliability Issues in Systems
DIAMOND: Targeting Verification and Reliability Issues in Systems
EU FP7 STREP Project DIAMOND A holistic view of design and soft errors
Success stories: FoREnSiC (C, system-level) zamiaCAD (VHDL/Verilog/SC, RTL)
Follow-up projects Significance to CEBE
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Toyota problems: reliability or verification?
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The DIAMOND conceptSoft-errors caused by cosmic
radiation
DIAMOND’sdiagnosis/correction
methods
Soft-errors in new generation chips due to background radiation
Electronic systems fail while working in the field
Design mistakes made by the engineer
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DIAMOND: Objectives
A unified, holistic diagnostic model for bugs and soft errors at all levels;
Automated localisation & correction techniques based on the unified model, both pre-silicon & post-silicon;
Implementation of a reasoning framework for localisation & correction, encompassing word-level techniques, formal, semi-formal, and dynamic techniques.
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DIAMOND Kick-off, Tallinn, February 2-3, 20106
DIAMOND: FP7 collaborative research
FP7-2009-ICT-4-248613 DIAMOND - Diagnosis, Error Modelling and Correction for Reliable Systems Design
Start January 2010; total budget 3.8M € (EU contribution 2.9M €); 462.5 PM
The IBM logo is a registered trademark of International Business Machines Corporation (IBM) in the United States and other countries.
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Verification and debug
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• ~2/3 of development time for verification• ~2/3 of verification time for debug• Thus, nearly half of the development cycle!• Automation of the debug step needed...
Debug
Verification
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Traditional debug flow
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Verification
Design
Spec
Error!
Counter-examples (waveforms), failed assertions, ...
???
• Too little information• Too much information
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Automated debug flow
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Verification
Design
Spec
Error!
Corrected design, Repair log, ...
Error localization
Error correction
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Maksim Jenihhin
DIAMOND Debug Tools
FoREnSiC Formal automated debug
environment for ESL HW in C zamiaCAD
A highly scalable framework for design analysis and automated debug at RTL (VHDL-centric)
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FoREnSiC
FoREnSiC: Formal Repair Environment for Simple C For system-level HW Developed by TU Graz, University of Bremen and TUT Front-end converting simple C descriptions to
flowchart model, different debug back-ends Open source and available at:
http://www.informatik.uni-bremen.de/agra/eng/forensic.php
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Forensic Flow
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Available FoREnSiC Back-Ends
FoREnSiC includes 3 complementary back-ends: Symbolic back-end (TU Graz)
Symbolic+concolic engines and model-based diagnosis for localization; template-based correction.
Cut-based back-end (University of Bremen) Formally verifies the equivalence between a C program and
an implementation in HDL.
Simulation-based back-end (Tallinn University of Technology, University of Verona) Intended for correcting larger programs. Statistical
localization + mutation-based correction
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Statistical localization + mutations
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Dynamic slicing for localization
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Statistical analysis
Ranking according to suspiciousness:
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Suspiciousness score
Circuit blocks
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Fault model for correction
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MUTATION OPERATOR C OPERATORS/EXAMPLES AOR (arithmetic operator replacement) +, -, *, /, % ROR (relational operator replacement) ==, !=, >, <, >=, <= LCR (logical connector replacement) &&, || ASOR (assignment operator replacement) +=, -=, *=, /=, %=, =
UOR (unary operator replacement) +, -, ~, ! Bitwise operator replacement <<, >>, &, |, ^ Bitwise assignment operator replacement <<=, >>=, &=, |=, ^=
Increment/decrement operator replacement x++, ++x, x--, --x
Number mutation (decimal digit replacement in integers, floats and array indexes)
0...9
Constant replacement unary minus/ unary plus/ zero +C, 0, -C
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Design error correction experiments
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Maksim Jenihhin
zamiaCAD team and cooperation Günter Bartsch, Stuttgart – founder Rainer Dorsch, Stuttgart – Bosch/IBM Tallinn University of Technology
Anton Tšepurov, PhD student Maksim Jenihhin Valentin Tihhomirov, PhD student Saif Abrar PhD student Jaan Raik
IBM Faculty Award 2011/2012
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Maksim Jenihhin
zamiaCAD flow
http://zamiacad.sf.net Front-end currently
supports VHDL Object database ZDB
Persistence Scalability Custom designed Highly optimized for
performance
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Maksim Jenihhin 21
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Maksim Jenihhin
zamiaCAD Evaluation A case study on ROBSY microprocessor 17k lines of VHDL code Error localization based on statistical ranking
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Bug data The proposed automated localization Manual
debug Statistical Ranking Cone inspection Time (min)
Bug name
Failed/Passed Test cases
Statements cand. / %
Located stm. rank
Cone dir. / depth
Added stm. cand.
Time
Bug 1 4 / 24 14 / 2.9% 3 - - 2 4 hours Bug 2 2 / 26 7 / 1.4% 1 - - 2 2 hours Bug 3 2 / 26 20 / 4% 3 - - 2 4 hours Bug 4 1 / 27 6 / 1.2% (1) fw / 1 21 2+(5) 4 hours Bug 5 2 / 26 11 / 2.3% 1 - - 2 2 hours Bug 6 1 / 27 8 / 1.7% (1) bw / 1 13 2+(10) 5 hours Bug 7 1 / 27 21 / 4.3% (1) fw / 1 10 2+(1) 1 hours
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DIAMOND results
Publications 2 papers at IEEE D&T, 2 papers at JETTA, ...
PhD defenses 2012, S.Kostin, A.Tšertov, A.Karputkin, T.Viilukas 2013, I.Aleksejev, A.Tšepurov, U.Reinsalu
Follow-up projects FP7 STREP BASTION 3 EU COST Actions 1 Estonian ICT programme
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ICT COST Actions
Rich-model toolkit: an infrastructure for reliable computer systems 2009 oct. – 2013 oct.
Median: manufacturable and dependable multicore architectures at nanoscale 2011 dec. – 2015 nov.
Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE) 2012- 2016
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ICTP FUSETEST
Functional Self‐Test, Self‐Diagnosis and Failure Analysis for Integrated Electronics Systems (FUSETEST)
Partner: Testonica 2013 apr. – 2015 aug.
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Significance to CEBE
Verification and correction of bugs in the CEBE processor family
Application of design error correction engines in fine-tuning medical algorithms
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Thank you!
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More info: www.fp7-diamond.eu