Taking advantage of SiC’s high switching speedsfiles.iccmedia.com/events/powercon17/munich_12_littelfuse.pdf · Taking advantage of SiC’s high switching speeds. with optimizations

11

Dr. Kevin M. SpeerGlobal Manager of Technology StrategyPower Semiconductors

Power Electronics ConferenceTuesday 5 December 2017, Munich, Germany

Taking advantage of SiC’s high switching speedswith optimizations in measurement, layout, and design

OutlineSiC’s benefits over the IGBT

Common challenges and best practices

Accurate test & measurement

Optimized power loop layout

Proper gate drive design & integration

Summary






Summary

4Confidential and Proprietary | Littelfuse, Inc. © 2017 4Confidential and Proprietary | Littelfuse, Inc. © 2017

SiC MOSFETs vs Si IGBTs | root cause

Si GaN 4H-SiC Diamond*

Band gap (eV) 1.1 3.4 3.3 5.5

Breakdown field(MV/cm)

0.3 ~5 3 to 5 1 to 10

Carrier mobility(cm2/V-s)

n: 1450p: 370

n: 900p: 200

n: 948p: 99

n: 2000p: 2100

Saturation velocity(×107 cm/s)

1.0 2.5 2.0 2.7

Thermal conductivity(W/cm-K)

1.6 1.3 3.7 8.0

*The ionization energies of diamond are impractically large. For example, SiC’s shallow donors are < 100 meV, while diamond’s shallow donors are > 1700 meV.


SiC MOSFETs vs Si IGBTs | the compromise

SiC waferSiC drift region (1200 V uses ~12 μm)

SiC channel region

Source

Drain

Si wafer

Si drift region(1200 V needs ~120 μm)

Si channel region

Source

Drain

To block high voltage, the drift layer of a Si device must be ~10x thicker than for SiC, leading to:

• enormous conduction losses, since the drift layer is lightly doped, and hence…

• necessity to use of bipolar device architecture for high-voltage silicon


Yet there are drawbacks to silicon bipolar devices: Minority carriers injected across pn junctions in ON state When switched OFF, they must recombine or be swept out Both processes take time, leading to what is commonly known as reverse recovery Limits switching frequency and presents reliability concerns due to IGBT overstress

SiC MOSFETs vs Si IGBTs | the penalty

With SiC, we can make high-voltage devices using a unipolar structure, giving:• Reduced switching losses, PLUS…

• Capability to switch at higher speeds


D3

LCSI

Ls

Lg

Lpwr

Ld

Rg Vdc

IL

Vg

Standard double-pulse test circuit

Coupled inductance between the gate and power circuit

Limits switching speed and increases switching losses

Common source, LCSI

Parasitic inductance of the circuit flowing through the power device(s) and load

Major influence on voltage spikes during turn-off transient

Power loop, Lpwr

Inductance at the gate which can be part of the package or part of drive circuit

High-amplitude, MHz-range oscillations at turn-on, creating EMC issues

Gate, Lg

SiC | new possibilities…and problems

0

200

400

600

800

1.05 1.0502 1.0504 1.0506 1.0508 1.051

x 10-4

-200

0

200

400

600

800

1.05 1.0502 1.0504 1.0506 1.0508 1.051

-20

-10

0

10

20

Vds(V)

Ids(A)

1 1.001 1.002 1

-20

0

20

1 1.001 1.002 1

-10

0

10

20

Vgs(V)

Ids(A)

88Confidential and Proprietary | Littelfuse, Inc. © 2017

We are dealing with high voltages and high currents,and SiC can switch very fast

Problems that once went unnoticed with IGBTs have become design roadblocks

These design roadblocks then become commercial roadblocks

Littelfuse |device-maker + design assistant

And everyone wins.

As the designer/supplier of revolutionary technology,

the responsibility to help knock down design roadblocks rests with us.

Littelfuse Philosophy






Summary


Measurement | challenges

It is only through accurate, precise measurement that we can:

Fully appreciate the potential benefits of SiC

Identify problems at the prototype stage to prevent them at production

If we don’t know it’s broken,how can we fix it?

Si IGBT SiC MOSFET

dV/dt (V/ns) 10 50

dI/dt (A/ns) 0.5 3 - 5

Switching time (ns) > 100 < 30

Typical switching speeds of Si IGBT and SiC MOSFET

With these switching speeds, high-performance probes are needed to capture finer details of dynamic behavior


Measurement | best practices, Voltage

Method Pros Cons

Differential probes • Galvanic isolation • Limited bandwidth

Voltage divider • High bandwidth • Requires large

resistive load

Passive probes • High bandwidth

• Non-galvanic isolation

• Requires a common ground

Despite requiring dedicated isolation and a common ground, passive probes offer the necessary bandwidth to capture ultra-fast dynamic nuances without the added bulk and parasitics insertion of a voltage divider.

Recommendation


Measurement | best practices, CurrentMethod Pros Cons

Current probe • Galvanic isolation • Limited bandwidth

Current transformer

• High bandwidth• Galvanic isolation

• Saturates at large currents

• Not suitable for dc

Rogowski coil

• Galvanic isolation• Flexible tip

• Limited bandwidth• Not suitable for dc

Coaxial shunt

• High bandwidth• High accuracy

• Non-galvanic isolation

For characterization and evaluation purposes only, the coaxial shunt is an excellent choice due to its bandwidth and accuracy.

Recommendation






Summary


System loops | concept introduction

Gate-source loops

At a high level, the power system has two major loops…

Consider…

VDC/2

VDC/2

LOAD

S1HS Drive

S2LS Drive



Gate-source loops

Power loops


Consider…

VDC/2

VDC/2

LOAD

S1HS Drive

S2LS Drive



Gate-source loops

Power loops


Consider…

Common paths

VDC/2

VDC/2

LOAD

S1HS Drive

S2LS Drive


System loops | focus on Lpwr

Power loops

Lpwr can include:• the package (LD and LS)• the overall parasitic

inductance of the remaining power loop

ComponentsVDC/2

VDC/2

LOAD

S1HS Drive

S2LS Drive


Power loop layout | challengesProblem 1Voltage overshoot

Problem 2Switching oscillations

Caused by combination of parasitic inductance and fast switching speeds (di/dt)

Generates electromagnetic interference

Even at small values of Lpwr, can exceed typical design margins

Radiative or conductive coupling into nearby circuits

User must either slow down switching speed (which negates a benefit of SiC), or…

Malfunctions in gate drive, protection, etc.

…select higher-voltage components at higher costs, or resort to more complicated, multi-level topologies

Non-compliance with electromagnetic compatibility (EMC) mandates

1 1.0002 1.00041.0006 1.0008 1.001

-20

-10

0

10

20

Ids(A)

0

200

400

600

800

Vds(V)

Lpwr = 2 nHLpwr = 10 nH


Power loop layout | more on overshoot

600

625

650

675

700

725

750

1 2 5 10 15 20

Maximum VDS vs Parasitic inductance

Lpwr Ld Lcsi Lg Ls

125 V = 20.8%

75 V = 12.5%

Lpwr has substantial effect on overshoot voltage, easily exceeding design margins for modest values of Lpwr.

BEWARE!

Simulations using VDC = 600 V, IL = 20 A, di/dt = 2.5 A/ns, and Rg = 5 Ω. (P/N: SIC1MO120E0080)

Note: Just one pin on a standard TO-247-3L has a parasitic inductance of 7 nH!


Power loop layout | best practicesIf one bases each design choice around the following best practices, you’ll be well on your way to minimizing the effects of power loop inductance!

1. Emphasize compactness and simplicity. Board traces should be as short and/or wide as possible to minimize path inductance.

2. Overlap dc+ and dc-. To the greatest degree possible, overlap the dc+ and dc- traces in order to further reduce inductance of power loop.

3. Decoupling capacitor. Connect across dc rails – as close as possible to power switches – to mask high-frequency noise generated by the power devices from bleeding into the power loop. (results shown in appendix)

Recommendations






Summary


System loops | focus on Gate-source, Common

Gate-source loops

Common paths

Can include:• the package (LG and LS)• the overall parasitic

inductance of the remaining gate-source loop

• Also introduced is the common source inductance, Lcsi

ComponentsVDC/2

VDC/2

LOAD

S1HS Drive

S2LS Drive


Gate drive & integration | challenges

Problem 1VG overshoot (high LG, LS)

Problem 2High Lcsi

Caused by combination of parasitic inductance and fast switching speeds (di/dt)

Resists fast changes in current and slows down switching speed

Can lead to inadvertent turn-on and catastrophic shoot-through

Unnecessarily increases switching losses

Excessive oxide fields can also induce device damage and limit lifetime

The gate drive circuit has two purposes:1. Turn on/off the power switches in a stable and well-controlled manner2. Incorporate intelligent protection when necessary

1 1.001 1.002 1

-20

0

20

1 1.001 1.002 1

-10

0

10

20

Vgs(V)

Ids(A)

1.05 1.0502 1.0504 1.0506 1.0508 1.051

x 10-4

-200

0

200

400

600

800

1.05 1.0502 1.0504 1.0506 1.0508 1.051

-20

-10

0

10

20

Vds(V)

Ids(A)



Problem 1VG overshoot (high LG, LS)Caused by combination of parasitic inductance and fast switching speeds (di/dt)

Can lead to inadvertent turn-on and catastrophic shoot-through

Excessive oxide fields can also induce device damage and limit lifetime

1 1.001 1.002 1

-20

0

20

1 1.001 1.002 1

-10

0

10

20

Vgs(V)

Ids(A)

LG = 2 nH, LG = 10 nH

Simulations using VDC = 600 V, IL = 20 A, di/dt = 2.5 A/ns, and Rg = 5 Ω. (P/N: LFSIC1MO120E0080).

Even low values of LG

result in VGS oscillations well above Vth

Oscillations in VGS

naturally lead to ringing in IDS, which can give rise to EMC issues



Problem 2High Lcsi

Resists fast changes in current and slows down switching speed

Unnecessarily increases switching losses

Here we see how higher values of Lcsi lead to higher switching losses and undercut a key benefit of SiC

0

100

200

300

400

1 2 5 10 15 20

Eon (uJ) vs Lcsi

0

50

100

150

200

1 2 5 10 15 20Lcsi (nH)

Eoff (uJ) vs Lcsi

5 nH 20 nH

Etot(μJ)

266 545


Power loop layout | best practices

If one bases each design choice around the following best practices, you’ll be well on your way to optimizing the design and integration of your gate drive!

1. Reduce length of gate loop as much as possible. This will reduce magnitude of VGS

oscillations.2. Decouple gate loop from power loop. To reduce capacitive coupling and minimize

parasitic inductance. This can be done, for instance, using TO-247-4L or TO-263-7L with Kelvin source connections.

3. Orthogonal thinking. If possible, put the plane of the gate-source loop perpendicular to the plane of the power loop to reduce inductive coupling.

Recommendations


Summary

Because of its material properties, SiC is poised to disrupt the power electronics community like the IGBT did 30 years ago

Due to its high switching speed, new challenges are encountered that we must identify and resolve– Measurement

– Power loop design

– Gate drive design and integration

We have outlined a number of fundamentals and best practices to help designers get off to the right start

Thank you for your attention!


EXTRA SLIDES


Impact of decoupling capacitors

No on-board decoupling cap.130% VshootFres=13.2 MHz

With on-board decoupling cap.20% VshootFres=93 MHz

100ns/div

Gate voltage Vgs(20V/div) Drain-source voltage Vds(100V/div)Device current Ids(4A/div)

20ns/div

Gate voltage Vgs(20V/div) Drain-source voltage Vds(50V/div)Device current Ids(8A/div)


Device placement to reduce commutation loop

Through hole devices:• Horizontal power loop• Dec. Cap. on board• Placement for smallest commutation loop

- 25 nH Lcom

Surface mount devices:• Vertical power loop• Dec. Cap. placed on bottom • Minimized commutation loop

- 7nH Lcom


Copper planes to help simplify routing

• Reduce voltage drop, maintain the same voltage potential (for digital circuits)

• Reduce loop inductance and loop resistance, reduce radiated noise (dc bus)

• High frequency mirror current control (EMI noise reduction)

• Increase capacitive coupling with other circuits

Adding copper plane is not always good, only add plane when necessary


Mirror current control

HF signal line through split copper planes

Stitching capacitor

Trace routing with mirror current controlHF signal line through vias

LF

HF

Copper plane• Current only propagates through lowest impedance path• For high frequency current, current return through its

mirror current path

3434Confidential and Proprietary | Littelfuse, Inc. © 2017

There are some basic guidelines

Adding Kelvin source to alleviate LCSI

Advanced interconnect methodologies to optimize LS and LG

Discrete packaging

Assist with board design and layout to optimize Lpwr and decouple LS and LG

Ground plane design and mirror current control for EMI reduction

Layout support

Tailored support using decades of device and applications expertise

Evaluation kits, reference designs, and demo boards

Design tools

Simplify customer integration of high-current components

Advanced attach and interconnect methodologies to optimize Rth and L’s

Module packaging

Taking advantage of SiC’s high switching speedsfiles.iccmedia.com/events/powercon17/munich_12_littelfuse.pdf · Taking advantage of SiC’s high switching speeds. with optimizations

Documents