Page 1 EE457 Instructor: G. Puvvada Homework #6 Due: ============================================================== Part I Complete the exercises on cache below. Out of the six cases, the first case was fully answered. All processors are considered to be byte-addressable processors. Direct Fully Associative Block-set Associative 2 Blocks/Set Direct Fully Associative Block-set Associative 4 Blocks/Set Direct Fully Associative Block-set Associative 4 Blocks/Set Direct Fully Associative Block-set Associative 2 Blocks/Set Direct Fully Associative Block-set Associative 4 Blocks/Set Mapping Technique Addr Space Cache Size Block Size TAG FIELD BLOCK OR SET FIELD WORD FIELD Processor 16-bit Data 20-bit address 16-bit Data 20-bit address 32-bit Data 20-bit address 32-bit Data 32-bit address 64-bit Data 32-bit address Size 1MB 8KB 2 Words (4 Bytes) 8-bit wide A19 - A12 10-bit wide A11 - A2 1-bit wide A1 A0 (BE1 , BE0 ) BYTE FIELD (as appropriate) 18-bit wide A19 - A2 1-bit wide A1 A0 (BE1 , BE0 ) 7-bit wide A19 - A13 11-bit wide A12 - A2 1-bit wide A1 A0 (BE1 , BE0 ) Block field Set field 16KB 4 Words (8 Bytes) 2 Words (8 Bytes) 4 Words (16 Bytes) 2 Words (16 Bytes) 32KB 128KB 512KB Direct Fully Associative Block-set Associative 2 k Blocks/Set (2 b x8)-bit Data m-bit address 2 w Words ( 2 w+b Bytes) 2 c B 2 m B Note: For an 8-bit processor, word is same as byte. Hence, in the last case above, b will be zero and the byte filed and word field will be merged into one field of w bits.
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EE457 Instructor: G. PuvvadaHomework #6 Due:
==============================================================Part I Complete the exercises on cache below. Out of the six cases, the first case was fully answered. All processors are considered to be byte-addressable processors.
Direct
Fully Associative
Block-set Associative2 Blocks/Set
Direct
Fully Associative
Block-set Associative4 Blocks/Set
Direct
Fully Associative
Block-set Associative4 Blocks/Set
Direct
Fully Associative
Block-set Associative2 Blocks/Set
Direct
Fully Associative
Block-set Associative4 Blocks/Set
MappingTechnique
AddrSpace
CacheSize
BlockSize
TAG FIELD BLOCK ORSET FIELD
WORDFIELD
Processor
16-b
it D
ata
20-b
it a
ddre
ss16
-bit
Dat
a20
-bit
add
ress
32-b
it D
ata
20-b
it a
ddre
ss32
-bit
Dat
a32
-bit
add
ress
64-b
it D
ata
32-b
it a
ddre
ss
Size
1MB 8KB 2Words(4Bytes)
8-bit wideA19 - A12
10-bit wideA11 - A2
1-bit wideA1
A0(BE1, BE0)
BYTEFIELD
(as appropriate)
18-bit wideA19 - A2
1-bit wideA1
A0(BE1, BE0)
7-bit wideA19 - A13
11-bit wideA12 - A2
1-bit wideA1
A0(BE1, BE0)Block field
Set field
16KB
4Words(8Bytes)
2Words(8Bytes)
4Words(16Bytes)
2Words(16Bytes)
32KB
128KB
512KB
Direct
Fully Associative
Block-set Associative2k Blocks/Set
(2b x8
)-bi
t Dat
a m
-bit
add
ress
2w
Words( 2w+b
Bytes)
2cB2mB
Note: For an 8-bit processor, word is same as byte. Hence, in the last case above, b will be zero and the byte filed and word field will be merged into one field of w bits.
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Part II From the textbook. Notation: 2nd Ed. problem number(1st Ed. problem number)
Problems 7.7(7.1), 7.8(7.2), 7.20(7.3)
Part III Please refer to your classnotes pages 7-21, 7-22, and 7-23.
Design a cache arrangement (similar to the one shown in page 7-A-22)for a 80386-based system (80386: 32-bit address, 32-bit data system).Use the following parameters.
Main memory address space: 4 GBCache size: 1 MBBlock size: 2 words (8 bytes)Set size: 2 Blocks
Figure out the cache data RAM and Tag RAM sizes, system addressbit connections, etc. Use interleaved memory organization similar tofig 7.13c in your book (7.12c in 1st edition). The bus size is 32-bit here. Since block size is only two words, the degree of interleaving may be different from what is shown in fig 7.13c (7.12c in 1st edition).
Part IV Question 6 from Spring 1994 Midterm exam (Attached).Part V Questions 5 and 6 from Summer 1994 Midterm exam (Attached).Part VI Question 4 from Spring 1999 Midterm exam (Attached).Part VII Question 3 from Spring 1999 Final exam (Attached).Part VIII Question 3 from Fall 1999 Final exam (Attached).
Note: In your exam questions, you find the following formats for the address from the CPU. You are asked (in the exams)to divide, the same into appropriate fields.For example, for the first case (16-bit data, 20-bit address, direct mapping), you would have done as shown below.
Text of the three problems 7.7(7.1), 7.8(7.2), 7.20(7.3) from the 1st Ed./2nd Ed., which are not available in the 3rd edition of the textbook
Notation: 2nd edition problem number (1st edition problem number)
Problem 7.7(7.1)Here is a series of address references given as word addresses: 1, 4, 8, 5, 20, 17, 19, 56, 9, 11, 4, 43, 5, 6, 9, 17. Assuming a direct-mapped cache with 16 one-word blocks that is initially empty, label each reference in the list as a hit or a miss and show the final contents of the cache.
Problem 7.8(7.2)Using the series of references given in Exercise 7.7, show the hits and misses and final cache contents for a direct-mapped cache with four-word blocks and a total size of 16 words.
Problem 7.20(7.3)Using the series of references given in Exercise 7.7, show the hits and misses and final cache contents for a two-way set-associative cache with one-word blocks and a total size of 16 words. Assume LRU replacement.