5 5 4 4 3 3 2 2 1 1 D D C C B B A A A Table of Content Cover Block Diagram Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Revision History Rev. Code Date Description By 1. Interrupted lines coded with the same letter or letter combinations are electrically connected. CPU PWR PWR TREE 2018-03-12 Frank Initial version LPDDR4 eMMC//QSPI CPU IO CPU PHY BOOT CFG PMIC CPU MISC (i.MX8M Mini Reference Board) 8MMINILPD4-CPU 8MMINILPD4-CPU 8MMINILPD4-CPU 8MMINILPD4-CPU WIFI/BT Module SOM Interface 2. Device type number is for reference only. The number varies with the manufacturer. 3. Special signal usage: _B Denotes - Active-Low Signal <> or [] Denotes - Vectored Signals 4. Interpret diagram in accordance with American National Standards Institute specifications, current revision, with the exception of logic block symbology. This board was designed for maximum flexibility in software development and demonstrates multiple functions possible with i.MX processors. Although best design practices have been applied, some areas may not be suitable for a mass-production design. Preliminary - Subject to Change without Notice! NXP CONFIDENTIAL AND PROPRIETARY A1 1. Update U1 I.MX8M Mini symbol naming. Frank 2018-03-27 1. Change PMIC U8 to BD71847; Frank 2018-05-01 B 2. Add external PU resistor R133 for SD2_nRST, as internal is PD and ROM won't pull it to high; 3. DNP R63,R64,C389,C390, as internal VREF works well; B1 2018-06-19 Frank 1. Remove the IOMUX table; C 2018-09-12 Frank 2. Remove external DDR VREF Circuit as Internal works well; 1. Remove optional 32K Crystal Circuit for i.MX8M Mini; 8. Update the description of the Block Diagram and Power Tree; 3. Add R134, R135 for BOOT_MODE3 option to TESTMODE for compatible design with i.MX8M Nano; 5. Remove R50, R62, R107, R128 to simplify the optional design; 4. Change J4_Pin56 from GND to TESTMODE(BOOT_MODE3) for compatible design with i.MX8M Nano; 7. Update the symbol of i.MX8M Mini: 6. Remove C7 for NVCC_3V3; 9. Update some descriptions of the schematic; 10. Add R136, C405 on VDD_MIPI_1V2 for compatible design with i.MX8M Nano; > Correct naming for AB13 from PVCC0_1V8 to PVCC0_1P8; > Correct power domain for B27, C26 from NVCC_CLK to VDD_24M_XTAL_1P8; > Correct power domain for J23, J24 from VDDA_1P8 to VDD_ANA1_1P8; > Correct power domain for A22, B22, F22, A23, B23, F23 to VDD_USB_3P3; > Correct power domain for D22, E19, D23, E22 to VDD_USB_1P8, and also adjust the pin locations. 2018-11-29 Frank C1 1. Remove the note for R136; Frank C2 1. Update the Min/Typ/Max operating range for I.MX8M Mini power supplies; 2019-1-31 3. Add note for all IOs that internal pull up/down is not supported in 3.3V mode; 2. Add note for changing BD71847 BUCK1/2/5 output voltage according to the new operation range; Drawing Title: Size Document Number Rev Date: Sheet of Page Title: Designer: Drawn by: Approved: Microcontroller Product Group 6501 William Cannon Drive West Austin, TX 78735-8598 This document contains information proprietary to NXP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors. ICAP Classification: CP: IUO: PUBI: SCH-31399 PDF: SPF-31399 C2 8MMINILPD4-CPU C Monday, February 11, 2019 Title and Rev History Frank Liu <Approver> Frank Liu 1 13 ___ _X_ ___ Drawing Title: Size Document Number Rev Date: Sheet of Page Title: Designer: Drawn by: Approved: Microcontroller Product Group 6501 William Cannon Drive West Austin, TX 78735-8598 This document contains information proprietary to NXP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors. ICAP Classification: CP: IUO: PUBI: SCH-31399 PDF: SPF-31399 C2 8MMINILPD4-CPU C Monday, February 11, 2019 Title and Rev History Frank Liu <Approver> Frank Liu 1 13 ___ _X_ ___ Drawing Title: Size Document Number Rev Date: Sheet of Page Title: Designer: Drawn by: Approved: Microcontroller Product Group 6501 William Cannon Drive West Austin, TX 78735-8598 This document contains information proprietary to NXP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors. ICAP Classification: CP: IUO: PUBI: SCH-31399 PDF: SPF-31399 C2 8MMINILPD4-CPU C Monday, February 11, 2019 Title and Rev History Frank Liu <Approver> Frank Liu 1 13 ___ _X_ ___
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A
Table of Content
Cover
Block Diagram
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Revision History
Rev. Code Date DescriptionBy
1. Interrupted lines coded with the same letter or letter combinations are electrically connected.
CPU PWR
PWR TREE
2018-03-12 Frank Initial version
LPDDR4
eMMC//QSPI
CPU IO
CPU PHY
BOOT CFG
PMIC
CPU MISC
(i.MX8M Mini Reference Board)8MMINILPD4-CPU8MMINILPD4-CPU8MMINILPD4-CPU8MMINILPD4-CPU
WIFI/BT Module
SOM Interface
2. Device type number is for reference only. The number varies with the manufacturer.
3. Special signal usage:
_B Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
4. Interpret diagram in accordance with American National Standards Institute specifications, current revision, with the exception of logic block symbology.
This board was designed for maximum flexibility insoftware development and demonstrates multiplefunctions possible with i.MX processors. Although bestdesign practices have been applied, some areas maynot be suitable for a mass-production design.
Preliminary - Subject to Change without Notice!
NXP CONFIDENTIAL AND PROPRIETARY
A1 1. Update U1 I.MX8M Mini symbol naming.Frank2018-03-27
1. Change PMIC U8 to BD71847;
Frank2018-05-01B 2. Add external PU resistor R133 for SD2_nRST, as internal is PD and ROM won't pull it to high;
3. DNP R63,R64,C389,C390, as internal VREF works well;
B1 2018-06-19 Frank 1. Remove the IOMUX table;
C 2018-09-12 Frank
2. Remove external DDR VREF Circuit as Internal works well;
1. Remove optional 32K Crystal Circuit for i.MX8M Mini;
8. Update the description of the Block Diagram and Power Tree;
3. Add R134, R135 for BOOT_MODE3 option to TESTMODE for compatible design with i.MX8M Nano;
5. Remove R50, R62, R107, R128 to simplify the optional design;
4. Change J4_Pin56 from GND to TESTMODE(BOOT_MODE3) for compatible design with i.MX8M Nano;
7. Update the symbol of i.MX8M Mini:
6. Remove C7 for NVCC_3V3;
9. Update some descriptions of the schematic;
10. Add R136, C405 on VDD_MIPI_1V2 for compatible design with i.MX8M Nano;
> Correct naming for AB13 from PVCC0_1V8 to PVCC0_1P8;> Correct power domain for B27, C26 from NVCC_CLK to VDD_24M_XTAL_1P8;> Correct power domain for J23, J24 from VDDA_1P8 to VDD_ANA1_1P8;> Correct power domain for A22, B22, F22, A23, B23, F23 to VDD_USB_3P3;> Correct power domain for D22, E19, D23, E22 to VDD_USB_1P8, and also adjust the pin locations.
2018-11-29 FrankC1 1. Remove the note for R136;
FrankC21. Update the Min/Typ/Max operating range for I.MX8M Mini power supplies;
2019-1-31
3. Add note for all IOs that internal pull up/down is not supported in 3.3V mode;
2. Add note for changing BD71847 BUCK1/2/5 output voltage according to the new operation range;
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Title and Rev History
Frank Liu
<Approver>
Frank Liu
1 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Title and Rev History
Frank Liu
<Approver>
Frank Liu
1 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Title and Rev History
Frank Liu
<Approver>
Frank Liu
1 13
____X____
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
On SOM Board
I2SDAC
Cirrus Logic WM8524
WiFi/BT802.11b/g/n/ac
M.2 NGFFKEY-E:WiFi/BT...
LANE x4
MIPI DSI
mini-SAS CN
MIPI CSI
mini-SAS CN
GPIO/UART
EXP CN
LPDDR4 DRAM
Micron LPDDR4 16GbMT53D512M32D2DS-053 WT:D
x32 bits
eMMCx8 bits
GPIO/SAI/I2C...GPIO/UART...
Audio Card
SAI/GPIO/I2C...
MicroSD
ButtonONOFF
x4 bits
SDIO
SDIO
ONOFF/GPIO
JTAGMIPI DSI MIPI CSI
SDIO/UART/PCM
PCIe
SAI
SAI/I2C
ARM CORTEX 4x A53 + M4
P
2.4/5GHz
2.4/5GHz
POWERPMIC
ROHM BD71847MWV
i.MX8M MiniLPDDR4
NX
UART->USB FT2232D
JTAG
10 PIN Header
JTAG
USB TYPE-CUSB 2.0 OTG
DRP x2USB OTG
Infrared / LED
GPIO/PWM
Giga EthernetQualcomm: AR8031
I2C
I2C CN
I2C/RST
SD3.0 Support
PWM
DBG UART
LANE x4
GPIO/UART I2C
8MMINILPD4-EVK Block Diagram
ButtonReset
Micron 32MBMT25QU256ABA1
QSPI Norx4 bits
Sandisk 16GBSDINBDG4-16G-I1
RJ45RGMII
UART
RGMII
x2 UART(A53/M4)
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Block Diagram
Frank Liu
<Approver>
Frank Liu
2 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Block Diagram
Frank Liu
<Approver>
Frank Liu
2 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Block Diagram
Frank Liu
<Approver>
Frank Liu
2 13
____X____
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Base Board
LPDDR4
QSPI
eMMC
WiFi/BT
VDD1VDD2/VDDQ
VCC
VCCQVCC
VBATVIO
CPU: i.MX8M Mini
1234566778910101112
NVCC_SNVS_1V8VDD_SNVS_0V8RTC_RESET_BCLK_32K_OUTVDD_SOC_0V8VDD_DRAM&PU_0V9VDD_PHY_0V9VDD_ARM_0V9VDDA_1V8VDD_1V8/NVCC_1V8NVCC_DRAM_1V1NVCC_3V3NVCC_SD2VDD_PHY_1V2POR_BNVCC_ENET
1.80.8----0.850.95(0.975)0.90.85/0.95/1.01.81.81.13.33.3/1.81.2--1.8/2.5
1010----10002500102200300500NxCxVx(0.5xF)NxCxVx(0.5xF)10010--10
PWR/SignalSEQ TYP Required(mA)
PMIC: BD71847
1234566778910101112
LDO1LDO2RTC_RESET_BRTC_CLKBUCK1BUCK5LDO4BUCK2LDO3BUCK7BUCK8BUCK6MUXSWLDO6POR_B
1.80.8----0.850.9750.90.85/0.95/1.01.81.81.13.33.3/1.81.2--
1010----300030002503000300150030003000150300--
REGSEQ TYP Max Capability(mA)
8MMINILPD4-EVK PWR TREE
VSYS
5V
Base Board Peripherals
NVCC_ENET
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Power Tree
Frank Liu
<Approver>
Frank Liu
3 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Power Tree
Frank Liu
<Approver>
Frank Liu
3 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
Power Tree
Frank Liu
<Approver>
Frank Liu
3 13
____X____
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
i.MX8M Mini PWR
Supply from Base Board
GNDGND
NVCC_SNVS_1V8
GND
VDD_SNVS_0V8 GND
NVCC_SD2
NVCC_ENET
GND
NVCC_1V8
GND
VDD_SOC_0V8
GND
VDD_DRAM&PU_0V9
VDDA_1V8
NVCC_DRAM_1V1
GND
GND
NVCC_3V3
NVCC_3V3
VDD_1V8 NVCC_1V8
VDD_3V3
VDDA_1V8
GND
VDD_SOC_0V8
GND
GND
VDDA_1V8
GND
VDD_1V8
GND
VDD_PHY_0V9
VDD_PHY_1V2
GNDGND
GND
VDD_ARM_0V9
GND
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, January 07, 2019
CPU PWR
Frank Liu
<Approver>
Frank Liu
4 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, January 07, 2019
CPU PWR
Frank Liu
<Approver>
Frank Liu
4 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, January 07, 2019
CPU PWR
Frank Liu
<Approver>
Frank Liu
4 13
____X____
C210.22UF10V0201_CC
C2010uF6.3V0402_CC
C151uF6.3V0201_CC
C2531uF6.3V0201_CC
C741uF6.3V0201_CC
R136 0
C300.22UF10V0201_CC
C541uF6.3V0201_CC
C990.22UF10V0201_CC
C2511uF6.3V0201_CC
C931uF6.3V0201_CC
C3310uF6.3V0402_CC
C2561uF6.3V0201_CC
C2671uF6.3V0201_CC
C1000.22UF10V0201_CC
C2640.22UF10V0201_CC
C2604.7uF10V0402_CC
C90.22UF10V0201_CC
C481uF6.3V0201_CC
C2440.22UF10V0201_CC
C2682200PF
0201_CC16V
C26610uF6.3V0402_CC
C781uF6.3V0201_CC
C4052.2uF
DNP
10V0402_CC
C8910uF6.3V0402_CC
C1010.22UF10V0201_CC
C30.22UF10V0201_CC
C2541uF6.3V0201_CC
C901uF6.3V0201_CC
C2344.7uF10V0402_CC
C361uF6.3V0201_CC
C50.22UF10V0201_CC
C1040.22UF10V0201_CC
C2410.22UF10V0201_CC
C8810uF6.3V0402_CC
C911uF6.3V0201_CC
C2350.22UF10V0201_CC
C2551uF6.3V0201_CC
C80.22UF10V0201_CC
C10.22UF10V0201_CC
C170.22UF10V0201_CC
C611uF6.3V0201_CC
C3920.22UF10V0201_CC
C651uF6.3V0201_CC
i.MX8M Mini - GND
U1N
MIMX8MM6DVTLZAA
VSS50G15 VSS49G13 VSS48G10 VSS47
F3 VSS46F25 VSS45E3 VSS44
E25 VSS43C9 VSS42C6 VSS41C5 VSS40
C23 VSS39C22 VSS38C2 VSS37
C19 VSS36C18 VSS35C15
VSS33C13 VSS32C10 VSS31
B3 VSS30B26
VSS28AG1 VSS27AF3 VSS26AE9
VSS24AE5 VSS23
AE23 VSS22AE22 VSS21AE2 VSS20
AE19 VSS19AE18 VSS18AE15 VSS17AE14 VSS16AE13 VSS15AE10 VSS14AC3 VSS13
AC25 VSS12AB3 VSS11
AB25 VSS10AA9 VSS9AA7 VSS8
AA21 VSS7AA19 VSS6AA18 VSS5AA15 VSS4AA13 VSS3AA10 VSS2
A27 VSS1A1
VSS88R7
VSS89T12
VSS90T16
VSS51G18
VSS52G19
VSS53G21
VSS54G7
VSS55G9
VSS56H18
VSS57H2
VSS58J21
VSS59J25
VSS60J3
VSS61J7
VSS62K20
VSS64K25
VSS65K3
VSS66K7
VSS67L12
VSS68L16
VSS71N12
VSS72N16
VSS73N21
VSS74N25
VSS75N3
VSS76N7
VSS77P13
VSS78P15
VSS79P21
VSS80P25
VSS81P3
VSS82R12
VSS85R21
VSS86R25
VSS83R16
VSS84R20
VSS34C14
VSS25AE6
VSS91U12
VSS63K21
VSS69M12
VSS70M16
VSS87R3
VSS97W21
VSS92U16
VSS93V21
VSS29AG27
VSS94V25
VSS95V3
VSS96V7
VSS98W25
VSS99W3
VSS100W7
VSS101Y13
VSS102Y18
VSS103Y2
C351uF6.3V0201_CC
C161uF6.3V0201_CC
C951uF6.3V0201_CC
C230.22UF10V0201_CC
i.MX8M Mini - Power
MIMX8MM6DVTLZAA
U1M
NVCC_SNVS_1P8J22
VDD_SNVS_0P8K22
VDD_SOC1K15
NVCC_JTAGL19
VDD_DRAM1L10
VDD_DRAM2N10
VDD_DRAM3R10
VDD_DRAM4U10
VDD_SOC10R18
VDD_DRAM_PLL_1P8P5
VDD_SOC2K16
VDD_SOC3L15
VDD_SOC4M15
VDD_ARM1R13
PVCC0_1P8AB13
VDD_VPU1K12
PVCC2_1P8J13
NVCC_GPIO1W12
NVCC_ENETW22
VDD_ARM2R15
VDD_SOC9R17
VDD_VPU2K13
VDD_SOC6N15
VDD_ARM5T15
VDD_ARM3T13
VDD_ARM4T14
VDD_VPU3L11
VDD_VPU4L13
NVCC_SD2V22
VDD_ARM6U13
VDD_ANA_0P8_2N17
NVCC_SAI5W17
VDD_VPU5M13
VDD_GPU1P12
NVCC_SAI1W18
NVCC_CLKM19
VDD_GPU2R11
PVCC1_1P8T19
VDD_ANA1_1P8_2P19
VDD_GPU3U11
VDD_GPU4V12
NVCC_NANDU19
NVCC_I2CJ11
NVCC_SAI2V19
VDD_GPU5W11
NC1J18
VDD_ANA0_1P8_1Y15
VDD_ARM10V16
VDD_ARM11W13
NVCC_ECSPIH10
NVCC_UARTJ12
NVCC_SAI3Y10
VDD_ARM8V13 VDD_ARM7U15
NVCC_DRAM9T9 NVCC_DRAM8R9 NVCC_DRAM7R8
NVCC_DRAM5N8
NVCC_DRAM6N9
NVCC_DRAM1K8
NVCC_DRAM3L9
NVCC_DRAM4M9
VDD_ANA_0P8_1L17
NVCC_DRAM2K9
NVCC_SD1V20
VDD_SOC8L18
VDD_ANA1_1P8_1N20VDD_ANA0_1P8_2AA14
VDD_ARM_PLL_1P8R19
VDD_VPU6M14
VDD_ARM_PLL_0P8P16
NVCC_DRAM10U9
NVCC_DRAM12V9
VDD_ARM9V15
NVCC_DRAM11V8
VDD_SOC5N13
VDD_SOC7N18
VDD_DRAM_PLL_0P8P9
VDD_24M_XTAL_1P8N19
VDD_DRAM5J10
VDD_ARM13W15 VDD_ARM12W14
VDD_SOC11U17
VDD_SOC12U18
VDD_VPU7N11
VDD_DRAM6W10
VDD_ARM14W16
VDD_USB_3P3K19
VDD_USB_1P8H15
VDD_USB_0P8J17
VDD_PCI_1P8G14
VDD_PCI_0P8J16
VDD_MIPI_1P8H13
VDD_MIPI_1P2J15
VDD_MIPI_0P9J14
MIPI_VREG_CAPD15
NVCC_DRAM13P7
C26510uF6.3V0402_CC
C4000.22UF10V0201_CC
C941uF6.3V0201_CC
C5510uF6.3V
0402_CC
C60.22UF10V0201_CC
C2481uF6.3V0201_CC
C921uF6.3V0201_CC
C3911uF6.3V0201_CC
C24710uF6.3V0402_CC
VDD_MIPI_1V2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.06-1.17V
Power supply voltage ramp:
RESET_n is held LOW. VDD1 >= VDD2 VDD2 >= VDDQ
DRAM_RESET_NDRAM_ALERT_NDRAM_AC00DRAM_AC01DRAM_AC02DRAM_AC03DRAM_AC04DRAM_AC05DRAM_AC06DRAM_AC07DRAM_AC08DRAM_AC09DRAM_AC10DRAM_AC11DRAM_AC12DRAM_AC13DRAM_AC14DRAM_AC15DRAM_AC16DRAM_AC17DRAM_AC19DRAM_AC20DRAM_AC21DRAM_AC22DRAM_AC23DRAM_AC24DRAM_AC25DRAM_AC26DRAM_AC27DRAM_AC28DRAM_AC29DRAM_AC30DRAM_AC31DRAM_AC32DRAM_AC33DRAM_AC34DRAM_AC35DRAM_AC36DRAM_AC37DRAM_AC38DRAM_ZNDRAM_VREF
RESET_NMTEST1CKE0_ACKE1_ACS0_ACS1_ACK_t_ACK_c_A//CA0_ACA1_ACA2_ACA3_ACA4_ACA5_A
///MTESTCKE0_BCKE1_BCS1_BCS0_BCK_t_BCK_c_B//CA0_BCA1_BCA2_BCA3_BCA4_BCA5_B
////ZQVREF
RESET_nALERT_n / MTEST1CKE0CKE1CS0_nC0BG0BG1ACT_nA9A12A11A7A8A6A5A4A3CK_t_ACK_c_AMTESTCK_t_BCK_c_B//A2A1BA1PARITYA13BA0A10 / APA0C2CAS_n / A15WE_n / A14RAS_n / A16ODT0ODT1CS1_nZQVREF
Pin Name LPDDR4 DDR4
DQS0_t_ADQS0_c_ADMI0_ADQ0_ADQ1_ADQ2_ADQ3_ADQ4_ADQ5_ADQ6_ADQ7_ADQS1_t_ADQS1_c_ADMI1_ADQ08_ADQ09_ADQ10_ADQ11_ADQ12_ADQ13_ADQ14_ADQ15_ADQS0_t_BDQS0_c_BDMI0_BDQ0_BDQ1_BDQ2_BDQ3_BDQ4_BDQ5_BDQ6_BDQ7_BDQS1_t_BDQS1_c_BDMI1_BDQ08_BDQ09_BDQ10_BDQ11_BDQ12_BDQ13_BDQ14_BDQ15_B
Pin Name
DQSL_t_ADQSL_c_ADML_n_A / DBIL_n_ADQL0_ADQL1_ADQL2_ADQL3_ADQL4_ADQL5_ADQL6_ADQL7_ADQSU_t_ADQSU_c_ADMU_n_A / DBIU_n_ADQU0_ADQU1_ADQU2_ADQU3_ADQU4_ADQU5_ADQU6_ADQU7_ADQSL_t_BDQSL_c_BDML_n_B / DBIL_n_BDQL0_BDQL1_BDQL2_BDQL3_BDQL4_BDQL5_BDQL6_BDQL7_BDQSU_t_BDQSU_c_BDMU_n_B / DBIU_n_BDQU0_BDQU1_BDQU2_BDQU3_BDQU4_BDQU5_BDQU6_BDQU7_B
DRAM_DQS0_PDRAM_DQS0_NDRAM_DM0DRAM_DQ00DRAM_DQ01DRAM_DQ02DRAM_DQ03DRAM_DQ04DRAM_DQ05DRAM_DQ06DRAM_DQ07DRAM_DQS1_PDRAM_DQS1_NDRAM_DM1DRAM_DQ08DRAM_DQ09DRAM_DQ10DRAM_DQ11DRAM_DQ12DRAM_DQ13DRAM_DQ14DRAM_DQ15DRAM_DQS2_PDRAM_DQS2_NDRAM_DM2DRAM_DQ16DRAM_DQ17DRAM_DQ18DRAM_DQ19DRAM_DQ20DRAM_DQ21DRAM_DQ22DRAM_DQ23DRAM_DQS3_PDRAM_DQS3_NDRAM_DM3DRAM_DQ24DRAM_DQ25DRAM_DQ26DRAM_DQ27DRAM_DQ28DRAM_DQ29DRAM_DQ30DRAM_DQ31
LPDDR4 DDR4
Data Bus Command/Address
LPDDR4 2GB
GND
GND
GND
GNDNVCC_DRAM_1V1
GND
GND
VDD_1V8
GND
NVCC_DRAM_1V1
NVCC_DRAM_1V1
GND
GND
NVCC_DRAM_1V1
NVCC_DRAM_1V1
GND
GND
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, January 07, 2019
LPDDR4
Frank Liu
<Approver>
Frank Liu
5 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, January 07, 2019
LPDDR4
Frank Liu
<Approver>
Frank Liu
5 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, January 07, 2019
LPDDR4
Frank Liu
<Approver>
Frank Liu
5 13
____X____
R5 240 OHM1%
C3730.22uF10V0201_CC
C3840.22uF10V0201_CC
C10910uF6.3V0402_CC
R6 240 OHMDNP 1%
C11910uF6.3V0402_CC
R91501%
C3740.22uF10V0201_CC
TP37
C3720.22uF10V0201_CC
C10510uF6.3V0402_CC
R121 10KDNP
C3750.22uF10V0201_CC
MT53D512M32D2DS-053 WT:D
U2B
VDD2_R8R8
VDD1_F1F1
VDD1_F12F12
VDD1_G4G4
VDD1_G9G9
VDD1_T4T4
VDD1_T9T9
VDD1_U1U1
VDD1_U12U12
VDD2_A4A4
VDD2_A9A9
VDD2_F5F5
VDD2_F8F8
VSS_AB8AB8
VDD2_AB4AB4
VSS_AB5AB5
VSS_AB10AB10
VDD2_AB9AB9
VDD2_H1H1
VDD2_H5H5
VDD2_H8H8
VDD2_H12H12
VDD2_K1K1
VDD2_K3K3
VDD2_K10K10
VDD2_K12K12
VDD2_N1N1
VDD2_N3N3
VDD2_N10N10
VDD2_N12N12
VDD2_R1R1
VDD2_R5R5
VDDQ_B3B3
VDDQ_B5B5
VDDQ_B8B8
VDDQ_B10B10
VDDQ_D1D1
VDDQ_D5D5
VDDQ_D8D8
VDDQ_D12D12
VDDQ_F3F3
VDDQ_F10F10
VDDQ_U3U3
VDDQ_U10U10
VDDQ_W1W1
VDDQ_W5W5
VDDQ_W8W8
VDDQ_W12W12
VDDQ_AA3AA3
VDD2_U8U8 VDD2_U5U5 VDD2_R12
R12
VDDQ_AA5AA5
VDDQ_AA8AA8
VDDQ_AA10AA10
VSS_AB3AB3VSS_Y12Y12VSS_Y8Y8VSS_Y5Y5VSS_Y1Y1VSS_W11W11VSS_W9W9VSS_W4W4VSS_W2W2VSS_V12V12VSS_V8V8VSS_V5V5VSS_V1V1VSS_T12T12VSS_T10T10VSS_T8T8VSS_T5T5VSS_T3T3VSS_T1T1VSS_P12P12VSS_P10P10VSS_P3P3VSS_P1P1VSS_N11N11VSS_N9N9VSS_N4N4VSS_N2N2VSS_K11K11VSS_K9K9VSS_K4K4VSS_K2K2VSS_J12J12VSS_J10J10VSS_J3J3VSS_J1J1VSS_G12G12VSS_G10G10VSS_G8G8VSS_G5G5VSS_G3G3VSS_G1G1VSS_E12E12VSS_E8E8VSS_E5E5VSS_E1E1VSS_D11D11VSS_D9D9VSS_D4D4VSS_D2D2VSS_C12C12VSS_C8C8VSS_C5C5VSS_C1C1VSS_A10A10VSS_A3A3
C11810uF6.3V0402_CC
i.MX8M Mini - DDRPAD/(LPDDR4/DDR4/DDR3)
MIMX8MM6DVTLZAA
U1A
DRAM_DQ05B1
DRAM_DQ29AF1
DRAM_DQ26AD2
DRAM_DQ24AG5
DRAM_DQ00A5
DRAM_DQ02D2
DRAM_AC25/CK_c_B / A1 / A1U1
DRAM_DQ27AD1
DRAM_DM2AB1
DRAM_DQ01B5
DRAM_DM0A4
DRAM_DQ03D1
DRAM_DQ25AF5
DRAM_AC24/CK_t_B / A2 / A2U2
DRAM_DQS3_NAF2
DRAM_DQS0_NB2DRAM_DQS0_PA2
DRAM_DQS1_NH1
DRAM_DQS2_PAA1
DRAM_ALERT_NR2
DRAM_DQS2_NY1
DRAM_DQ21V1
DRAM_DM3AG4
DRAM_DQS3_PAG2
DRAM_DQ16AB2
DRAM_DQ07B4
DRAM_DQ08F2
DRAM_DQS1_PG1
DRAM_DM1F1
DRAM_DQ13K1
DRAM_AC19/MTEST / MTEST / MTESTN2
RESET_n / RESET_n / RESET#R1
DRAM_DQ31AF4
DRAM_DQ23AC2
DRAM_DQ20V2
DRAM_DQ22AC1
DRAM_DQ19W2
DRAM_DQ17AA2
DRAM_DQ18W1
DRAM_DQ06A3
DRAM_DQ04C1
DRAM_DQ10J1DRAM_DQ09G2
DRAM_DQ11J2
DRAM_DQ28AE1
DRAM_DQ14E1
DRAM_DQ12K2
DRAM_DQ15E2
VREF / VREF / VREFP1
DRAM_ZNP2
DRAM_DQ30AG3
DRAM_AC34/ -- /WE_n(A14)/WE#T1
DRAM_AC27/-- / PARITY / --R6
DRAM_AC35/-- / RAS_n(A16) / RAS#T2
DRAM_AC26/-- / BA1 / BA1N1
DRAM_AC07/-- / A9 / A9J5
DRAM_AC38/-- / CS1_n / CS1#AB6
DRAM_AC36/-- / ODT0 / ODT0V5
DRAM_AC15/-- / A3 / A3N6 DRAM_AC37/-- / ODT1 / ODT1W5
DRAM_AC06/-- / ACT_n / A15F6
DRAM_AC08/CA0_A / A12 / A12(BC#)J6
DRAM_AC09/CA1_A / A11 / A11K6
DRAM_AC10/CA2_A / A7 / A7E4
DRAM_AC11/CA3_A / A8 / A8D5
DRAM_AC12/CA4_A / A6 / A6N4
DRAM_AC13/CA5_A / A5 / A5N5
DRAM_AC02/CS0_A / CS0_n / CS0#K4
DRAM_AC03/CS1_A / C0 / --J4
DRAM_AC00/CKE0_A / CKE0 / CKE0F4
DRAM_AC01/CKE1_A / CKE1 / CKE1F5
DRAM_AC04/CK_t_A / BG0 / BA2L2
DRAM_AC05/CK_c_A / BG1 / A14L1
DRAM_AC14/ -- / A4 / A4K5
DRAM_AC28/CA0_B / A13 / A13W6
DRAM_AC29/CA1_B / BA0 / BA0V6
DRAM_AC30/CA2_B / A10(AP) / A10(AP)AC4
DRAM_AC31/CA3_B / A0 / A0AD5
DRAM_AC32/CA4_B / C2 / --R4
DRAM_AC33/CA5_B/CAS_n(A15)/CAS#R5
DRAM_AC23/CS0_B / -- / --V4
DRAM_AC22/CS1_B / -- / --W4
DRAM_AC20/CKE0_B / CK_t_B / CK_BAB4
DRAM_AC21/CKE1_B / CK_c_B / CK#_BAB5
DRAM_AC17/-- / CK_c_A / CK#_AM2 DRAM_AC16/-- / CK_t_A / CK_AM1
C3710.22uF10V0201_CC
C1140.22uF10V0201_CC
C10810uF6.3V0402_CC
C3760.22uF10V0201_CC
C3780.22uF10V0201_CC
C10610uF6.3V0402_CC
C11710uF6.3V0402_CC
C3700.22uF10V0201_CC
R4 10K
C11010uF6.3V0402_CC
C3790.22uF10V0201_CC
TP15
R123 10KDNP
C3820.22uF10V0201_CC
R122 10KDNP
C11310uF6.3V0402_CC
C3800.22uF10V0201_CC
R7 240 OHM1%
R124 10KDNP
C11110uF6.3V0402_CC
MT53D512M32D2DS-053 WT:D
U2A
CA0_AH2
CA0_BR2
CA1_AJ2
CA1_BP2
CA2_AH9
CA2_BR9
CA3_AH10
CA3_BR10
CA4_AH11
CA4_BR11
CA5_AJ11
CA5_BP11
CK_c_AJ9
CK_c_BP9
CK_t_AJ8
CK_t_BP8
CKE0_AJ4
CKE0_BP4
NC_J5J5
NC_P5P5
CS0_AH4
CS0_BR4
NC_H3H3
NC_R3R3
DMI0_AC3
DMI0_BY3
DMI1_AC10
DMI1_BY10
DNU_A1A1DNU_A2A2DNU_A11A11DNU_A12A12DNU_B1B1DNU_B12B12DNU_AA1AA1DNU_AA12AA12DNU_AB1AB1DNU_AB2AB2DNU_AB11AB11DNU_AB12AB12
DQ0_AB2
DQ0_BAA2
DQ1_AC2
DQ1_BY2
DQ2_AE2
DQ2_BV2
DQ3_AF2
DQ3_BU2
DQ4_AF4
DQ4_BU4
DQ5_AE4
DQ5_BV4
DQ6_AC4
DQ6_BY4
DQ7_AB4
DQ7_BAA4
DQ8_AB11
DQ8_BAA11
DQ9_AC11
DQ9_BY11
DQ10_AE11
DQ10_BV11
DQ11_AF11
DQ11_BU11
DQ12_AF9
DQ12_BU9
DQ13_AE9
DQ13_BV9
DQ14_AC9
DQ14_BY9
DQ15_AB9
DQ15_BAA9
DQS0_c_AE3
DQS0_c_BV3
DQS0_t_AD3
DQS0_t_BW3
DQS1_c_AE10
DQS1_c_BV10
DQS1_t_AD10
DQS1_t_BW10
NC_G11G11
NC_K5K5
NC_K8K8
NC_N5N5
NC_N8N8
ODT_CA_AG2
ODT_CA_BT2
RESET_NT11
ZQ0A5
NC_A8A8
C11510uF6.3V0402_CC
C3810.22uF10V0201_CC
C11210uF6.3V0402_CC
R81501%
DRAM_CK_C_A
DRAM_CK_T_A
DRAM_CK_C_B
DRAM_CK_T_B
DRAM_nRESET
DRAM_VREF DRAM_nRESET
DRAM_ZQ0
DRAM_ZQ1
DRAM_CA1_ADRAM_CA0_A
DRAM_CA3_A
DRAM_CA5_ADRAM_CA4_A
DRAM_CA2_A
DRAM_CK_C_ADRAM_CK_T_A
DRAM_nCS1_ADRAM_nCS0_A
DRAM_CKE0_ADRAM_CKE1_A
DRAM_CA1_BDRAM_CA0_B
DRAM_CA3_B
DRAM_CA5_BDRAM_CA4_B
DRAM_CA2_B
DRAM_CK_T_BDRAM_CK_C_B
DRAM_CKE0_BDRAM_CKE1_B
DRAM_nCS1_BDRAM_nCS0_B
DRAM_nCS0_A
DRAM_CA2_ADRAM_CA1_ADRAM_CA0_A
DRAM_CA3_ADRAM_CA4_ADRAM_CA5_A
DRAM_nCS1_A
DRAM_CKE0_ADRAM_CKE1_A
DRAM_CK_T_ADRAM_CK_C_A
ODT_CA_A
DRAM_CKE0_BDRAM_CKE1_B
DRAM_CK_T_BDRAM_CK_C_B
ODT_CA_B
DRAM_nCS1_BDRAM_nCS0_B
DRAM_CA1_B
DRAM_CA3_B
DRAM_CA5_BDRAM_CA4_B
DRAM_CA2_B
DRAM_CA0_B
DRAM_DMI1_A
DRAM_SDQS1_C_ADRAM_SDQS1_T_A
DRAM_DMI0_A
DRAM_SDQS0_C_ADRAM_SDQS0_T_A
DRAM_SDQS1_T_B
DRAM_DMI1_B
DRAM_SDQS1_C_B
DRAM_DMI0_B
DRAM_SDQS0_C_BDRAM_SDQS0_T_B
DRAM_DATA9_ADRAM_DATA8_A
DRAM_DATA14_ADRAM_DATA15_A
DRAM_DATA13_A
DRAM_DATA11_A
DRAM_DATA10_A
DRAM_DATA12_A
DRAM_DATA5_BDRAM_DATA4_B
DRAM_DATA2_BDRAM_DATA3_BDRAM_DATA1_BDRAM_DATA0_B
DRAM_DATA6_BDRAM_DATA7_B
DRAM_DATA0_ADRAM_DATA1_A
DRAM_DATA7_ADRAM_DATA6_ADRAM_DATA5_ADRAM_DATA4_A
DRAM_DATA2_ADRAM_DATA3_A
DRAM_DATA11_BDRAM_DATA10_B
DRAM_DATA12_BDRAM_DATA13_B
DRAM_DATA8_BDRAM_DATA9_B
DRAM_DATA15_BDRAM_DATA14_B
DRAM_SDQS1_C_B
DRAM_DATA4_BDRAM_DATA5_BDRAM_DATA6_BDRAM_DATA7_B
DRAM_DATA0_BDRAM_DATA1_BDRAM_DATA2_BDRAM_DATA3_B
DRAM_DATA14_B
DRAM_DATA9_B
DRAM_DATA15_B
DRAM_DATA8_B
DRAM_DATA10_B
DRAM_SDQS0_T_BDRAM_SDQS0_C_B
DRAM_DMI1_BDRAM_DMI0_B
DRAM_DATA11_BDRAM_DATA12_BDRAM_DATA13_B
DRAM_SDQS0_T_ADRAM_SDQS0_C_A
DRAM_DMI1_ADRAM_DMI0_A
DRAM_SDQS1_T_B
DRAM_DATA12_ADRAM_DATA13_A
DRAM_DATA8_A
DRAM_SDQS1_T_ADRAM_SDQS1_C_A
DRAM_DATA0_A
DRAM_DATA3_A
DRAM_DATA14_ADRAM_DATA15_A
DRAM_DATA9_ADRAM_DATA10_ADRAM_DATA11_A
DRAM_DATA2_ADRAM_DATA1_A
DRAM_DATA5_ADRAM_DATA6_ADRAM_DATA7_A
DRAM_DATA4_A
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M4 Debug
A53 Debug
Configure internal pull up at CPU sideConfigure internal pull up at CPU side
Dummy DQS for QSPI High Speed Timing
On Board BT
On Board BT
On Board BT
On Board WiFi
i.MX8M Mini IO Interface
Blink: SYS_STATUS
Configure internal pull up at CPU sideConfigure internal pull up at CPU side, open drain output
External PU is necessary for SD2 power control!
LED
IO internal pull up/down is not supported in 3.3V mode, must disable the internal pull up/downvia software and use external pull up/down resistors instead.All IO pin groups are impacted except for XTAL, DDR, PCI, USB and MIPI PHY IO's.See Errata e50080 for detailed information.
Caution:
GND
NVCC_1V8
NVCC_SD2
VDD_3V3
GND
SD1_CMD10
SD1_DATA110SD1_DATA210
SD1_DATA010
SD1_CLK10
SD1_DATA310
SD2_CMD 13
SD2_DATA0 13
SD2_CLK 13
SD2_nRST 13SD2_nCD 13
SAI1_MCLK 13
SAI1_TXFS 13SAI1_TXC 13
SAI1_TXD0 13SAI1_TXD1 13SAI1_TXD2 13SAI1_TXD3 11,13SAI1_TXD4 13SAI1_TXD5 11,13SAI1_TXD6 13SAI1_TXD7 13
SAI1_RXFS 13SAI1_RXC 13
SAI1_RXD0 13SAI1_RXD1 11,13SAI1_RXD2 11,13SAI1_RXD3 13SAI1_RXD4 13SAI1_RXD5 11,13SAI1_RXD6 11,13SAI1_RXD7 13
SAI2_MCLK 13
SAI2_RXD 10SAI2_RXC 13SAI2_RXFS 13
SAI2_TXD 10SAI2_TXC 10SAI2_TXFS 10
SAI3_TXFS13
SAI3_MCLK13
SAI3_RXFS13SAI3_RXC13
SAI3_TXD13SAI3_TXC13
SAI3_RXD13
SPDIF_EXT_CLK13SPDIF_RX13SPDIF_TX13
SAI5_RXFS13
SAI5_MCLK13
PDM_DATA013
ENET_MDIO 13ENET_MDC 13
ENET_TX_CTL 13ENET_TXC 13ENET_TD0 13ENET_TD1 13ENET_TD2 13ENET_TD3 13
ENET_RX_CTL 13ENET_RXC 13ENET_RD0 13ENET_RD1 13ENET_RD2 13ENET_RD3 13
QSPIA_nSS0 9
QSPIA_SCLK 9
UART1_TXD10UART1_RXD10
UART2_TXD13UART2_RXD13
I2C1_SDA 12I2C1_SCL 12
I2C2_SDA 13I2C2_SCL 13
I2C3_SDA 13I2C3_SCL 13
SD3_CMD 9SD3_CLK 9
UART4_RXD13UART4_TXD13
REF_CLK_32K 10,13
SD3_STROBE 9
SD3_DATA4 9
SD3_DATA5 9SD3_DATA6 9
SD3_DATA7 9
BT_WAKE_DEV10BT_WAKE_HOST10
BT_REG_ON10
WL_WAKE_HOST10
WL_REG_ON10
QSPIA_DATA1 9QSPIA_DATA0 9
SD3_DATA0 9
QSPIA_DATA2 9QSPIA_DATA3 9
WDOG_B 12
UART3_TXD13
UART3_RXD13
UART3_RTS13
UART3_CTS13SD2_VSEL 12
UART1_CTS10UART1_RTS10
GPIO1_IO01 13
GPIO1_IO05 13GPIO1_IO06 13GPIO1_IO07 13GPIO1_IO08 13GPIO1_IO09 13GPIO1_IO10 13GPIO1_IO11 13GPIO1_IO12 13GPIO1_IO13 13GPIO1_IO14 13GPIO1_IO15 13
SD1_STROBE13
PDM_DATA113PDM_DATA213PDM_DATA313
PDM_CLK13
ECSPI2_SCLK13ECSPI2_MISO13ECSPI2_MOSI13ECSPI2_SS013
I2C4_SCL 13I2C4_SDA 13
PMIC_nINT 12
SD2_WP 13
SD2_DATA1 13SD2_DATA2 13SD2_DATA3 13
SD3_DATA1 9SD3_DATA2 9SD3_DATA3 9
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
CPU IO
Frank Liu
<Approver>
Frank Liu
6 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
CPU IO
Frank Liu
<Approver>
Frank Liu
6 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
CPU IO
Frank Liu
<Approver>
Frank Liu
6 13
____X____
C24518pF50V0201_CC
R16 4.7K DNP
R133 4.7K
D1
LED GREEN
AC
R11 4.7K
R119 10K DNP
R120 10K DNP
R15 4.7K
NVCC_ENET
i.MX8M Mini - eNET
MIMX8MM6DVTLZAA
U1J
ENET_RD3AC26
ENET_RD1AD27
ENET_RD2AD26
ENET_RD0AE27
ENET_RX_CTLAF27
ENET_RXCAE26
ENET_TXCAG24
ENET_TD1AF26ENET_TD0AG26
ENET_TD2AG25
ENET_TD3AF25
ENET_TX_CTLAF24
ENET_MDCAC27
ENET_MDIOAB27
i.MX8M Mini - SDHC
NVCC_SD1
NVCC_SD2
MIMX8MM6DVTLZAA
U1I
SD1_STROBER24
SD1_DATA7W26 SD1_DATA6W27
SD1_RESET_BR23
SD2_WPAA27
SD1_DATA3T26
SD1_DATA5U26
SD2_RESET_BAB26
SD2_DATA3V23
SD1_DATA0Y27
SD1_DATA4U27
SD2_DATA1AB24SD2_DATA0AB23
SD1_DATA2T27 SD1_DATA1Y26
SD2_CLKW23
SD2_DATA2V24
SD1_CLKV26
SD1_CMDV27
SD2_CMDW24
SD2_CD_BAA26
R17 4.7K DNP
NVCC_SAI2
NVCC_SAI1
NVCC_SAI3
i.MX8M Mini - SAI
NVCC_SAI5
MIMX8MM6DVTLZAA
U1G
SAI5_RXFSAB15
SAI5_RXD0AD18
SAI5_RXD2AD13
SAI5_RXCAC15
SAI5_RXD1AC14
SAI1_RXD1AF15
SAI1_RXFSAG16
SAI5_RXD3AC13
SAI5_MCLKAD15
SAI1_RXD0AG15
SAI1_RXCAF16
SAI2_RXD0AC24
SAI2_RXFSAC19
SAI1_RXD3AF17
SAI1_RXD4AG18
SAI2_TXCAD22SAI2_TXFSAD23
SAI2_RXCAB22
SAI1_RXD2AG17
SAI1_TXFSAB19
SAI2_MCLKAD19
SAI2_TXD0AC22
SAI3_RXFSAG8
SAI3_TXFSAC6
SAI1_RXD6AG19
SAI1_RXD7AF19
SPDIF_RXAG9 SPDIF_TXAF9
SAI3_RXCAG7
SAI3_RXDAF7
SAI1_TXD0AG20
SAI1_RXD5AF18
SPDIF_EXT_CLKAF8
SAI1_TXD1AF20
SAI1_TXCAC18
SAI1_TXD4AG22SAI1_TXD3AF21
SAI3_MCLKAD6
SAI1_TXD5AF22
SAI1_TXD7AF23
SAI3_TXDAF6
SAI1_TXD6AG23
SAI1_TXD2AG21
SAI3_TXCAG6
SAI1_MCLKAB18
R12 4.7KR13 4.7K
i.MX8M Mini - NAND
NVCC_NAND
MIMX8MM6DVTLZAA
U1H
NAND_DQSR22
NAND_DATA07N26
NAND_DATA04M26
NAND_DATA06K26
NAND_WE_BR26
NAND_WP_BR27
NAND_READY_BP26
NAND_RE_BN27
NAND_DATA05L26
NAND_DATA03N23
NAND_DATA01K24
NAND_DATA02K23
NAND_CLEK27
NAND_CE3_BL27
NAND_CE0_BN24
NAND_CE1_BP27
NAND_DATA00P23
NAND_ALEN22
NAND_CE2_BM27
R1251K
NVCC_GPIO1
NVCC_ECSPI
i.MX8M Mini - SPI&GPIO
MIMX8MM6DVTLZAA
U1K
GPIO1_IO01AF14GPIO1_IO00AG14
GPIO1_IO02AG13
GPIO1_IO05AF12GPIO1_IO04AG12GPIO1_IO03AF13
GPIO1_IO08AG10GPIO1_IO07AF11GPIO1_IO06AG11
GPIO1_IO10AD10GPIO1_IO09AF10
GPIO1_IO12AB10GPIO1_IO11AC10
GPIO1_IO14AC9GPIO1_IO13AD9
GPIO1_IO15AB9
ECSPI2_MOSIB8
ECSPI1_SS0B6
ECSPI2_SCLKE6
ECSPI1_MOSIB7
ECSPI2_MISOA8
ECSPI1_MISOA7
ECSPI2_SS0A6
ECSPI1_SCLKD6
i.MX8M Mini - UART&I2C
NVCC_I2C
NVCC_UART
MIMX8MM6DVTLZAA
U1F
I2C2_SDAD9I2C2_SCLD10
I2C1_SCLE9
I2C4_SDAE13I2C4_SCLD13
I2C1_SDAF9
I2C3_SCLE10
I2C3_SDAF10
UART2_RXDF15
UART2_TXDE15
UART1_RXDE14
UART1_TXDF13
UART4_RXDF19
UART4_TXDF18
UART3_RXDE18
UART3_TXDD18
R14 4.7K
Q1
NX3008NBKW,115
1
23
R10 4.7K
ENET_MDCENET_MDIO
QSPIA_SCLK
QSPIA_nSS0
SD1_CMDSD1_CLK
SD1_DATA0SD1_DATA1SD1_DATA2SD1_DATA3
SAI5_MCLK
SAI5_RXFSPDM_CLK
SAI3_MCLK
SAI3_TXFSSAI3_TXCSAI3_TXD
SAI3_RXFSSAI3_RXCSAI3_RXD
SPDIF_TX
SPDIF_EXT_CLKSPDIF_RX
ENET_TD0ENET_TXCENET_TX_CTL
ENET_TD1ENET_TD2ENET_TD3
ENET_RX_CTLENET_RXC
SD2_CMDSD2_CLK
SD2_DATA0SD2_DATA1SD2_DATA2SD2_DATA3
SD2_nRSTSD2_nCDSD2_WP
SAI1_MCLK
SAI1_TXFSSAI1_TXC
SAI1_RXD0
SAI1_RXD2SAI1_RXD3SAI1_RXD4
SAI1_RXD1
SAI1_RXD5SAI1_RXD6SAI1_RXD7
SAI1_TXD0
SAI1_TXD2SAI1_TXD3
SAI1_TXD1
SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7
SAI1_RXCSAI1_RXFS
SAI2_MCLK
SAI2_TXFSSAI2_TXCSAI2_TXD
SAI2_RXFSSAI2_RXCSAI2_RXD
I2C1_SDAI2C1_SCL
I2C2_SCLI2C2_SDA
I2C3_SCLI2C3_SDA
I2C4_SCLI2C4_SDA
ENET_RD0
ENET_RD2ENET_RD1
ENET_RD3
UART1_RXDUART1_TXD
UART2_RXDUART2_TXD
UART4_RXDUART4_TXD
I2C1_SDAI2C1_SCL
I2C2_SCLI2C2_SDA
I2C3_SCLI2C3_SDA
I2C4_SCLI2C4_SDA
REF_CLK_32KGPIO1_IO01WDOG_BPMIC_nINTSD2_VSELGPIO1_IO05GPIO1_IO06GPIO1_IO07GPIO1_IO08GPIO1_IO09GPIO1_IO10GPIO1_IO11GPIO1_IO12GPIO1_IO13GPIO1_IO14GPIO1_IO15
SD3_CMDSD3_CLK
SD3_STROBE
SD3_DATA4
SD3_DATA5SD3_DATA6
SD3_DATA7
BT_WAKE_DEVBT_WAKE_HOST
BT_REG_ON
WL_WAKE_HOST
WL_REG_ON
SD3_DATA0SD3_DATA1SD3_DATA2SD3_DATA3
QSPIA_DATA1QSPIA_DATA2QSPIA_DATA3
QSPIA_DATA0
ECSPI2_SS0ECSPI2_MOSIECSPI2_MISOECSPI2_SCLK
UART3_RXD
UART3_TXDUART3_RTS
UART3_CTS
SD1_STROBE
UART1_RTSUART1_CTS
SYS_STATUS
PDM_DATA0PDM_DATA1PDM_DATA2PDM_DATA3
SD2_DATA0
SD2_CMD
SYS_STATUS
SD2_nRST
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
i.MX8M Mini PHYs
Voltage Range:0~3.3V
Voltage Range:0~3.3V
GND
GND
USB1_VBUS
GND
GND
USB2_VBUS
GND
PCIE_RXN 13PCIE_RXP 13
CSI_DN0 13CSI_DP0 13
DSI_CKN 13DSI_CKP 13
DSI_DN0 13DSI_DP0 13
DSI_DN1 13DSI_DP1 13
DSI_DN2 13DSI_DP2 13
DSI_DN3 13DSI_DP3 13
USB1_DN 13USB1_DP 13
USB1_ID 13
CSI_DP1 13CSI_DN1 13
CSI_DN2 13CSI_DP2 13
CSI_DP3 13CSI_DN3 13
USB2_DN 13USB2_DP 13
USB2_ID 13
CSI_CKN 13CSI_CKP 13
PCIE_TXN 13PCIE_TXP 13
PCIE_CLKN 13PCIE_CLKP 13
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, January 07, 2019
CPU PHY
Frank Liu
<Approver>
Frank Liu
7 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, January 07, 2019
CPU PHY
Frank Liu
<Approver>
Frank Liu
7 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, January 07, 2019
CPU PHY
Frank Liu
<Approver>
Frank Liu
7 13
____X____
i.MX8M Mini - CSI
VDD_MIPI_1P8
MIMX8MM6DVTLZAA
U1E
MIPI_CSI_CLK_PB16
MIPI_CSI_D3_PB18
MIPI_CSI_CLK_NA16
MIPI_CSI_D3_NA18
MIPI_CSI_D2_PB17
MIPI_CSI_D0_PB14
MIPI_CSI_D1_PB15
MIPI_CSI_D2_NA17
MIPI_CSI_D0_NA14
MIPI_CSI_D1_NA15
R28 8.2K 1%
C3930.22UF10V0201_CC
C3940.22UF10V0201_CC
R29 200 1%
R108 30K 1%
R109 30K 1%
i.MX8M Mini - PCIe
VDD_PCI_1P8
MIMX8MM6DVTLZAA
U1C
PCIE_RXN_PB19PCIE_RXN_NA19
PCIE_CLK_NA21
PCIE_CLK_PB21
PCIE_TXN_NA20
PCIE_TXN_PB20
PCIE_RESREFD19
i.MX8M Mini - USB
VDD_USB_3P3
VDD_USB_1P8
VDD_USB_1P8
VDD_USB_3P3
MIMX8MM6DVTLZAA
U1B
USB1_DNA22
USB2_DNA23
USB2_TXRTUNEE22
USB1_TXRTUNEE19
USB2_DPB23
USB1_IDD22
USB2_VBUSF23
USB2_IDD23
USB1_DPB22
USB1_VBUSF22
i.MX8M Mini - DSI
VDD_MIPI_1P8
MIMX8MM6DVTLZAA
U1D
MIPI_DSI_CLK_PB11MIPI_DSI_CLK_NA11
MIPI_DSI_D2_PB12
MIPI_DSI_D0_PB9
MIPI_DSI_D1_PB10
MIPI_DSI_D3_PB13
MIPI_DSI_D2_NA12
MIPI_DSI_D0_NA9
MIPI_DSI_D1_NA10
MIPI_DSI_D3_NA13
R30 200 1%
CSI_CKP
CSI_DN0CSI_DP0
CSI_CKN
PCIE_RXPPCIE_RXN
DSI_CKP
DSI_DN0DSI_DP0
DSI_DN1DSI_DP1
DSI_CKN
DSI_DN2DSI_DP2
DSI_DN3DSI_DP3
USB1_DNUSB1_DP
USB1_ID
CSI_DN1CSI_DP1
CSI_DN2CSI_DP2
CSI_DN3CSI_DP3
USB2_DNUSB2_DP
USB2_ID
PCIE_TXPPCIE_TXN
PCIE_CLKNPCIE_CLKP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
JTAG Debug
PU
PU
PU
PU
PU
Recommend to use external clock source, XTALO must be connected to NVCC_SNVS_1V8/2, or VDD_SNVS_0V8!
# System On/Off Button
PD
Factory use only
PU
PD
Refer to datasheet
Signal Naming:
I.MX8M Mini I.MX8M NanoNet Name
TEST_MODE TEST_MODE BOOT_MODE3BOOT_MODE2JTAG_nTRSTJTAG_nTRST
Note:
BOOT_MODE2(JTAG_nTRST) must be pull UP on BB for i.MX8M Mini;BOOT_MODE3 must be pull down on BB for i.MX8M Mini;
GND
GND
GND
GND
NVCC_SNVS_1V8
GND
VDD_SNVS_0V8
BOOT_MODE0 11,13BOOT_MODE1 11,13
CLKOUT1 13CLKOUT2 13
CLK_32K_OUT12
ONOFF13
POR_B12,13
PMIC_ON_REQ12,13
PMIC_STBY_REQ12
JTAG_TCK 13JTAG_TMS 13JTAG_TDI 13
JTAG_nTRST 13JTAG_TDO 13
RTC_RESET_B12
CLKIN1 13CLKIN2 13
TEST_MODE 13
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
A4
Monday, January 07, 2019
CPU MISC
Frank Liu
<Approver>
Frank Liu
8 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
A4
Monday, January 07, 2019
CPU MISC
Frank Liu
<Approver>
Frank Liu
8 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
A4
Monday, January 07, 2019
CPU MISC
Frank Liu
<Approver>
Frank Liu
8 13
____X____
TP19
TP6
R135 100K
TP20
TP10
i.MX8M Mini - MISC
NVCC_SNVS_1P8
NVCC_JTAG
VDD_24M_XTAL_1P8 N
VCC_CLK
VDD_ANA1_1P8
MIMX8MM6DVTLZAA
U1L
BOOT_MODE0G26
JTAG_TDIE27
ONOFFA25
POR_BB24
RTC_RESET_BF24 TEST_MODE
D26
BOOT_MODE1G27
JTAG_TMSF27
RTC_XTALIA26
RTC_XTALOB25
PMIC_STBY_REQE24
PMIC_ON_REQA24
JTAG_MODD27JTAG_TRST_BC27JTAG_TDOE26
24M_XTALIB27
24M_XTALOC26
CLKOUT2J26
JTAG_TCKF26
CLKIN2J27
CLKOUT1H26
CLKIN1H27
TSENSOR_RES_EXTJ24
TSENSOR_TEST_OUTJ23
TP21
TP38
TP1TP2TP3TP4
R21100K
TP5TP8
R103 100K 1%
R20100K
R134 0
R102100K
R23 10K
R113 0
R26 510K
TP9
C12312pF25V0201_CC
Y1
24MHZ
14
3 2
R100 0
C12412pF25V0201_CC
TP7
R1810K
TP39
JTAG_TCK
JTAG_TDIJTAG_TMS
JTAG_TDO
XTALO_24M
BOOT_MODE0BOOT_MODE1
TESTMODE
CLKIN2
JTAG_TDIJTAG_TDO
JTAG_TCKJTAG_TMS
JTAG_MODJTAG_nTRST
CLKOUT2CLKOUT1
CLKIN1
ONOFF
POR_B
RTC_RESET_B
PMIC_ON_REQ
TS_RES_EXT
TS_TEST_OUTXTALO_32K
XTALI_32K
XTALI_24M
PMIC_STBY_REQ
JTAG_nTRST
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
eMMC
QSPI Flash
# 1.8V(Fixed)
Storage
16GB
32MBGND
GND
VDD_1V8VDD_1V8
GND
GND
GND
GND
VDD_3V3
VDD_1V8
VDD_1V8
QSPIA_nSS06
QSPIA_SCLK6
SD3_DATA06
SD3_CLK6
SD3_CMD6
QSPIA_DATA06 QSPIA_DATA1 6
QSPIA_DATA26
QSPIA_DATA36
SD3_DATA16SD3_DATA26SD3_DATA36SD3_DATA46SD3_DATA56SD3_DATA66SD3_DATA76
SD3_STROBE 6
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, February 11, 2019
eMMC/QSPI
Frank Liu
<Approver>
Frank Liu
9 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, February 11, 2019
eMMC/QSPI
Frank Liu
<Approver>
Frank Liu
9 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, February 11, 2019
eMMC/QSPI
Frank Liu
<Approver>
Frank Liu
9 13
____X____
C1274.7uF10V0402_CC
C1290.22UF10V0201_CC
TP40
C1310.22UF10V0201_CC
TP34
C1280.22UF10V0201_CC
C1371uF6.3V0201_CC
TP35
TP16
C1320.22UF10V0201_CC
C1380.22UF10V0201_CC
C1330.22UF10V0201_CC
eMMC16GB
U4A
SDINBDG4-16G-I1
CLKM6
CMDM5
RSTK5
VDDIC2
VCCQ1C6
VCCQ5P5
VCCQ2M4
VCCQ4P3VCCQ3N4
VC
C3
J1
0V
CC
2F
5V
CC
1E
6
VC
C4
K9
VS
S2
E7
VS
S3
G5
VS
S4
H1
0
VS
S6
K8
VSSQ2N2
VSSQ3N5
VSSQ4P4
VSSQ5P6
VSSQ1C4DAT7
B6 DAT6B5 DAT5B4 DAT4B3 DAT3B2 DAT2A5 DAT1A4 DAT0A3
VS
S1
A6
VS
S5
J5
RCLKH5
U4B
SDINBDG4-16G-I1
NC_A1A1
NC_A2A2
NC_A8A8
NC_A9A9
NC_A10A10
NC_A11A11
NC_A12A12
NC_A13A13
NC_A14A14
NC_B1B1
NC_B7B7
NC_B8B8
NC_B9B9
NC_B10B10
NC_B11B11
NC_B12B12
NC_B13B13
NC_B14B14
NC_C1C1
NC_C3C3
NC_C7C7
NC_C8C8
NC_C9C9
NC_C10C10
NC_C11C11
NC_C12C12
NC_C13C13
NC_C14C14
NC_D1D1
NC_D2D2
NC_D3D3
NC_D4D4
NC_D12D12
NC_D13D13
NC_D14D14
NC
_E
1E
1
NC
_E
2E
2
NC
_E
3E
3
NC
_E
12
E1
2
NC
_E
13
E1
3
NC
_E
14
E1
4
NC
_F
1F
1
NC
_F
2F
2
NC
_F
3F
3
NC
_F
12
F1
2
NC
_F
13
F1
3
NC
_F
14
F1
4
NC
_G
1G
1
NC
_G
2G
2
NC
_G
12
G1
2
NC
_G
13
G1
3
NC
_G
14
G1
4
NC
_H
1H
1
NC
_H
2H
2
NC
_H
3H
3
NC
_H
12
H1
2
NC
_H
13
H1
3
NC
_H
14
H1
4
NC
_J1
J1
NC
_J2
J2
NC
_J3
J3
NC
_J1
2J1
2
NC
_J1
3J1
3
NC
_J1
4J1
4
NC_K1K1NC_K2K2NC_K3K3
NC_K12K12NC_K13K13NC_K14K14NC_L1L1NC_L2L2NC_L3L3NC_L12L12NC_L13L13NC_L14L14NC_M1M1NC_M2M2
NC
_E
8E
8
VS
F1
E9
VS
F2
E1
0
NC
_E
5E
5
VS
F3
F1
0
NC
_G
3G
3
NC
_G
10
G1
0
NC_A7A7
NC_C5C5
NC_K6K6
VS
F4
K1
0
NC_K7K7
NC
_P
10
P1
0
NC
_P
7P
7
NC
_P
14
P1
4N
C_
P1
3P
13
NC
_P
12
P1
2N
C_
P1
1P
11
NC
_P
9P
9N
C_
P8
P8
NC
_P
2P
2N
C_
P1
P1
NC_N14N14
NC_N13N13
NC_N12N12
NC_N11N11
NC_N10N10
NC_N9N9
NC_N8N8
NC_N7N7
NC_N6N6
NC_N3N3
NC_N1N1
NC_M14M14
NC_M13M13
NC_M12M12
NC_M11M11
NC_M10M10
NC_M9M9
NC_M8M8
NC_M7M7
NC_M3M3
TP17
R11810KDNP
R11710KDNP
C1360.22UF10V0201_CC
R3710K
C13910uF6.3V0402_CC
U5
MT25QU256ABA1EW7-0SIT
S1
DQ12
W/DQ23
VS
S4
DQ05
C6
HOLD/DQ37
VC
C8
EP
9
C13010uF6.3V0402_CC
TP18
TP36
eMMC_VDDIM
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout: Route the Antenna signals as 50 ohm.
Antenna 2.4G/5G
MatchingCircuit
oi
io
i
od
i
od
i
Configure internal pull up at CPU side
Configure internal pull up at CPU side
QCA9377 Based
# 1.8V(Fixed)
2.4G/5G WIFI/BT Module
To support WIFI wakeup function,VDD_3V3 and VDD_1V8 must be 'ON'.
VDD_3P3
VDDIO_SDIO/VDDIO_AO/VDDIO_XTAL/VDDIO_GPIO1/VDDIO_GPIO23.3V
1.8V
Power Sequence
GND GND
GND
GND
GND
GND
VDD_3V3 VDD_1V8
VDD_1V8
VDD_3V3
GND
WIFI_1V1
UART1_RTS 6UART1_CTS 6
UART1_RXD 6UART1_TXD 6
WL_REG_ON 6
BT_REG_ON 6
WL_WAKE_HOST 6
BT_WAKE_HOST6
REF_CLK_32K6,13
SD1_DATA1 6SD1_DATA2 6
SD1_DATA0 6
SD1_DATA3 6
SD1_CMD 6SD1_CLK 6
BT_WAKE_DEV 6
SAI2_TXD 6SAI2_TXFS 6SAI2_TXC 6
SAI2_RXD 6
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, January 07, 2019
WIFI/BT Module
Frank Liu
<Approver>
Frank Liu
10 13
____A____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, January 07, 2019
WIFI/BT Module
Frank Liu
<Approver>
Frank Liu
10 13
____A____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Monday, January 07, 2019
WIFI/BT Module
Frank Liu
<Approver>
Frank Liu
10 13
____A____
R130 0
TP50
R115 0
L2
1.5uH
1 2
TP48
TP11
L32.2nHDNP0402_CC
12
C14047uF6.3V0805_CC
R131 0
C1450.1uF10V0201_CC
C1460.1uF10V0201_CC
R132 0
C1430.1uF10V0201_CC
C1411uF6.3V0201_CC
TP13
TP14
C1480.1uF10V0201_CC
C14222uF10V0603_CC
J2
MXC3N2001
12
3
C1441uF6.3V0201_CC
GPIO1
SDIO
GPIO2
Alwayon
LBEE5KL1PJ
U6
2G_WIFI/BT_RF_OUT20
ANT24
WLAN_EN39
HCI_UART_WAKEHOST17
BT_EN40
32KHz_CLK_IN15
PCM_OUT34
PCM_CLK31
PCM_IN33
3D_FRAME_SYNC26
SDIO_CLK11
SDIO_DATA36
HCI_UART_CTS30
HCI_UART_TXD28
HCI_UART_RXD27
HCI_UART_RTS29
SDIO_DATA27SDIO_DATA18SDIO_DATA09SDIO_CMD10
VD
DIO
_S
DIO
12
VD
D_
3P
34
1
GN
D1
1
GN
D3
14
GN
D4
19
GN
D5
21
GN
D6
23
GN
D7
25
GN
D8
35
GN
D9
38
GN
D1
04
3
GN
D1
15
0
GN
D1
25
1
GN
D2
5
GN
D1
35
2
GN
D1
45
3
GN
D1
55
4
GN
D1
65
5
GN
D1
75
6
GN
D1
85
7
GN
D1
95
8
GN
D2
05
9
GN
D2
16
0
GN
D2
26
1
GN
D2
36
2
SDIO_INTERRUPT_L13
VB
UC
K_
GN
D_
PM
2
PW
M_
PM
3
VD
D1
1_
PM
4
VD
DIO
_G
PIO
21
6
VD
DIO
_G
PIO
13
7
WLAN_RF_KILL_L18
2G_WIFI/BT_RF_IN22
PCM_SYNC32
VD
DIO
_X
TA
L3
6
VD
DIO
_A
O4
2
LTE_UART_TXD45
LTE_UART_RXD44
CLK_REQ46
DBG_UART_TXD47
DBG_UART_RXD48
QOW49
TP12
TP49
R129 0
C1470.1uF10V0201_CC
R44 0
L41.3nHDNP0402_CC
12
REF_CLK_32K
ANT_IN0RF_ANT0
BT_RXDBT_TXD
BT_CTSBT_RTS
WL_REG_ON
BT_REG_ON
WL_WAKE_HOST
BT_WAKE_HOST
2G_RF_FILTER
SD1_DATA0
SD1_CLKSD1_CMD
SD1_DATA1SD1_DATA2SD1_DATA3
32K_CLKIN SAI2_TXFSSAI2_TXD
SAI2_TXC
SAI2_RXD
BT_WAKE_DEV
SAI2_TXFS_RESSAI2_TXD_RES
SAI2_TXC_RES
SAI2_RXD_RES
PWM_1V1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
i.MX8M Mini ROM Fuse
Boot Mode and CFG Switch
BT_CFG Pins:
1. Bootcfg/SAI1 singals have internal PD before and after POR_B reset is deasserted!
Note:
2. Standalone SOM board can support eMMC/SDHC3 boot, by populating R71, R72, R75, R76, R79, R95, R97!
BOOT_CFG0
3. When using Base Board for Multi boot selection, you must keep the resistors DNP on SOM board!
USDHC IO VOLTAGESELECTION For Manufacture Mode0 - 3.3V1 - 1.8V
SD Loopback ClockSource Sel (for SDR50and SDR104 only)'0' - through SD pad'1' - direct
BOOT_CFG[14]BOOT_CFG[15] BOOT_CFG[13] BOOT_CFG[12] BOOT_CFG[11] BOOT_CFG[10] BOOT_CFG[9] BOOT_CFG[8]0x470[15:8]
4 3 2 07 6 5 1Address
Power Cycle Enable'0' - No power cycle'1' - Enabled via
Port Select:00 - uSDHC101 - uSDHC210 - uSDHC3
001 - SD/eSD
010 - MMC/eMMC
Infinit-Loop(Debug USE only)0 - Disable1 - Enable
011 - NAND
100 - QSPI
110 - SPI NOR
Pages In Block:00 - 12801 - 6410 - 3211 - 256
Nand_Row_address_bytes:00 - 301 - 210 - 411 - 5
FLASH_TYPE000-Device supports 3B read by default001-Device supports 4B read by default010-HyperFlash 1V8011-HyperFlash 3V3100-MXIC Octal DDR
Port Select:000 - eCSPI1001 - eCSPI2010 - eCSPI3
SPI Addressing:0 - 3-bytes (24-bit)1 - 2-bytes (16-bit)
0x470[15:8]
0x470[15:8]
0x470[15:8]
0x470[15:8]
0x470[15:8]
Others - Reserved for future use0x470[15:8]
Reserved
BOOT_CFG[6]BOOT_CFG[7] BOOT_CFG[5] BOOT_CFG[4] BOOT_CFG[3] BOOT_CFG[2] BOOT_CFG[1] BOOT_CFG[0]
Speed000 - Normal/SDR12001 - High/SDR25010 - SDR50011 - SDR104101 - Reserved for DDR50Others - Reserved
Bus Width:0 - 1-bit1 - 4-bit
Fast Boot:0 - Regular1 - Fast Boot
Bus Width:000 - 1-bit001 - 4-bit010 - 8-bit101 - 4-bit DDR (MMC 4.4)110 - 8-bit DDR (MMC 4.4)Else - reserved.
BOOT_SEARCH_COUNT:00 - 201 - 210 - 411 - 8
USDHC IO VOLTAGESELECTION For Normal Boot Mode0 - 3.3V1 - 1.8V
Toggle Mode 33MHz Preamble Delay, Read Latency:'000' - 16 GPMICLK cycles.'001' - 1 GPMICLK cycles.'010' - 2 GPMICLK cycles.'011' - 3 GPMICLK cycles.'100' - 4 GPMICLK cycles.'101' - 5 GPMICLK cycles.'110' - 6 GPMICLK cycles.'111' - 7 GPMICLK cycles.'1111'- 15 GPMICLK cycles.
Reserved
0x470[7:0]
0x470[7:0]
0x470[7:0]
0x470[7:0]
0x470[7:0]
Reserved Reserved
Speed00 - Normal01 - High10 - Reserved for HS20011 - Reserved
BT_TOGGLEMODE
HOLD TIME:00 - 500us01 - 1ms10 - 3ms11 - 10ms
FlexSPI FLASH Dummy Cycle
Reserved Reserved Reserved Reserved Reserved Reserved
SD/eSD
MMC/eMMC
NAND
FlexSPI
SPINOR Reserved
CS select SPI only:00 - CS#0 default01 - CS#110 - CS#211 - CS#3
FLASH Auto Probe Type
Flash Auto Probe
BOOT_CFG1
SAI1_RXD0
BOOT_CFG1SAI1_RXD1
SAI1_RXD2 BOOT_CFG2
BOOT_CFG3SAI1_RXD3
SAI1_RXD4 BOOT_CFG4
BOOT_CFG5SAI1_RXD5
BOOT_CFG6SAI1_RXD6
SAI1_RXD7 BOOT_CFG7
BOOT_CFG8SAI1_RXD8
SAI1_RXD9 BOOT_CFG9
BOOT_CFG10SAI1_RXD10
SAI1_RXD11 BOOT_CFG11
BOOT_CFG12SAI1_RXD12
BOOT_CFG13SAI1_RXD13
SAI1_RXD14 BOOT_CFG14
BOOT_CFG15SAI1_RXD15
BOOT_CFG2
BOOT_CFG11
BOOT_CFG5BOOT_CFG6
BOOT_CFG13
BOOT_MODE0BOOT_MODE1
00
01
10
11
Boot From Fuses
Serial Downloader
Internal Boot (Development)
Reserved
BOOT TYPE:
Boot Mode
IO internal pull up/down is not supported in 3.3V mode, must disable the internal pull up/downvia software and use external pull up/down resistors instead.All IO pin groups are impacted except for XTAL, DDR, PCI, USB and MIPI PHY IO's.See Errata e50080 for detailed information.
Caution:
NVCC_3V3NVCC_1V8
SAI1_RXD1 6,13SAI1_RXD2 6,13SAI1_RXD5 6,13SAI1_RXD6 6,13SAI1_TXD3 6,13SAI1_TXD5 6,13
BOOT_MODE0 8,13BOOT_MODE1 8,13
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Friday, January 25, 2019
BOOT_CFG
Frank Liu
<Approver>
Frank Liu
11 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Friday, January 25, 2019
BOOT_CFG
Frank Liu
<Approver>
Frank Liu
11 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Friday, January 25, 2019
BOOT_CFG
Frank Liu
<Approver>
Frank Liu
11 13
____X____
R71
10K
DN
P
R72
10K
DN
P
R76
10K
DN
P
R95
10K
DN
P
R79
10K
DN
P
R75
10K
DN
P
R47
10K
DN
P
R97
10K
DN
P
BOOT_MODE0BOOT_MODE1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0.85V 3A
0.85/0.95/1.0V 3A
0.975V 3A
3.3V 3A
1.8V 1.5A
1.1V 3A
OD
OD
OD # System Reset Button
# CPU WDOG_B Reset
1.8V 300mA
1.8V 10mA
0.8V 10mA
3.3V/1.8V 150mA
1.2V 300mA
0.9V 250mA
i.MX8M Mini LPDDR4 EVK Power Sequence
1010----300030002503000300150030003000150300--
TYP Max Current(mA)PWR/SignalSEQ
1234566778910101112
LDO1LDO2RTC_RESET_BRTC_CLKBUCK1BUCK5LDO4BUCK2LDO3BUCK7BUCK8BUCK6MUXSWLDO6POR_B
REG MIN
1.620.76----0.78/0.8050.805/0.8550.8550.805/0.9/0.951.711.651.0633.0/1.651.14--
MAX
1.980.9----0.90.9/1.01.00.95/1.0/1.051.891.951.143.63.6/1.951.26--
GND Testpoints
SYS PMIC
Backup PWR Supply
1. PWRON is used as RESET Button as default, need to configure PWRON long push as 10ms, Cold Reset, and short push detect should be disabled !
Note:
2. WDOG_B is used as Cold Reset, external pull up is needed. On EVK, R106 is not necessary, since WDOG_B/GPIO1_IO02 of CPU has internal pull up.
>20uF for SW6 Input
NVCC_SNVS_1V8VDD_SNVS_0V8RTC_RESET_BCLK_32K_OUTVDD_SOC_0V8VDD_DRAM&PU_0V9VDD_PHY_0V9VDD_ARM_0V9VDDA_1V8VDD_1V8/NVCC_1V8NVCC_DRAM_1V1VDD_3V3/NVCC_3V3NVCC_SD2VDD_PHY_1V2POR_B
1.80.8----0.82/0.850.85/0.950.90.85/0.95/1.01.81.81.13.33.3/1.81.2--
BUCK1 default output voltage is 0.8V. Software will change it to 0.85V in SPL before DDR initialization.
Note:
BUCK5 default output voltage is 0.9V. Software will change it to 0.975V(BD71847 BUCK5 doesn't support 0.95V output) in SPL before DDR initialization.BUCK2 default output voltage is 0.9V. Software will change it to 0.85V for 1.2GHz operation, 0.95V for 1.6GHz, 1.0V for 1.8GHz.
VSYS_5V
GND
GND
GND
VDD_3V3
GND
GND
VDD_1V8
GND
GND
GND
VSYS_5V
VDD_1V8
NVCC_DRAM_1V1
VDD_3V3
VDD_1V8
NVCC_SNVS_1V8
GNDGND
GND
NVCC_SNVS_1V8
VDD_SOC_0V8
VDD_DRAM&PU_0V9
VDD_ARM_0V9
VDD_1V8
GND
VDDA_1V8
VDD_SNVS_0V8
NVCC_SNVS_1V8
NVCC_SD2
GND
GND
GND
GND
GND
GND
GND
VDD_PHY_1V2
GND
GND
VDD_PHY_0V9
GND
VSYS_5V
VDD_SOC_0V8
VDD_ARM_0V9
VDD_DRAM&PU_0V9
NVCC_DRAM_1V1
GND
POR_B 8,13
PMIC_nINT 6
I2C1_SDA6
I2C1_SCL6
WDOG_B6
PMIC_ON_REQ8,13
PMIC_STBY_REQ8
CLK_32K_OUT 8
RTC_RESET_B 8
SD2_VSEL6
SYS_nRST13
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
PMIC
Frank Liu
<Approver>
Frank Liu
12 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
PMIC
Frank Liu
<Approver>
Frank Liu
12 13
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
C
Monday, February 11, 2019
PMIC
Frank Liu
<Approver>
Frank Liu
12 13
____X____
L11
1uH1 2
QZ2
32.768KHZ
12
C316 10uF0603_CC16V
C27522uF10V0603_CC
C333 1uF6.3V 0201_CC
TP23
TP27
L13
0.47uH1 2
TP32
C306 10uF0603_CC16V
C272 1uF6.3V 0201_CC
R51 0
C337 1uF6.3V 0201_CC
C323 10uF0603_CC16V
TP30
R57 1MDNP
U8B
BD71847MWV
LDO1_VOUT10
VSYS_29
LDO2_VOUT8
VIN_1P8_143
VSYS_341
LDO6_VOUT44
VSYS_15
VIN_3P3_27
LDO3_VOUT6
LDO5_VOUT4
VIN_1P8_256
MUXSW_VOUT55
SD_VSELECT45
LDO4_VOUT42
VIN_3P3_11
TP24
TP28
TP33
J6
HDR 1X2 THDNP
12
L6
0.47uH1 2
R48 0
C360 4.7uF10V 0402_CC
C29918pF50V0201_CC
C279 10uF0603_CC16V
C30322uF10V0603_CC
R111 0R61 100K
R52 0
C307 10uF0603_CC16V
C363 4.7uF10V 0402_CC
R54 0
TP22
C30422uF10V0603_CC
C281 10uF0603_CC16V
TP25
TP29
C273 1uF6.3V 0201_CC
C112.2uF16V0402_CC
TP52
C14 4.7uF10V 0402_CC
TP44
C31122uF10V0603_CC
R114 0
C31822uF10V0603_CC
R127 0
C32422uF10V0603_CC
C351 4.7uF10V 0402_CC
C29818pF50V0201_CC
TP45
C102.2uF16V0402_CC
C31222uF10V0603_CC
C31722uF10V0603_CC
C32522uF10V0603_CC
TP47
TP53
U8C
BD71847MWV
INT
LD
O1P
511
AG
ND
12
XIN14
XOUT13
DV
DD
28
SCL26
SDA27
C32K_OUT29
IRQ39
POR25
RTC_RESET3
WDOG2
PMIC_ON_REQ15
PMIC_STBY_REQ16
PWRON40
PG
ND
157
PG
ND
258
PG
ND
359
PG
ND
460
PG
ND
561
R106 100KDNP
C28322uF10V0603_CC
C295 10uF0603_CC16V
U8A
BD71847MWV
BUCK1_VIN18
BUCK1_LX_119
BUCK1_LX_220
BUCK1_FB17
BUCK2_LX_121
BUCK2_LX_222
BUCK2_FB24
BUCK2_VIN23
BUCK5_VIN_131
BUCK5_VIN_232 BUCK5_LX_1
33
BUCK5_LX_234
BUCK5_FB30
BUCK6_VIN_147
BUCK6_VIN_248 BUCK6_LX_1
49
BUCK6_LX_250
BUCK6_FB46
BUCK7_VIN53
BUCK7_LX_151
BUCK7_FB54
BUCK8_VIN37
BUCK8_LX_135
BUCK8_LX_236
BUCK8_FB38
BUCK7_LX_252
C122.2uF16V0402_CC
TP26
TP46
R55 0
C13 4.7uF10V 0402_CC
C28722uF10V0603_CC
C365 10uF10V 0603_CC
C301 10uF0603_CC16V
L5
0.47uH1 2
TP31
C28522uF10V0603_CC
L10
0.47uH1 2
L15
0.47uH1 2
C18 4.7uF10V 0402_CC
INTLDO_1V5
XIN_32K
XOUT_32K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
When using M.2 WIFI Module, remove R115, populate R116!
A53 Debug
M4 Debug
Header Receptacle
B2B Connector for CPU Board
Receptacle
IO internal pull up/down is not supported in 3.3V mode, must disable the internal pull up/downvia software and use external pull up/down resistors instead.All IO pin groups are impacted except for XTAL, DDR, PCI, USB and MIPI PHY IO's.See Errata e50080 for detailed information.
Caution:
GND
USB1_VBUS
USB2_VBUS
GND
VSYS_5V VSYS_5V
GNDGND
GND GND GND
VDD_1V8VDD_3V3
GNDGNDGND
NVCC_ENET
VSYS_5V
GND
VDD_3V3
GND
VDD_1V8
GND
I2C2_SDA6
USB1_DN 7USB1_DP 7
USB2_DN 7USB2_DP 7
PCIE_RXN 7PCIE_RXP 7
PCIE_TXN 7PCIE_TXP 7
REF_CLK_32K6,10
JTAG_nTRST8JTAG_TMS8
JTAG_TCK8
DSI_DN0 7DSI_DP0 7
DSI_DP1 7DSI_DN1 7
DSI_DN2 7DSI_DP2 7
DSI_DP3 7DSI_DN3 7
DSI_CKN 7DSI_CKP 7
CSI_DN0 7CSI_DP0 7
CSI_CKP 7CSI_CKN 7
CSI_DP1 7CSI_DN1 7
CSI_DP2 7CSI_DN2 7
CSI_DP3 7CSI_DN3 7
USB1_ID 7
USB2_ID 7
UART3_RTS6UART3_RXD6
UART3_CTS6
ECSPI2_MISO6
ECSPI2_SS06ECSPI2_SCLK6
I2C2_SCL6
CLKOUT18
UART3_TXD6
ECSPI2_MOSI6
CLKOUT28
I2C3_SCL6
I2C4_SCL6I2C3_SDA6
UART2_RXD6UART2_TXD6
I2C4_SDA6
UART4_TXD6UART4_RXD6
JTAG_TDO8
ONOFF8PMIC_ON_REQ8,12
POR_B8,12
JTAG_TDI8
SD1_STROBE6SD2_DATA26
SD2_CLK6SD2_DATA36
SD2_CMD6
SD2_DATA06
SD2_nCD6SD2_WP6
SD2_DATA16
SD2_nRST6
CLKIN18CLKIN28
BOOT_MODE08,11BOOT_MODE18,11
GPIO1_IO01 6GPIO1_IO05 6
GPIO1_IO08 6GPIO1_IO09 6GPIO1_IO10 6
SAI2_MCLK 6SAI2_RXFS 6SAI5_RXFS 6
GPIO1_IO11 6GPIO1_IO12 6GPIO1_IO13 6GPIO1_IO14 6GPIO1_IO15 6
GPIO1_IO06 6GPIO1_IO07 6
SAI1_RXD0 6SAI1_RXD1 6,11SAI1_RXD2 6,11
SAI1_RXC 6SAI1_RXFS 6
SAI1_RXD6 6,11
SAI1_RXD3 6SAI1_RXD4 6SAI1_RXD5 6,11
SAI1_RXD7 6
SAI1_MCLK 6SAI1_TXFS 6
SAI3_TXFS6SAI3_TXC6
SAI3_MCLK6SYS_nRST12
SAI3_RXC6SAI3_RXFS6SAI3_TXD6
SPDIF_TX6SAI3_RXD6
SPDIF_RX6
SPDIF_EXT_CLK6
PDM_DATA06PDM_DATA16
PDM_CLK6
PDM_DATA36
SAI5_MCLK6
PDM_DATA26
SAI2_RXC6
SAI1_TXD06SAI1_TXD16
SAI1_TXC6
SAI1_TXD36,11
SAI1_TXD26
SAI1_TXD46SAI1_TXD56,11SAI1_TXD66SAI1_TXD76
ENET_RXC 6
ENET_RD2 6
ENET_RX_CTL 6
ENET_RD1 6ENET_RD0 6
ENET_RD3 6
ENET_MDIO 6ENET_MDC 6
ENET_TXC6
ENET_TX_CTL6
ENET_TD06
ENET_TD26ENET_TD16
ENET_TD36
PCIE_CLKN 7PCIE_CLKP 7
TEST_MODE8
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Friday, January 25, 2019
SOM Interface
Frank Liu
<Approver>
Frank Liu
13 13
____A____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Friday, January 25, 2019
SOM Interface
Frank Liu
<Approver>
Frank Liu
13 13
____A____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-31399 PDF: SPF-31399 C2
8MMINILPD4-CPU
B
Friday, January 25, 2019
SOM Interface
Frank Liu
<Approver>
Frank Liu
13 13
____A____
BH2
C40210uF
0603_CC16V
J5
DF40C-100DS-0.4V(51)
24681012141618202224262830323436384042444648505254565860
13579
1113151719212325272931333537394143454749515355575961 62
64636567
6668
69 7072
73 7475 7677 7879 80
71
81 8283 8485 8687 8889 9091 9293 9495 9697 9899 100
C22.2uF10V0402_CC
J4
DF40C-100DP-0.4V(51)
2468
1012141618202224262830323436384042444648505254565860
13579111315171921232527293133353739414345474951535557596162
64 636567
6668
697072
7374757677787980
71
81828384858687888990919293949596979899100
C40322uF10V0603_CC
J7
DF40C-20DS-0.4V(51)
1 23 4
657 89 10
11 1213 1415 1617 1819 20
BH3
C40110uF
0603_CC16V
TP51
C40422uF10V0603_CC
BH1
R116 0DNP
DSI_CKPDSI_CKN
DSI_DN2DSI_DP2
DSI_DN3DSI_DP3
DSI_DN0DSI_DP0
DSI_DN1DSI_DP1
CSI_DN2CSI_DP2
CSI_DN3CSI_DP3
CSI_CKPCSI_CKN
CSI_DN1CSI_DP1
CSI_DN0CSI_DP0
PCIE_RXPPCIE_RXN
USB1_DNUSB1_DP
USB2_DNUSB2_DP
USB1_ID
USB2_ID
I2C2_SCLI2C2_SDA
PCIE_TXPPCIE_TXN
PCIE_CLKPPCIE_CLKN
ECSPI2_MISOECSPI2_SCLKECSPI2_SS0UART3_CTS
UART3_RTSUART3_RXD
REF_CLK_32K M.2_32K_OUT
JTAG_nTRSTJTAG_TMS
JTAG_TCKCLKOUT1
UART3_TXD
ECSPI2_MOSI
CLKOUT2
I2C3_SCLI2C3_SDAI2C4_SCL
I2C4_SDAUART2_RXDUART2_TXDUART4_RXDUART4_TXD
JTAG_TDO
ONOFFPMIC_ON_REQPOR_B
JTAG_TDI
SD1_STROBESD2_DATA2
SD2_CLKSD2_DATA3
SD2_CMD
SD2_DATA1SD2_DATA0
SD2_nCDSD2_WP
SD2_nRST
CLKIN1CLKIN2BOOT_MODE0BOOT_MODE1
GPIO1_IO08
GPIO1_IO05GPIO1_IO01
GPIO1_IO09GPIO1_IO10
SAI2_RXFSSAI2_MCLK
SAI5_RXFS
GPIO1_IO11GPIO1_IO12GPIO1_IO13
GPIO1_IO15GPIO1_IO14
GPIO1_IO07GPIO1_IO06
SAI1_RXD0
SAI1_RXD2SAI1_RXD1
SAI1_RXCSAI1_RXFS
SAI1_RXD6
SAI1_RXD3
SAI1_RXD5SAI1_RXD4
SAI1_RXD7
SAI1_TXFSSAI1_MCLK
SAI3_TXFS
M.2_32K_OUTSYS_nRSTSAI3_MCLK
SAI3_TXC
SAI3_RXDSAI3_RXC
SAI3_TXDSAI3_RXFS
SPDIF_TXSPDIF_RX
SPDIF_EXT_CLKPDM_CLKPDM_DATA0PDM_DATA1PDM_DATA2PDM_DATA3
SAI5_MCLKSAI2_RXC
SAI1_TXD2
SAI1_TXD3SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7
SAI1_TXD1SAI1_TXD0SAI1_TXC
ENET_RXCENET_RX_CTL
ENET_RD0
ENET_RD2ENET_RD1
ENET_RD3
ENET_MDIOENET_MDC
ENET_TXC
ENET_TX_CTL
ENET_TD0
ENET_TD2ENET_TD1
ENET_TD3
TEST_MODE
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