T1 hardware tor Control System, OK veral automates have been added, LV and HV sequences. M manages transition between Busy, ON and OFF states. tor Safety System, OK tector temperatures within expected range. Control Loop, OK in 40MHz LHC clock and Fast Command. ystem chain, OK ded a firmware patch to the ORx mezzanine to increase the robustness the system in the rare case the frame sent from the detector is corrupte er system, OK stalled new fibers distribution patch panel. stalled two new Trigger TOTFED boards with 3 ORxs each. ployed new Trigger TOTFED firmware FW OPTO Receiver FPGA, calculates the CSC hits multiplicity. FW Merger FPGA, calculates which sextant is fires based on majority voting (x out of 5 CSC planes) technique. er chain under test, ready for next 90m * run.
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T1 hardware Detector Control System, OK several automates have been added, LV and HV sequences. FSM manages transition between Busy, ON and OFF states.
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T1 hardware
Detector Control System, OKseveral automates have been added, LV and HV sequences.FSM manages transition between Busy, ON and OFF states.
Detector Safety System, OKDetector temperatures within expected range.
Slow Control Loop, OKMain 40MHz LHC clock and Fast Command.
DAQ system chain, OKadded a firmware patch to the ORx mezzanine to increase the robustnessof the system in the rare case the frame sent from the detector is corrupted.
Trigger system, OKinstalled new fibers distribution patch panel.installed two new Trigger TOTFED boards with 3 ORxs each.deployed new Trigger TOTFED firmware
FW OPTO Receiver FPGA, calculates the CSC hits multiplicity.FW Merger FPGA, calculates which sextant is fires based onmajority voting (x out of 5 CSC planes) technique.
Trigger chain under test, ready for next 90m * run.