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T-Micro From chip level to 12” wafer level 3D processing
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T-Micro · 2018. 4. 4. · We focus on a versatile bonding technology for silicon LSI, compound semiconductor, and microelectromechanical system devices at temperatures of less than

Sep 17, 2020

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Page 1: T-Micro · 2018. 4. 4. · We focus on a versatile bonding technology for silicon LSI, compound semiconductor, and microelectromechanical system devices at temperatures of less than

T-Micro

From chip level to 12” wafer level 3D processing

Page 2: T-Micro · 2018. 4. 4. · We focus on a versatile bonding technology for silicon LSI, compound semiconductor, and microelectromechanical system devices at temperatures of less than

Tohoku-MicroTec Co., Ltd.Tohoku-MicroTec Co., Ltd.

Advantages of 3D IC

Conventional SoC 3D-SoCLength of TSV:

20-150mm

-Short global interconnect small RC delay, small CP

-High band width-Small form factor

1. Maximization of electrical performances

2. Increase of circuit density

3. New Architecture (Hyper-parallel processing, Multifunction, etc)

4. Heterogeneous integration

5. Cost reduction

6. Realization of high performance detector with ~100% area factor in chip

segment 2D-SoC into functional block

Long Global interconnect

large RC delay, large CP

Sync.

clock

Compound semiconductor

SoC: System on Chip (System LSI)

We provide cutting-edge 3D-IC R&D Prototyping and Pilot / Low-Volume Production Service

State-of-the-art technologies◦ 200mm and 300mm 3D process engineering lines and advanced technology platforms

- design / layout / mask making

- wafer / chip thinning

- forming TSV on chip / wafer (front side / backside TSV)

- redistribution routing

- both side u-bumps formation on chip / wafer

- chip / wafer stacking

3D stacking LSIs prototype manufacturing service◦ Prototyping of proof of concepts using commercial/customized 2D chips

◦ die-level 3D hetero-integration with backside TSV technology

Support your small-volume, special customized 3D productions◦ base-line process set-up for the pilot production

◦ facilitate your product development

2.5D interposer R&D foundry and pilot production service ◦ Large area interposer

◦ Interposer with passive devices

Development innovative 3D stacking technologies for creative 3D products and

applications

Supply IP and special customized TEG wafers for process-induced reliability

characterization

Page 3: T-Micro · 2018. 4. 4. · We focus on a versatile bonding technology for silicon LSI, compound semiconductor, and microelectromechanical system devices at temperatures of less than

Lineup of Neural Microprobes

Double–sided

Si Probes

Array typeMicroelectrode

Microprobe w/ μ-fluidic channel

4-shunk

Double–sided

Si Probes

w/ optical waveguide

μ-bump

μ-TSV (10k~1M TSVs/chip)

Technology / Samples

MicroProbes for Neural recording

・Diagnosis and treatment for brain disorder

・Research for BMI/BCI

[Double-sided Si Probe]

[ Tungsten core Omnidirectional probe]

Others

Obsessive-Compulsive Disorder (OCD)

Parkinson’s Disease

Essential Tremor

Epilepsy245,000

216,000

80,000

775,000

3,500,000

Depression

Research/InvestigationPractical use

DystoniaNeurodegenerative Disease

Diagnosis of Epilepsy patient

Au micro-bump connection

Overall view

1.3

mm

38 chips stack

Low cost 3D-Soc Manufacturing Technology

We focus on a versatile bonding technology for silicon LSI,compound semiconductor, and microelectromechanical systemdevices at temperatures of less than 200 C for heterogeneousintegration. Our new gold (Au) micro-bump technology is one of thepromising candidates for this purpose.

12-inch Wafer50mm

2.5D Interposer

3μmΦ 5-10μmΦ0.7μmΦ

18

μm

W-TSV Cu-TSV (Via middle)

3μm

Cu-TSV (Via last)

30

μm

TSV Process

3D Stacked Imager Sensor

LSI Chip

LSI Chip

Capacitor Chip

Inductor Chip

MEMS Chip

Cavity ChipBeam Lead

Cu TSV

Interposer

Cu Sidewall

Chip

Hetero-Integrated LSI-MEMS Multi-Chip Module

Vertically Stacked MEMS on LSI Chip

MEMS Chip

LSI ChipSubstrate

Cu Sidewall

UT

LT

Back gate Metal

5μm

UT: upper tier

LT: lower tier

3D Stacked SOI pixel detector

3D-MEMS/Hetero-Integration

5μm 5μm

Cylinder bump for fragile material5μm pitch Au Cone bump

CdTe

Si

3D-Sensor/Detector

TSV

Micro-bump

Heterogeneous Integration

Low cost fabrication

5μm

Page 4: T-Micro · 2018. 4. 4. · We focus on a versatile bonding technology for silicon LSI, compound semiconductor, and microelectromechanical system devices at temperatures of less than

Headquarter (Japan)

6-6-40 Aza-Aoba Suite 203, Aramaki, Aoba-ku,

Sendai, 980-8579 Japan

Phone:+81-22-398-6264, Fax:+81-22-398-6265

[email protected]

US Office

750 North King Road #206 San Jose CA 95133

USA

Phone: 408-464-7972

[email protected]

Information in this document is subject to change without notice.

Copyright (C) 2016 Tohoku-MicroTec Co., Ltd. All Right Reserved.

200mm/300mm 3D Integration Process Facilities

Tohoku-MicroTec Co., Ltd. (http://www.t-microtec.com)

DeveloperDouble sided

i-Line Stepper

Low Temp.

Asher

High-Aspect-Ratio Sputter Electroplating SystemMetal Etcher

CtW / WtW Aligner and BonderSelf-Assembly System CtC / CtW Flip-Chip Bonder

TSV Liner-CVDEdge Trimming Dicing SawWafer Grinder CMPWafer Debonder Evaporator for Metal Bump

Temporary Bonder Deep Si RIE Self-Assembly Multichip

Bonder

NpD for cone

bump

T-Micro

Ver.9.0