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SystemVerilog Assertions andFunctional Coverage

Ashok B. Mehta

SystemVerilog Assertionsand Functional CoverageGuide to Language, Methodologyand Applications

Second Edition

123

Ashok B. MehtaLos Gatos, CAUSA

Additional material to this book can be downloaded from http://extras.springer.com.

ISBN 978-3-319-30538-7 ISBN 978-3-319-30539-4 (eBook)DOI 10.1007/978-3-319-30539-4

Library of Congress Control Number: 2016932750

© Springer International Publishing Switzerland 2014, 2016This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or partof the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmissionor information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilarmethodology now known or hereafter developed.The use of general descriptive names, registered names, trademarks, service marks, etc. in thispublication does not imply, even in the absence of a specific statement, that such names are exempt fromthe relevant protective laws and regulations and therefore free for general use.The publisher, the authors and the editors are safe to assume that the advice and information in thisbook are believed to be true and accurate at the date of publication. Neither the publisher nor theauthors or the editors give a warranty, express or implied, with respect to the material contained herein orfor any errors or omissions that may have been made.

Printed on acid-free paper

This Springer imprint is published by Springer NatureThe registered company is Springer International Publishing AG Switzerland

To

My dear wife Ashraf Zahedi

and

My dear parents Rukshamaniand Biren Mehta

Foreword

Louis H. Sullivan, an American architect, considered the father of the modernskyscraper, and mentor to Frank Lloyd Wright, coined the phrase ‘form followsfunction.’ The actual quote is ‘form ever follows function’ which is a bit morepoetic and assertive than the version that has found its way into the commonvernacular. He wrote those words in an article written for Lippincott’s Magazine#57 published in March 1896. Here is the passage in that article that contains thefamous quote:

“Whether it be the sweeping eagle in his light or the open apple-blossom, then toiling workhorse, the blithe swan, the branching oak, the winding stream at its base, the drifting clouds—over all the coursing sun, form ever follows function, and this is the law.Where function doesnot change, form does not change. The granite rocks, the ever brooding hills, remain for ages;the lightning lives, comes into shape, and dies, in a twinkling.

It is the pervading law of all things organic and inorganic, of all things physical andmetaphysical, of all things human and all things superhuman—of all true manifestationsof the head, of the heart, of the soul—that the life is recognizable in its expression, thatform ever follows function. This is the law.”

Earlier in the article, Sullivan foreshadows his thought with this passage:

“All things in nature have a shape, that is to say, a form, an outward semblance, that tells uswhat they are, that distinguishes them from ourselves and from each other.”

The precise meaning of this pithy phrase has been debated in art and architecturecircles since Sullivan’s article was first published. However, it is widely accepted tomean that the form of something—its shape, color, size, etc.—is related to what itdoes. Water flows, rocks sit, and birds fly.

In his book ‘The Design of Everyday Things,’ (Basic Books 1988) Don Normandiscusses a similar concept, the notion of affordances. Norman defines the term as‘… the perceived and actual properties of the thing, primarily those fundamentalproperties that determine just how the thing could possibly be used.’ He cites someexamples: ‘A chair affords (“is for”) support and, therefore, affords sitting. A chair

vii

can also be carried. Glass is for seeing through, and for breaking. Wood is normallyused for solidity, opacity, support or carving.’

Norman’s idea turns Sullivan’s upside down. He is saying function followsform. The shape, color, size, etc., of an object affects what it does. Nonetheless,both men would likely agree that form and function, whichever drives the other, areinextricably linked.

Software designers have the luxury of choosing the form to fit the function. Theyare not as constrained by the laws of physics as say, a cabinetmaker. The cabi-netmaker must choose materials that will not only look nice, but will withstand theweight of books or dishes or whatever is to be placed on the shelves. Softwaredesigners have some constraints with regard to memory space and processing time,but beyond that they have a lot of freedom to build whatever comes to mind.

Sullivan referred to ‘all things physical and metaphysical.’ Without much of astretch, we can interpret that to include software, a most abstract human creation.The form of a piece of software is linked to its function. The complex software thatverification engineers build, called a testbench, must be designed before it can bebuilt. The verification engineer, like an architect, must determine the form of hiscreation.

The architecture space is wide open. Computer code, while much more abstractthan say, a staircase or a door handle on a car, has a form and a function. The formof computer code is the set of syntactic elements strung together in a program. Thefunction is what the program does when executed, often referred to as its semantics.

A verification engineer is typically presented a set of requirements, often as adesign specification, and asked to build a testbench that meets these requirements.Because of the tremendous flexibility afforded by the software medium, he mustchoose the form carefully to ensure that not only meets the requirements, but is easyto use, reusable, and robust. He must choose a form that fits the function.

Often an assertion is just the right thing to capture the essence of some part of adesign. The form of an assertion is short sequence of text that can be inserted easilywithout disrupting the design. With their compact syntax and concise semantics,assertions can be used to check low-level invariants, protocols, or end-to-endbehavior.

The function of an assertion, in a simulation context, is to assert that somethingis always (or never) the case. It ensures that invariants are indeed invariant.Assertions can operate as checkers or as coverpoints. The fact that they can beincluded in-line in RTL code or in separate checkers and that they can be short orlong for simple or complex checking makes them invaluable in any testbench.

The wise verification engineer uses all the tools as his disposal to create aneffective and easy-to-use testbench. He will consider the function of the testbenchand devise a form that suits the required function. Assertions are an important partof any testbench.

Ashok Mehta has written a book that makes assertions accessible. His approach isvery pragmatic, choosing to show you how to build and use assertions rather thanengage in a lot of theoretical discussion. Not that theoretical discussion is irrelevant—it is useful to understand the theoretical underpinnings of any technology. However,

viii Foreword

there are many other books on that topic. This book fills a gap for practicing engineerswhere before no text provided the how-tos of building and using assertions in areal-world context.

Ashok opens up the world of assertions to verification engineers who may havethought them too opaque to consider using in a real testbench. He does an espe-cially nice job of deconstructing assertions to show how they work and how to writethem. Through detailed examples, he shows all the pieces that go into creatingassertions of different kinds, and how they fit together. Ashok completes the pictureby demonstrating how assertions and coverage fit together.

Part of the book is devoted to functional coverage. He deconstructs the some-times awkward SystemVerilog syntax of covergoups and coverpoints. Like he haswith assertions, he takes the mystery out of building a high-quality coverage model.

With the mysteries of assertions unmasked, you can now include them in yourpersonal vocabulary of testbench forms. This will enable you to create testbencheswith more sophisticated function.

February 2013 Mark Glasser

Foreword ix

Preface to the Second Edition

The first edition of this book was well received, and the readers provided many agood suggestion on further elaboration of language semantics. Readers also pointedout some errata on the language syntax. I am greatly indebted to the readers andcolleagues for their input and support. In addition, the IEEE 1800-2012 LRM camealong. Many features of the 2012 LRM were missing in the first edition, since theLRM was not ready yet. This edition incorporates the errata/suggestions fromreaders as well as the IEEE 1800-2012 feature set. Among many, features such as‘checkers,’ ‘let declarations,’ past and future global clock sampled value functions,strong and weak properties, abort properties, and ‘.triggered’ end point detectionmethod are included. Furthermore, this edition adds many more examples and addsfurther clarification of the semantic nuances of the language.

Pleasant reading.

xi

Preface to the First Edition

Having been an end user of EDA tools for over 20 years, I have seen that many newtechnologies stay on wayside because either the engineers do not have time to learnthese new technologies/languages or the available material is too complex to digest.A few years back I decided to tackle this problem by creating a very practical,application-oriented down-to-earth SystemVerilog Assertions (SVA) and functionalcoverage (FC) class for professional engineers. The class was well received, and Ireceived a lot of feedback on making the class even more useful. That culminated inover 500 slides of class material just on SVA and FC. Many suggested that I hadcollected enough material for a book. That is how I ended up on this project withthe same goal that the reader should understand the concept clearly in an easy andintuitive manner and be able to apply the concepts to real-life applications rightaway.

The style of the book is such that the concepts are clarified directly in a slidestyle diagram with talking points. This will hopefully make it easy to use the bookas a quick reference as well. Applications immediately following a topic will furtherclarify the subject matter, and my hope is that once you understand the semanticsand applications of a given topic, you are ready to apply that to your daily designwork. These applications are modeled such that you should be able to use them inyour design with minimal modifications.

This book is meant for both design and verification engineers. As a matter offact, I have devoted a complete section on the reasons and practicality behindhaving micro-level assertions written by the design engineers and macro-levelassertions written by verification engineers. Gone are the days when designerswould write RTL and throw it over the wall for the verification engineer to qualitycheck.

The book covers both IEEE 1800-2005 and IEEE 1800-2009/2012 standardSVA language.

Chapter 1 is introduction to SVA and FC giving a brief history of SVA evo-lution. It also explains how SVA and FC fall under SystemVerilog umbrella toprovide a complete assertions and functional coverage-driven methodology.

xiii

Part I: SystemVerilog Assertions (SVA)

Chapter 2 goes in-depth on SVA-based methodology providing detail that you canright away use in your project execution. Questions such as ‘How do I know I haveadded enough assertions?’, ‘What type of assertions should I add’, etc., areexplained with clarity.

Chapter 3 describes immediate assertions. These are non-temporal assertionsallowed in procedural code.

Chapter 4 goes into the fundamentals of concurrent assertions to set the stage forthe rest of the book. How the concurrent multi-threaded semantics work, when andhow assertions get evaluated in a simulation time tick, formal arguments, disabling,etc., are described here.

Chapter 5 describes the so-called sampled value functions such as $rose, $fell,$stable, $past, etc.

Chapter 6 is the big one! This chapter describes all the operators offered by thelanguage including clock delay with and without range, consecutive repetition withand without range, non-consecutive repetition with and without range, ‘through-out,’ ‘within,’ ‘and,’ ‘or,’ ‘intersect,’ ‘first_match,’ and ‘if…else,’. Each of theoperator descriptions is immediately followed by examples and applications tosolidify the concept.

Chapter 7 describes the system functions and tasks such as $isunknown and$onehot.

Chapter 8 discusses a very important aspect of the language that being propertieswith multiple clocks. There is not a single design nowadays that uses only a singleclock. A simple asynchronous FIFO will have a read clock and a write clock whichare asynchronous. Properties need to be written such that check in one clockdomain triggers a check in another clock domain. The chapter goes in plenty detailto demystify semantics to write assertions that cross clock domains. The so-calledCDC (Clock Domain Crossing) assertions are explained in this chapter.

Chapter 9 is probably the most useful one describing local variables. Withoutthis multi-threaded feature, many of the assertions would be impossible to write.There are plenty of examples to help you weed through the semantics.

Chapter 10 is on recursive properties. These are rarely used but are very handywhen you want to know that a property holds until another becomes true or false.

Chapters 11–13 describe other useful features such as ‘expect,’ ‘assume,’ anddetecting end point of a sequence. The .triggered and .matched end points ofsequences are indeed very practical features. Note that .ended (of LRM 2005) isnow deprecated and replaced with .triggered.

Chapter 14 is entirely devoted to very powerful and practical features that do notquite fit elsewhere. Of main interest, here is the example/testbench for asyn-chronous FIFO checks, concurrent assertions in procedural code, sequence inVerilog ‘always’ block sensitivity list, and the phenomenon of a ‘vacuous pass’ !

Chapter 15 is solely devoted to asynchronous assertions. The example in thischapter shows why you need to be extremely careful in using such assertions.

xiv Preface to the First Edition

Chapter 16 is entirely devoted to IEEE 1800 2009-2012 features. There aremany useful features added by the language designers.

Chapter 17 describes 6 LABs for you to try out. The LABs start with simpleexample moving gradually onto complex ones.

Note: The LABs are available on Springer download site. All required Verilogfiles, testbenches, and run scripts are included for both PC and Linux OS.

Chapter 18 provides answers to the LABs of Chap. 17

Part II: SystemVerilog Functional Coverage (FC)

Chapter 19 provides introduction to functional coverage and explains differenceswith code coverage.

Chapter 20 is fully devoted to functional coverage including in-depth detail oncovergroups, coverpoints, and bins including transition and cross coverage.

Chapter 21 provides practical hints to performance implications of coveragemethodology. Do not try to cover everything all the time.

Chapter 22 describes coverage options, which you may keep in your back pocketas reference material for a rainy day!

Preface to the First Edition xv

Acknowledgements

I am very grateful to many who helped with review and editing of the book, inparticular, Mark Glaser for his excellent foreword and in-depth review of the book,Vijay Akkati for detailed review of the chapters, Dr. Sandeep Goel for motivationand editing of the book, and Bob Slee for his sustained support throughout theendeavor and for facilitating close cooperation with EDA vendors. I would also liketo thank Tom Slee, Kea Hunt, Norbert Eng, Joe Chang, and Frank Lee for all thingsverification.

And last but certainly not the least, I would like to thank my wife Ashraf Zahedifor her enthusiasm and encouragement throughout the writing of this book andputting up with long nights and weekends required to finish the book. She is thecornerstone of my life always with a positive attitude to carry the day through upand down of life.

xvii

Contents

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 How Will This Book Help You? . . . . . . . . . . . . . . . . . . . . . 41.2 SystemVerilog Assertions and Functional Coverage

Under IEEE 1800 SystemVerilog Umbrella . . . . . . . . . . . . . . 51.3 SystemVerilog Assertions Evolution . . . . . . . . . . . . . . . . . . . 7

2 SystemVerilog Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 What Is an Assertion? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2 Why Assertions? What Are the Advantages? . . . . . . . . . . . . . 9

2.2.1 Assertions Shorten Time to Develop . . . . . . . . . . . . 102.2.2 Assertions Improve Observability . . . . . . . . . . . . . . 112.2.3 Assertions Provide Temporal Domain Functional

Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.4 Assertion Based Methodology Allows for Full

Random Verification . . . . . . . . . . . . . . . . . . . . . . . 142.2.5 Assertions Help Detect Bugs not Easily Observed

at Primary Outputs . . . . . . . . . . . . . . . . . . . . . . . . 152.2.6 Other Major Benefits . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 How Do Assertions Work with an Emulator?. . . . . . . . . . . . . 162.4 Assertions in Static Formal . . . . . . . . . . . . . . . . . . . . . . . . . 172.5 One-Time Effort, Many Benefits. . . . . . . . . . . . . . . . . . . . . . 192.6 Assertions Whining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6.1 Who Will Add Assertions? War Within! . . . . . . . . . 212.7 A Simple PCI Read Example—Creating an Assertions Test

Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.8 What Type of Assertions Should I Add? . . . . . . . . . . . . . . . . 242.9 Protocol for Adding Assertions . . . . . . . . . . . . . . . . . . . . . . 252.10 How Do I Know I Have Enough Assertions? . . . . . . . . . . . . . 262.11 Use Assertions for Specification and Review . . . . . . . . . . . . . 262.12 Assertion Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.13 Conventions Used in the Book. . . . . . . . . . . . . . . . . . . . . . . 28

xix

3 Immediate Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 Concurrent Assertions—Basics (Sequence, Property, Assert) . . . . . 354.1 Implication Operator, Antecedent and Consequent . . . . . . . . . 404.2 Clocking Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424.3 Sampling Edge (Clock Edge) Value: How Are Assertions

Evaluated in a Simulation Time Tick?. . . . . . . . . . . . . . . . . . 444.3.1 Default Clocking Block . . . . . . . . . . . . . . . . . . . . . 484.3.2 Gated Clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.4 Concurrent Assertions Are Multi-threaded . . . . . . . . . . . . . . . 534.5 Formal Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.6 Disable (Property) Operator—‘Disable Iff’ . . . . . . . . . . . . . . . 584.7 Severity Levels (for Both Concurrent and Immediate

Assertions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.8 Binding Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.8.1 Binding Properties (Scope Visibility) . . . . . . . . . . . . 624.8.2 Assertion Adoption in Existing Design . . . . . . . . . . 64

4.9 Difference Between ‘Sequence’ and ‘Property’ . . . . . . . . . . . . 65

5 Sampled Value Functions $rose, $fell, $stable, $past . . . . . . . . . . . 675.1 $rose—Edge Detection in Property/Sequence . . . . . . . . . . . . . 68

5.1.1 Edge Detection Is Useful Because … . . . . . . . . . . . 685.1.2 $fell—Edge Detection in Property/Sequence. . . . . . . 715.1.3 $rose, $fell—in Procedural . . . . . . . . . . . . . . . . . . . 71

5.2 $stable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725.2.1 $stable in Procedural Block . . . . . . . . . . . . . . . . . . 73

5.3 $past. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.3.1 Application: $past () . . . . . . . . . . . . . . . . . . . . . . . 785.3.2 $past Rescues $fell! . . . . . . . . . . . . . . . . . . . . . . . 78

6 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816.1 ##m—Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.1.1 Clock Delay Operator: ##m Where m=0 . . . . . . . . . 826.2 ##[m:n]—Clock Delay Range . . . . . . . . . . . . . . . . . . . . . . . 84

6.2.1 Clock Delay Range Operator: ##[m:n]: MultipleThreads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.2.2 Clock Delay Range Operator :: ##[m:n](m=0; n=$) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.3 [*m]—Consecutive Repetition Operator. . . . . . . . . . . . . . . . . 946.4 [*m:n]—Consecutive Repetition Range . . . . . . . . . . . . . . . . . 98

6.4.1 Application: Consecutive Repetition RangeOperator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.5 [=m]—Repetition Non-consecutive . . . . . . . . . . . . . . . . . . . . 1076.6 [=m:n]—Repetition Non-consecutive Range. . . . . . . . . . . . . . 111

6.6.1 Application: Repetition Non-consecutiveOperator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

xx Contents

6.7 [->m] Non-consecutive GoTo Repetition Operator . . . . . . . . . 1146.8 Difference Between [=m:n] and [->m:n] . . . . . . . . . . . . . . . . 115

6.8.1 Application: GoTo Repetition—Non-consecutiveOperator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6.9 Sig1 throughout Seq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176.9.1 Application: Sig1 throughout Seq1 . . . . . . . . . . . . . 118

6.10 Seq1 within Seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216.10.1 Application: Seq1 within Seq2 . . . . . . . . . . . . . . . . 1226.10.2 ‘within’ Operator PASS CASES . . . . . . . . . . . . . . . 1236.10.3 ‘within’ Operator: FAIL CASES. . . . . . . . . . . . . . . 124

6.11 Seq1 and Seq2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246.11.1 Application: ‘and’ Operator . . . . . . . . . . . . . . . . . . 127

6.12 Seq1 ‘or’ Seq2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276.12.1 Application: or Operator . . . . . . . . . . . . . . . . . . . . 128

6.13 Seq1 ‘intersect’ Seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316.14 Application: ‘intersect’ Operator . . . . . . . . . . . . . . . . . . . . . . 132

6.14.1 Application: intersect Operator (InterestingApplication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6.14.2 ‘intersect’ and ‘and’ :: What’s the Difference? . . . . . 1376.15 first_match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.15.1 Application: first_match . . . . . . . . . . . . . . . . . . . . . 1386.16 not <property expr> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

6.16.1 Application: not Operator. . . . . . . . . . . . . . . . . . . . 1416.17 if (expression) property_expr1 else property_expr2 . . . . . . . . . 143

6.17.1 Application: if then else. . . . . . . . . . . . . . . . . . . . . 1456.18 ‘iff’ and ‘implies’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7 System Functions and Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477.1 $onehot, $onehot0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477.2 $isunknown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497.3 $countones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.3.1 $countones (as Boolean) . . . . . . . . . . . . . . . . . . . . 1517.4 $assertoff, $asserton, $assertkill . . . . . . . . . . . . . . . . . . . . . . 151

8 Multiple Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558.1 Multiply-Clocked Sequences and Properties . . . . . . . . . . . . . . 155

8.1.1 Multiply Clocked Sequences . . . . . . . . . . . . . . . . . 1568.1.2 Multiply Clocked Sequences—Legal and Illegal

Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578.1.3 Multiply Clocked Properties—‘and’ Operator . . . . . . 1588.1.4 Multiply Clocked Properties—‘or’ Operator . . . . . . . 1598.1.5 Multiply Clocked Properties—‘not’—Operator . . . . . 1618.1.6 Multiply Clocked Properties—Clock Resolution . . . . 1618.1.7 Multiply Clocked Properties—Legal and Illegal

Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Contents xxi

9 Local Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679.1 Application: Local Variables . . . . . . . . . . . . . . . . . . . . . . . . 179

10 Recursive Property. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18110.1 Application: Recursive Property . . . . . . . . . . . . . . . . . . . . . . 18210.2 Application: Recursive Property . . . . . . . . . . . . . . . . . . . . . . 183

11 Detecting and Using Endpoint of a Sequence . . . . . . . . . . . . . . . . . 18711.1 .triggered (Replaced for .ended) . . . . . . . . . . . . . . . . . . . . . . 18711.2 .matched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

11.2.1 Application: .matched . . . . . . . . . . . . . . . . . . . . . . 198

12 ‘expect’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

13 ‘assume’ and Formal (Static Functional) Verification . . . . . . . . . . . 205

14 Very Important Topics and Applications . . . . . . . . . . . . . . . . . . . . 20714.1 Asynchronous FIFO Assertions . . . . . . . . . . . . . . . . . . . . . . 207

14.1.1 Asynchronous FIFO Design . . . . . . . . . . . . . . . . . . 20814.1.2 Asynchronous FIFO Testbench and Assertions . . . . . 21014.1.3 Test the Testbench . . . . . . . . . . . . . . . . . . . . . . . . 214

14.2 Embedding Concurrent Assertions in Procedural Code . . . . . . 21714.3 Calling Subroutines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22214.4 Sequence as a Formal Argument . . . . . . . . . . . . . . . . . . . . . 22514.5 Sequence as an Antecedent . . . . . . . . . . . . . . . . . . . . . . . . . 22614.6 Sequence in Sensitivity List . . . . . . . . . . . . . . . . . . . . . . . . . 22714.7 Building a Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22814.8 Clock Delay: What if You Want Variable Clock Delay? . . . . . 22914.9 What if the ‘Action Block’ Is Blocking? . . . . . . . . . . . . . . . . 23114.10 Interesting Observation with Multiple (Nested) Implications

in a Property. Be Careful. . . . . . . . . . . . . . . . . . . . . . . . . . . 23414.11 Subsequence in a Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 23514.12 Cyclic Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23614.13 Refinement on a Theme . . . . . . . . . . . . . . . . . . . . . . . . . . . 23714.14 Simulation Performance Efficiency . . . . . . . . . . . . . . . . . . . . 23714.15 It’s a Vacuous World! Huh? . . . . . . . . . . . . . . . . . . . . . . . . 239

14.15.1 Concurrent Assertion—Without—An Implication . . . 23914.15.2 Concurrent Assertion—With—An Implication . . . . . 24014.15.3 Vacuous Pass. What? . . . . . . . . . . . . . . . . . . . . . . 24114.15.4 Concurrent Assertion–with ‘Cover’ . . . . . . . . . . . . . 241

14.16 Empty Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

15 Asynchronous Assertions!!!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

16 IEEE-1800-2009/2012 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 25116.1 Strong and Weak Sequences . . . . . . . . . . . . . . . . . . . . . . . . 25116.2 Deferred Immediate Assertions . . . . . . . . . . . . . . . . . . . . . . . 25216.3 $changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

xxii Contents

16.4 $sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25716.5 $past_gclk, $rose_gclk, $fell_gclk, $stable_gclk, $changed_

gclk, $future_gclk, $rising_gclk, $falling_gclk, $steady_gclk,$changing_gclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

16.6 ‘followed by’ Properties #-# and #=# . . . . . . . . . . . . . . . . . . 26116.7 ‘always’ and ‘s_always’ Property . . . . . . . . . . . . . . . . . . . . . 26216.8 ‘eventually’,‘s_eventually’ . . . . . . . . . . . . . . . . . . . . . . . . . . 26416.9 ‘until’, ‘s_until’, ‘until_with’ and ‘s_until_with’ . . . . . . . . . . . 26516.10 ‘nexttime’ and ‘s_nexttime’ . . . . . . . . . . . . . . . . . . . . . . . . . 26716.11 ‘case’ Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27016.12 $inferred_clock and $inferred_disable . . . . . . . . . . . . . . . . . . 27116.13 ‘let’ Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

16.13.1 let: Local Scope . . . . . . . . . . . . . . . . . . . . . . . . . . 27416.13.2 let: With Parameters . . . . . . . . . . . . . . . . . . . . . . . 27516.13.3 let: In Immediate and Concurrent Assertions . . . . . . 277

16.14 ‘restrict’ for Formal Verification . . . . . . . . . . . . . . . . . . . . . . 28016.15 Abort Properties: reject_on, accept_on, sync_reject_on,

sync_accept_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28016.16 $assertpassoff, $assertpasson, $assertfailoff, $assertfailon,

$assertnonvacuouson, $assertvacuousoff . . . . . . . . . . . . . . . . 28416.17 $assertcontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28516.18 Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

16.18.1 Nested Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . 29516.18.2 Checkers: Illegal Conditions . . . . . . . . . . . . . . . . . . 29616.18.3 Checkers: Important Points. . . . . . . . . . . . . . . . . . . 29816.18.4 Checker: Instantiation Rules . . . . . . . . . . . . . . . . . . 301

17 SystemVerilog Assertions LABs . . . . . . . . . . . . . . . . . . . . . . . . . . 30517.1 LAB1: Assertions with/Without Implication and ‘bind’ . . . . . . 305

17.1.1 LAB1: ‘bind’ DUT Model and Testbench . . . . . . . . 30617.1.2 LAB1: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 308

17.2 LAB2: Overlap and Non-overlap Operators . . . . . . . . . . . . . . 31017.2.1 LAB2 DUT Model and Testbench . . . . . . . . . . . . . 31017.2.2 LAB2: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 311

17.3 LAB3: Synchronous FIFO Assertions . . . . . . . . . . . . . . . . . . 31317.3.1 LAB3: DUT Model and Testbench . . . . . . . . . . . . . 31317.3.2 LAB3: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 317

17.4 LAB4: Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32117.4.1 LAB4: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 324

17.5 LAB5: Data Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . 32717.5.1 LAB5: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 335

17.6 LAB6: PCI Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 33617.6.1 LAB6: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 340

Contents xxiii

18 SystemVerilog Assertions—LAB Answers . . . . . . . . . . . . . . . . . . . 34318.1 LAB1: Answers: ‘bind’ and Implication Operators . . . . . . . . . 34418.2 LAB2: Answers: Overlap and Non-overlap Operators . . . . . . . 34918.3 LAB3: Answers: Synchronous FIFO . . . . . . . . . . . . . . . . . . . 35318.4 LAB4: Answers: Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 35518.5 LAB5: Answers: Data Transfer Protocol . . . . . . . . . . . . . . . . 35618.6 LAB6: Answers: PCI Read Protocol . . . . . . . . . . . . . . . . . . . 359

19 Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36119.1 Difference Between Code Coverage and Functional

Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36119.2 Assertion Based Verification (ABV) and Functional Coverage

(FC) Based Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . 36219.2.1 Follow the Bugs!! . . . . . . . . . . . . . . . . . . . . . . . . . 366

20 Functional Coverage—Language Features . . . . . . . . . . . . . . . . . . . 36720.1 Covergroup/Coverpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36720.2 System Verilog ‘Covergroup’—Basics … . . . . . . . . . . . . . . . 36820.3 SystemVerilog Coverpoint Basics . . . . . . . . . . . . . . . . . . . . . 368

20.3.1 Covergroup/Coverpoint Example … . . . . . . . . . . . . 37120.4 System Verilog ‘Bins’—Basics … . . . . . . . . . . . . . . . . . . . . 372

20.4.1 Covergroup/Coverpoint with Bins—Example … . . . . 37420.4.2 System Verilog ‘covergroup’—Formal and Actual

Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37520.4.3 ‘covergroup’ in a ‘class’ . . . . . . . . . . . . . . . . . . . . 376

20.5 ‘cross’ Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37820.6 More ‘Bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

20.6.1 ‘Bins’ for Transition Coverage . . . . . . . . . . . . . . . . 38220.6.2 ‘wildcard bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . 38620.6.3 ‘ignore_bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38620.6.4 ‘illegal_bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38720.6.5 ‘binsof’ and ‘intersect’. . . . . . . . . . . . . . . . . . . . . . 388

21 Performance Implications of Coverage Methodology . . . . . . . . . . . 39121.1 Know What You Should Cover . . . . . . . . . . . . . . . . . . . . . . 39121.2 Know When You Should Cover . . . . . . . . . . . . . . . . . . . . . . 39221.3 When to ‘Cover’ (Performance Implication). . . . . . . . . . . . . . 39221.4 Application: Have You Transmitted All Different Lengths

of a Frame? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

22 Coverage Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39522.1 Coverage Options—Instance Specific—Example. . . . . . . . . . . 39722.2 Coverage Options—Instance Specific Per-Syntactic Level . . . . 39722.3 Coverage Options for ‘Covergroup’ Type—Example. . . . . . . . 400

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

xxiv Contents

About the Author

Ashok B. Mehta has been working in the ASIC/SoC design and verification fieldfor over 20 years. He started his career at Digital Equipment Corporation(DEC) working first as a CPU design engineer, moving on to hardware designverification of the VAX11-785 CPU design. He then worked at Data General, Intel(first Pentium design team) and, after a route of a couple of startups, worked atApplied Micro and TSMC. He was a very early adopter of Verilog and participatedin Verilog, VHDL, iHDL (Intel HDL), and SDF (standard delay format) technicalsubcommittees. He has also been a proponent of ESL (Electronic System Level)designs, and at TSMC, he released two industry-standard reference flows that takedesigns from ESL to RTL while preserving the verification environment for reusefrom ESL to RTL. Lately, he has been involved with 3DIC design verificationchallenges at TSMC which is where SystemVerilog Assertions played an instru-mental role in stacked die SoC design verification.

Ashok earned an MSEE from University of Missouri. He holds 13 US Patents inthe field of SoC and 3DIC design verification. In his spare time, he is an amateurphotographer and likes to play drums on 1970s rock music driving his neighbors upthe wall.

xxv

List of Figures

Figure 1.1 Verification cost increases as the technologynode shrinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 1.2 Design productivity and design complexity . . . . . . . . . . . . 2Figure 1.3 SystemVerilog assertions and functional coverage

components under SystemVerilog IEEE 1800-2009umbrella . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 1.4 SystemVerilog evolution . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 1.5 SystemVerilog assertion evolution . . . . . . . . . . . . . . . . . . 7Figure 2.1 A simple bus protocol design and its SVA property . . . . . . 10Figure 2.2 Verilog code for the simple bus protocol . . . . . . . . . . . . . 11Figure 2.3 Assertions improve observability . . . . . . . . . . . . . . . . . . . 12Figure 2.4 SystemVerilog assertions provide temporal domain

functional coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 2.5 Assertions for hardware emulation . . . . . . . . . . . . . . . . . . 17Figure 2.6 Assertions and assumptions in formal (static functional)

and simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 2.7 Assertions and OVL for different uses . . . . . . . . . . . . . . . 19Figure 2.8 A simple PCI read protocol. . . . . . . . . . . . . . . . . . . . . . . 22Figure 3.1 Immediate assertion—basics . . . . . . . . . . . . . . . . . . . . . . 32Figure 3.2 Immediate assertions: finer points . . . . . . . . . . . . . . . . . . 33Figure 4.1 Concurrent assertion—basics . . . . . . . . . . . . . . . . . . . . . . 36Figure 4.2 Concurrent assertion—sampling edge and action

blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 4.3 Concurrent assertion—implication, antecedent

and consequent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 4.4 Property with an embedded sequence . . . . . . . . . . . . . . . . 39Figure 4.5 Implication operator—overlapping

and non-overlapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 4.6 Equivalence between overlapping and non-overlapping

implication operators . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 4.7 Clocking basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

xxvii

Figure 4.8 Clocking basics—clock in ‘assert’, ‘property’and ‘sequence’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 4.9 Assertions variable sampling and evaluation/execution ina simulation time tick . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 4.10 Default Clocking block. . . . . . . . . . . . . . . . . . . . . . . . . . 49Figure 4.11 ‘clocking’ and ‘default clocking’ . . . . . . . . . . . . . . . . . . . 50Figure 4.12 Gated clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 4.13 Multi-threaded concurrent assertions. . . . . . . . . . . . . . . . . 54Figure 4.14 Formal and actual arguments . . . . . . . . . . . . . . . . . . . . . . 55Figure 4.15 Formal and Actual arguments—default value and name

based connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 4.16 Formal and actual arguments—default value and position

based connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 4.17 Passing event control to a formal . . . . . . . . . . . . . . . . . . . 57Figure 4.18 ‘disable iff’ operator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Figure 4.19 Severity levels for concurrent and immediate

assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 4.20 Binding properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 4.21 Binding properties to design ‘module’ internal signals

(scope visibility) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 4.22 Binding properties to an existing design. Assertions

adoption in existing design . . . . . . . . . . . . . . . . . . . . . . . 64Figure 5.1 Sampled value functions $rose, $fell—basics. . . . . . . . . . . 68Figure 5.2 $rose—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Figure 5.3 usefulness of ‘edge’ detection and performance

implication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 5.4 ; $rose—finer points. . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 5.5 $fell—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 5.6 $rose and $fell in procedural block and continuous

assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Figure 5.7 $stable—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Figure 5.8 $stable in procedural block . . . . . . . . . . . . . . . . . . . . . . . 74Figure 5.9 $past—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 5.10 $past—gating expression . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 5.11 $past—gating expression—simulation log . . . . . . . . . . . . . 77Figure 5.12 $past application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Figure 5.13 $past rescues $fell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 6.1 ##m clock delay—basics . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 6.2 ##m clock delay with m=0 . . . . . . . . . . . . . . . . . . . . . . . 83Figure 6.3 ##0—application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 6.4 ##[m:n] clock delay range. . . . . . . . . . . . . . . . . . . . . . . . 85Figure 6.5 ##[m:n]—multiple threads. . . . . . . . . . . . . . . . . . . . . . . . 87Figure 6.6 ##[m:n] clock delay range with m=0 and n=$ . . . . . . . . . . 95Figure 6.7 ##[1:$] delay range application . . . . . . . . . . . . . . . . . . . . 96

xxviii List of Figures

Figure 6.8 [*m]—consecutive repetition operator—basics . . . . . . . . . . 96Figure 6.9 [*m] consecutive repetition operator—application . . . . . . . 97Figure 6.10 [*m:n] consecutive repetition range—basics . . . . . . . . . . . 98Figure 6.11 [*m:n] consecutive repetition range—example . . . . . . . . . . 100Figure 6.12 [*m:n] consecutive repetition range—application . . . . . . . . 101Figure 6.13 [*m:n] consecutive repetition range—application . . . . . . . . 102Figure 6.14 [*m:n] consecutive repetition range—application . . . . . . . . 103Figure 6.15 [*m:n] consecutive repetition range—application . . . . . . . . 104Figure 6.16 Design application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Figure 6.17 Design application—simulation log . . . . . . . . . . . . . . . . . 108Figure 6.18 Repetition non-consecutive operator—basics . . . . . . . . . . . 109Figure 6.19 Non-consecutive repetition operator—example. . . . . . . . . . 110Figure 6.20 Repetition non-consecutive range—basics . . . . . . . . . . . . . 111Figure 6.21 Repetition non-consecutive range—application . . . . . . . . . 113Figure 6.22 Repetition non-consecutive range—[=0:$] . . . . . . . . . . . . . 113Figure 6.23 GoTo non-consecutive repetition—basics . . . . . . . . . . . . . 114Figure 6.24 Non-consecutive repetition—example . . . . . . . . . . . . . . . . 115Figure 6.25 Difference between [=m:n] and [->m:n] . . . . . . . . . . . . . . 116Figure 6.26 GoTo repetition—non-consecutive

operator—application . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Figure 6.27 Sig1 throughout seq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Figure 6.28 Sig1 throughout Seq1—application . . . . . . . . . . . . . . . . . 119Figure 6.29 Sig1 throughout seq1—application simulation log . . . . . . . 120Figure 6.30 Seq1 within seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Figure 6.31 Seq1 within seq2—application . . . . . . . . . . . . . . . . . . . . . 122Figure 6.32 within operator—simulation log

example—PASS cases . . . . . . . . . . . . . . . . . . . . . . . . . . 123Figure 6.33 within operator—simulation log

example—FAIL cases . . . . . . . . . . . . . . . . . . . . . . . . . . 125Figure 6.34 Seq1 and seq2—basics . . . . . . . . . . . . . . . . . . . . . . . . . . 126Figure 6.35 and operator—application . . . . . . . . . . . . . . . . . . . . . . . . 126Figure 6.36 and operator—application-II . . . . . . . . . . . . . . . . . . . . . . 127Figure 6.37 and of expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Figure 6.38 Seq1 or seq2—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Figure 6.39 or operator—application . . . . . . . . . . . . . . . . . . . . . . . . . 129Figure 6.40 or operator—application II . . . . . . . . . . . . . . . . . . . . . . . 130Figure 6.41 or operator—application III . . . . . . . . . . . . . . . . . . . . . . . 131Figure 6.42 or of expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Figure 6.43 Seq1 intersect seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Figure 6.44 Seq1 ‘intersect’ seq2—application . . . . . . . . . . . . . . . . . . 134Figure 6.45 Seq1 intersect seq2—application II. . . . . . . . . . . . . . . . . . 134Figure 6.46 intersect makes sense with subsequences with ranges . . . . . 135Figure 6.47 intersect operator: interesting application. . . . . . . . . . . . . . 135Figure 6.48 and versus intersect—what’s the difference . . . . . . . . . . . . 137

List of Figures xxix

Figure 6.49 first_match—application . . . . . . . . . . . . . . . . . . . . . . . . . 139Figure 6.50 first_match application . . . . . . . . . . . . . . . . . . . . . . . . . . 140Figure 6.51 first_match application . . . . . . . . . . . . . . . . . . . . . . . . . . 140Figure 6.52 not operator—basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Figure 6.53 not operator—application . . . . . . . . . . . . . . . . . . . . . . . . 142Figure 6.54 not operator—application . . . . . . . . . . . . . . . . . . . . . . . . 143Figure 6.55 if… else . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Figure 6.56 if… else—application . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Figure 7.1 $onehot and $onehot0 . . . . . . . . . . . . . . . . . . . . . . . . . . 148Figure 7.2 $isunknown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Figure 7.3 $isunknown application . . . . . . . . . . . . . . . . . . . . . . . . . 149Figure 7.4 $countones—basics and application . . . . . . . . . . . . . . . . . 150Figure 7.5 Application $countones. . . . . . . . . . . . . . . . . . . . . . . . . . 150Figure 7.6 $countones as boolean . . . . . . . . . . . . . . . . . . . . . . . . . . 151Figure 7.7 $assertoff, $asserton, $assertkill—basics . . . . . . . . . . . . . . 152Figure 7.8 Application assertion control . . . . . . . . . . . . . . . . . . . . . . 152Figure 8.1 Multiply clocked sequences—basics . . . . . . . . . . . . . . . . . 156Figure 8.2 Multiply clocked sequences—identical clocks . . . . . . . . . . 157Figure 8.3 Multiply clocked sequences—illegal conditions . . . . . . . . . 158Figure 8.4 Multiply clocked properties—‘and’ operator

between two different clocks . . . . . . . . . . . . . . . . . . . . . . 159Figure 8.5 Multiply clocked properties—‘and’ operator

between same clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Figure 8.6 Multiply clocked properties—‘or’ operator . . . . . . . . . . . . 160Figure 8.7 Multiply clocked properties—‘not’ operator. . . . . . . . . . . . 161Figure 8.8 Multiply clocked properties—clock resolution . . . . . . . . . . 162Figure 8.9 Multiply clocked properties—clock resolution—II . . . . . . . 162Figure 8.10 Multiply clocked properties—clock resolution—III. . . . . . . 163Figure 8.11 Multiply clocked properties—legal and illegal

conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Figure 9.1 Local variables—basics . . . . . . . . . . . . . . . . . . . . . . . . . 168Figure 9.2 Local variables—do’s and don’ts . . . . . . . . . . . . . . . . . . . 169Figure 9.3 Local variables—and formal argument . . . . . . . . . . . . . . . 170Figure 9.4 Local variables—visibility. . . . . . . . . . . . . . . . . . . . . . . . 171Figure 9.5 Local variable composite sequence with an ‘OR’ . . . . . . . . 171Figure 9.6 Local variables—for an ‘OR’ assign local

data—before- the composite sequence . . . . . . . . . . . . . . . 172Figure 9.7 Local variables—assign local data in both

operand sequences of ‘OR’ . . . . . . . . . . . . . . . . . . . . . . . 172Figure 9.8 Local variables—‘and’ of composite sequences . . . . . . . . . 173Figure 9.9 Local variables—finer nuances III . . . . . . . . . . . . . . . . . . 173Figure 9.10 Local variables—further nuances IV. . . . . . . . . . . . . . . . . 174Figure 9.11 Local variable cannot be used in delay range. . . . . . . . . . . 174

xxx List of Figures

Figure 9.12 Local variables—cannot use a ‘formal’ to size a localvariable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 9.13 Local variables—application . . . . . . . . . . . . . . . . . . . . . . 179Figure 10.1 Recursive property—basics . . . . . . . . . . . . . . . . . . . . . . . 182Figure 10.2 Recursive property—application. . . . . . . . . . . . . . . . . . . . 183Figure 10.3 Recursive property—application. . . . . . . . . . . . . . . . . . . . 184Figure 10.4 Recursive property—further nuances I . . . . . . . . . . . . . . . 185Figure 10.5 Recursive property—further nuances II . . . . . . . . . . . . . . . 185Figure 10.6 Recursive property—mutually recursive . . . . . . . . . . . . . . 186Figure 11.1 .triggered—end point of a sequence . . . . . . . . . . . . . . . . . 188Figure 11.2 .triggered with overlapping operator . . . . . . . . . . . . . . . . . 189Figure 11.3 .triggered with non-overlapping operator . . . . . . . . . . . . . . 190Figure 11.4 .matched—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Figure 11.5 .matched with non-overlapping operator . . . . . . . . . . . . . . 197Figure 11.6 .matched—overlapped operator . . . . . . . . . . . . . . . . . . . . 197Figure 11.7 .matched—application . . . . . . . . . . . . . . . . . . . . . . . . . . 198Figure 12.1 ‘expect’—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202Figure 12.2 ‘expect’—error conditions . . . . . . . . . . . . . . . . . . . . . . . . 203Figure 13.1 ‘Assume’ and formal verification . . . . . . . . . . . . . . . . . . . 206Figure 14.1 Embedding concurrent assertions in procedural code . . . . . 217Figure 14.2 Concurrent assertion embedded in procedural code is

non-blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218Figure 14.3 Embedding concurrent assertions in procedural

code—further nuances . . . . . . . . . . . . . . . . . . . . . . . . . . 219Figure 14.4 Calling subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Figure 14.5 Calling subroutines—further nuances . . . . . . . . . . . . . . . . 223Figure 14.6 Application: calling subroutines and local variables . . . . . . 224Figure 14.7 Sequence as a formal argument . . . . . . . . . . . . . . . . . . . . 225Figure 14.8 Sequence as an antecedent . . . . . . . . . . . . . . . . . . . . . . . 226Figure 14.9 Sequence in procedural block sensitivity list . . . . . . . . . . . 227Figure 14.10 Sequence in ‘sensitivity’ list . . . . . . . . . . . . . . . . . . . . . . 228Figure 14.11 Application: building a counter using local variables . . . . . 229Figure 14.12 Variable delay—problem statement . . . . . . . . . . . . . . . . . 230Figure 14.13 Variable delay—solution. . . . . . . . . . . . . . . . . . . . . . . . . 231Figure 14.14 Blocking action block. . . . . . . . . . . . . . . . . . . . . . . . . . . 232Figure 14.15 Blocking versus non-blocking action block . . . . . . . . . . . . 233Figure 14.16 Multiple implications in a property. . . . . . . . . . . . . . . . . . 234Figure 14.17 Subsequence in a sequence—clock inference . . . . . . . . . . . 236Figure 14.18 Subsequence in a sequence . . . . . . . . . . . . . . . . . . . . . . . 236Figure 14.19 Cyclic dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Figure 14.20 Refinements on a theme . . . . . . . . . . . . . . . . . . . . . . . . . 238Figure 14.21 Simulation performance efficiency . . . . . . . . . . . . . . . . . . 238Figure 14.22 Assertion without implication operator . . . . . . . . . . . . . . . 239Figure 14.23 Assertion resulting in vacuous pass . . . . . . . . . . . . . . . . . 240

List of Figures xxxi

Figure 14.24 Assertion with ‘cover’ for PASS . . . . . . . . . . . . . . . . . . . 242Figure 14.25 Empty match [*m] where m = 0 . . . . . . . . . . . . . . . . . . . 243Figure 14.26 empty match—example . . . . . . . . . . . . . . . . . . . . . . . . . 244Figure 14.27 empty match example—II . . . . . . . . . . . . . . . . . . . . . . . . 245Figure 14.28 Empty sequence. Further rules . . . . . . . . . . . . . . . . . . . . . 245Figure 15.1 Asynchronous assertion—problem statement . . . . . . . . . . . 248Figure 15.2 Asynchronous assertion—problem statement analysis

continued . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249Figure 15.3 Asynchronous assertion—solution . . . . . . . . . . . . . . . . . . 250Figure 16.1 $changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257Figure 17.1 LAB1: ‘bind’ assertions. Problem definition . . . . . . . . . . . 306Figure 17.2 LAB3: Synchronous FIFO: problem definition. . . . . . . . . . 313Figure 17.3 LAB4: counter: problem definition. . . . . . . . . . . . . . . . . . 322Figure 17.4 LAB5: data transfer protocol: problem definition . . . . . . . . 329Figure 17.5 LAB6: PCI protocol: problem definition . . . . . . . . . . . . . . 337Figure 18.1 LAB1: ‘bind’ assertions (answers) . . . . . . . . . . . . . . . . . . 344Figure 18.2 LAB1: Q&A on ‘no_implication’ operator (answers) . . . . . 345Figure 18.3 LAB1: Q&A on ‘implication’ operator (answers) . . . . . . . . 346Figure 18.4 LAB1: Q&A on ‘overlap’ operator (answers) . . . . . . . . . . 349Figure 18.5 LAB1: Q&A on ‘non-overlap’ operator (answers) . . . . . . . 350Figure 18.6 LAB3: FIFO: answers . . . . . . . . . . . . . . . . . . . . . . . . . . 353Figure 18.7 LAB4: counter: answers . . . . . . . . . . . . . . . . . . . . . . . . . 355Figure 18.8 LAB5: data transfer bus protocol: answers . . . . . . . . . . . . 357Figure 18.9 LAB6: PCI protocol: answers . . . . . . . . . . . . . . . . . . . . . 359Figure 19.1 Assertion based verification (ABV) and functional

coverage (FC) based methodology . . . . . . . . . . . . . . . . . . 363Figure 19.2 Assertions and coverage closed loop verification

methodology—I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Figure 19.3 Assertion and functional Coverage closed loop

verification methodology—II . . . . . . . . . . . . . . . . . . . . . . 365Figure 20.1 ‘covergroup’ and ‘coverpoint’—basics . . . . . . . . . . . . . . . 369Figure 20.2 ‘coverpoint’—basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 370Figure 20.3 ‘covergroup’/‘coverpoint’ example . . . . . . . . . . . . . . . . . . 371Figure 20.4 ‘bins’—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373Figure 20.5 ‘covergroup’/‘coverpoint’ example with ‘bins’ . . . . . . . . . . 374Figure 20.6 ‘covergroup’—formal and actual arguments. . . . . . . . . . . . 375Figure 20.7 ‘covergroup’ in a SystemVerilog class (courtesy LRM

1800-2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377Figure 20.8 Multiple ‘covergroup’ in a SystemVerilog class . . . . . . . . . 377Figure 20.9 ‘cross’ coverage—basics . . . . . . . . . . . . . . . . . . . . . . . . . 379Figure 20.10 ‘cross’ coverage—simulation log . . . . . . . . . . . . . . . . . . . 380Figure 20.11 ‘cross’—example (further nuances) . . . . . . . . . . . . . . . . . 381Figure 20.12 ‘cross’ example—simulation log . . . . . . . . . . . . . . . . . . . 381Figure 20.13 ‘bins’ for transition coverage . . . . . . . . . . . . . . . . . . . . . . 382

xxxii List of Figures

Figure 20.14 ‘bins’—transition coverage further features . . . . . . . . . . . . 383Figure 20.15 ‘bins’ for transition—example with simulation log . . . . . . . 384Figure 20.16 Example of PCI cycles transition coverage . . . . . . . . . . . . 385Figure 20.17 wildcard ‘bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386Figure 20.18 ‘ignore_bins’—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 387Figure 20.19 ‘illegal_bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388Figure 20.20 ‘binsof’ and ‘intersect’ . . . . . . . . . . . . . . . . . . . . . . . . . . 389Figure 21.1 Functional coverage—performance implication . . . . . . . . . 392Figure 21.2 Application—have you transmitted all different lengths

of a frame? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394Figure 22.1 Coverage options—reference material . . . . . . . . . . . . . . . . 396Figure 22.2 Coverage options—instance specific—example . . . . . . . . . 397Figure 22.3 Coverage options—instance specific per-syntactic

level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398Figure 22.4 Coverage options type specific per syntactic level . . . . . . . 399Figure 22.5 Coverage options for ‘covergroup’ type

specific—comprehensive example . . . . . . . . . . . . . . . . . . 400Figure 22.6 Predefined coverage system tasks and functions. . . . . . . . . 401

List of Figures xxxiii

List of Tables

Table 2.1 PCI read protocol test plan by functional verification team . . . 23Table 2.2 PCI read protocol test plan by design team . . . . . . . . . . . . . . 24Table 2.3 Conventions used in this book . . . . . . . . . . . . . . . . . . . . . . . 28Table 6.1 Concurrent assertion operators . . . . . . . . . . . . . . . . . . . . . . . 82

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