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System Verilog Assertions SE303b – Conception des systèmes sur puces (SoC) Ulrich Kühne 30/11/2018
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System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

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Page 1: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

System Verilog AssertionsSE303b – Conception dessystèmes sur puces (SoC)

Ulrich Kühne30/11/2018

Page 2: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Outline

Introduction

Sequences

Strength & Infinity

Advanced Operators

2/29 SE303b Ulrich Kühne 30/11/2018

Page 3: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

A Practical Verification Language?

LTL and CTL have emerged from theoretical interestBound to specific complexity classes andequivalence notionsNested CTL/LTL properties are hard to understandSubtle semantic differences

F X p ≡ X F p ≡ AX AF p 6≡ AF AX p

F G p 6≡ AF AG p

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Page 4: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

System Verilog Assertionsmodule monitor( foo.MONITOR I );

property slave_data_notunknown_when_ready;@(posedge I.clk)

I.ready | -> $isunknown(I.s) == 0;endproperty

assert_slave_data_notunknown_when_ready: assert property (slave_data_notunknown_when_ready)else $error("%m: ready is asserted but data from slave is non valid");

property slave_ready_until_valid;@(posedge I.clk)

$rose(I.ready) | -> I.ready throughout I.valid [->1]; //ou I.ready [*0:$] ##1 I.valid;endproperty

assert_slave_ready_until_valid: assert property(slave_ready_until_valid)else $error("%m:slave’s ready must be held until valid is set");

property slave_data_held_when_ready;bit [7:0] s;@(posedge I.clk) disable iff (I.nrst == 0)

(I.ready && !I.valid , s = I.s) | => s == I.s; //ou $stable(I.s);endproperty

assert_slave_data_held_when_ready: assert property(slave_data_held_when_ready)else $error("%m: data must be held stable when slave is ready");

endmodule

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Page 5: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

System Verilog Assertions

Industrial standard(IEEE 1800-2012)Embedded in SystemVerilog HDLSuperset of LTLSequences and regular expressionsSupports simulation and formalverification

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Page 6: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Basic Property Structure

// basic property structureproperty foo;

@(posedge clk) disable iff (rst)expr;

endproperty // foo

// verification directivesassert_foo: assert property(foo);assume_foo: assume property(foo);

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Page 7: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Past Values and Value Changes

Value of a signal in the preceding cycle:$past(a)

Shortcut for rising edge:$rose(a) is equal to !$past(a) && a

Shortcut for falling edge:$fell(a) is equal to $past(a) && !a

Shortcut for stable signal:$stable(a) is equal to $past(a) == a

Shortcut for changed signal:$changed(a) is equal to $past(a) ^ a

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Page 8: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Outline

Introduction

Sequences

Strength & Infinity

Advanced Operators

8/29 SE303b Ulrich Kühne 30/11/2018

Page 9: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Sequentially ExtendedRegular Expressions (SERE)

Typical use case: Chains of eventsAwkward to describe in LTLIntuitive description by regular expressionsSyntax resembles known languages (bash, Python, . . . )

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Page 10: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Sequences

a ##1 b ##2 c

clk

a

b

c

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

Find all matching cycles. . .

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Page 11: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Variable Delay

a ##[1:3] b

clk

a

b

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

Find all matches. . .

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Page 12: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Repetition

Consider sequence:a ##1 a ##1 a ##1 b ##1 b

Shortcut for repeating sequence:a[*3] ##1 b[*2]

Variable repetition:a[*1:3]

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Page 13: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Assertion Semantics

property foo;@(posedge clk)a ##[1:3] b;

endproperty

assert_foo: assert property(foo);

What are we actually verifying here?Sequence a ##[1:3] b must match in all cyclesImplicit always operator (G in LTL)

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Page 14: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Suffix Implication

// suffix implicationfoo ##1 bar |-> pof ##[1:3] mop

clk

foo

bar

pof

mop

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Page 15: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Non-Overlapping Suffix Implication

// non-overlapping suffix implicationfoo ##1 bar |=> pof ##[1:3] mop

clk

foo

bar

pof

mop

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Page 16: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Example

Prop. 1: “Whenever signal rdy is asserted, it muststay asserted for 5 clock cycles”

property rdy_stable;@(posedge clk)!rdy ##1 rdy |=> rdy[*4];

endproperty

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Page 17: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Outline

Introduction

Sequences

Strength & Infinity

Advanced Operators

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Page 18: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Infinity

Special symbol $ for infinity

Can be used in variable delay and repetition

a[*] is a shortcut for a[*0:$]

a[+] is a shortcut for a[*1:$]

Exercise: What is the meaning of this sequence?

(start ##1 busy[*] ##1 done)[+]

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Page 19: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Infinity

Prop. 2: “Whenever signal busy is asserted,rdy must be asserted eventually.”

property rdy_after_busy;@(posedge clk)busy |-> ##[0:$] rdy;

endproperty

This property is wrong!

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Page 20: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Infinity

This assertion has no counter-example

busy |-> ##[0:$] rdy

clk

busy

rdy

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Page 21: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Strength

Use of strong(...) operatorEnforces a match before the end of evaluation(which is infinity in formal verification)Weak and strong versions of many operators

A1: assert property (busy |-> ##[0:$] rdy);A2: assert property (busy |-> strong( ##[0:$] rdy ));A3: assert property (busy |-> eventually rdy);A4: assert property (busy |-> s_eventually rdy);

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Page 22: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Until

a until b

a s_until b

clk

a

b

a until_with b

a s_until_with b

clk

a

b

Attention: Weak until operators allow infinite wait!

clk

a

b

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Page 23: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Outline

Introduction

Sequences

Strength & Infinity

Advanced Operators

23/29 SE303b Ulrich Kühne 30/11/2018

Page 24: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Goto Repetition

Prop. 3: “After signal write is serviced by ack,signal ready should be asserted.”

(write ##1 !ack[*] ##1 ack) |=> ready

Prop. 4: “After signal wr_burst is serviced twice by ack,signal ready should be asserted.”

(wr_burst ##1 !ack[*] ##1 ack ##1 !ack[*] ##1 ack) |=> ready

(wr_burst ##1 (!ack[*] ##1 ack)[*2] ) |=> ready

wr_burst ##1 ack[->2] |=> ready

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Page 25: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Goto Repetition

wr_burst ##1 ack[->2] |=> ready

clk

wr_burst

ack

ready

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Page 26: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Within / Throughout

Prop. 5: “Throughout the whole burst cycle, the signalready should be low.”

!ready throughout (wr_burst ##1 ack[->2])

Prop. 6: “Within a granted bus cycle, a write transactionshould be completed.”

(write ##1 ack[->1]) within (gnt ##1 !gnt[->1])

This property is (probably) wrong!

(write ##1 ack[->1] ##1 1) within (gnt ##1 !gnt[->1])

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Page 27: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Local Variables

Prop. 7: “After a completed write transaction, the value ofwdata is stored in the register entry.”

clk

write

wdata 0xFFE1

ack

entry 0xFFE1

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Page 28: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Local Variables

Prop. 7: “After a completed write transaction, the value ofwdata is stored in the register entry.”

property foo;logic[15:0] tmp;@(posedge clk)(write, tmp = wdata) ##1 ack[->1] |=>

entry == tmp;endproperty

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Page 29: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

Practical Exercise

Formalization of a textual specificationImplementation & verification with qformalSee exercise on websitehttps://sen.enst.fr/verification-formelle

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https://sen.enst.fr/verification-formelle
Page 30: System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

References I

Cerny, E., Dudani, S., Havlicek, J., and Korchemny, D. (2015).SVA: The Power of Assertions in SystemVerilog.Springer.

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