Introduction System-on-Chip Pietro Andreani Dept. of Electrical and Information Technology Lund University, Sweden Overview • Modern MOS processes • High-k + metal gate 45nm CMOS process from Intel • Moore’s law • Interconnects P. Andreani – System-on-Chip Introduction 2 • International Technology Semiconductor Roadmap (ITRS) • more Moore and more than Moore • Packaging The march of materials (potential) P. Andreani – System-on-Chip Introduction 3 • CMOS is not simple any more • CMOS is not cheap any more (but, maybe/hopefully, cheaper?) MOS with polysilicon gate P. Andreani – System-on-Chip Introduction 4 • Depleted region in polysilicon gate decreased “on” current, increased “off” current • SiO 2 dielectric cannot be too thin, otherwise tunneling current through the gate becomes unacceptably large This and most following slides from Intel documents
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Introduction
System-on-Chip
Pietro AndreaniDept. of Electrical and Information Technology
Lund University, Sweden
Overview
• Modern MOS processes• High-k + metal gate 45nm CMOS process from Intel
• Moore’s law
• Interconnects
P. Andreani – System-on-Chip Introduction 2
• International Technology Semiconductor Roadmap (ITRS)• more Moore and more than Moore
• Packaging
The march of materials
(potential)
P. Andreani – System-on-Chip Introduction 3
• CMOS is not simple any more• CMOS is not cheap any more (but, maybe/hopefully, cheaper?)
MOS with polysilicon gate
P. Andreani – System-on-Chip Introduction 4
• Depleted region in polysilicon gate decreased “on” current, increased “off” current
• SiO2 dielectric cannot be too thin, otherwise tunneling current through the gate becomes unacceptably large
This and most following slides from Intel documents
MOS with polysilicon gate - problems
P. Andreani – System-on-Chip Introduction 5
• SiON scaling running out of atoms!• Dielectric cannot be too thin, otherwise tunneling current through the gate
becomes unacceptably large
• Polysilicon depletion limits inversion
New HK+MG MOS device
P. Andreani – System-on-Chip Introduction 6
Advantages of HK+MG
P. Andreani – System-on-Chip Introduction 7
Polysilicon removed after annealing
P. Andreani – System-on-Chip Introduction 8
• A problem with metal gates is that they would melt during annealing (however, there is intense research to avoid the so-called “gate last” process)
Some process details
P. Andreani – System-on-Chip Introduction 9
• Hafnium-based high-k dielectric, dual-metal gate, strained silicon• High-k first, metal-gate last (metal gate deposition after high-T anneals)• Strained silicon process; transistor mask count same as 65nm• Gate leakage reduce 1000x for PMOS, 25x for NMOS
Strained silicon
P. Andreani – System-on-Chip Introduction 10
• Photos from 65nm CMOS • Strained silicon improves mobility of charge carriers
Device photo (45nm CMOS)
P. Andreani – System-on-Chip Introduction 11
• 35nm minimum gate length• 160nm contacted gate pitch• 20% Ge in SiGe
Comparison
P. Andreani – System-on-Chip Introduction 12
At an earlier stage (HK dielectric)
P. Andreani – System-on-Chip Introduction 13
From G. Moore, ISSCC ‘02
Device scaling – keeping Moore’s law alive and well
P. Andreani – System-on-Chip Introduction 14
• Contacted gate pitch of 160nm 0.7x scaling continues