The EDA Lab System in Package and Chip-Package-Board Co- Design Progress Report Jia-Wei Fang, Kuan-Hsien Ho, and Yao-Wen Chang The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering National Taiwan University August 14, 2008 1
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System in Package and Chip-Package-Board Co-Design
System in Package and Chip-Package-Board Co-Design. Progress Report Jia-Wei Fang, Kuan-Hsien Ho, and Yao-Wen Chang. The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering National Taiwan University August 14, 2008. Outline. - PowerPoint PPT Presentation
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The EDA Lab
System in Package and Chip-Package-Board Co-Design
Progress Report
Jia-Wei Fang, Kuan-Hsien Ho, and Yao-Wen Chang
The Electronic Design Automation Laboratory
Graduate Institute of Electronics Engineering
National Taiwan University
August 14, 2008
1
2
Outline
․ System in Package Introduction Problem Formulation Extensions
․ Placement and Routing for Chip-Package-Board Co-Design Considering Differential Pairs
Introduction Problem Formulation Placement and Routing Algorithm Experimental Results Conclusions
․ Schedule
System in Package (SiP)
․ Can get higher deign performance and is easier for implementation than that of Systems on Chip (SoC)
․ Place multiple dies/flip-chips on the same package Stack specific dies Locate fingers around each group of dies
․ Connect nets among dies, flip-chips, and the package
3
Die
Bonding wire
Finger
Ball
BGA package
Package wire
StackedDies
Through silicon via
Metal layersFlip-chip
Ball
Pad
SiP Problem Formulation
․ Problem: Given dies with pads, flip-chips with balls, a PGA/BGA package
with pins/balls, a netlist containing pre- and free-assignment nets, and design constraints
Place dies, corresponding fingers of dies, and flip-chips on the PGA/BGA package, then assign signals and route wires among dies, flip-chips, and the package
․ Objectives: Maximize routability Minimize total wirelength under the design constraints
4
Extensions
․ Package placement to Multiple dies placement
․ Ball arrangement to Finger arrangement
․ Signal assignment for fingers and pins to Signal assignment for pads and pins Pre-assignment and free-assignment signal routing
․ Differential-pair routing to Other routing constraints
5
6
Outline
․ System in Package Introduction Problem Formulation Extensions
․ Placement and Routing for Chip-Package-Board Co-Design Considering Differential Pairs
Introduction Problem Formulation Placement and Routing Algorithm Experimental Results Conclusions
․ Schedule
7
Chip-Package-Board Co-Design
DieBonding wireFinger
BGAPinBump ball
PCB
PCB wire
Package wire
Metal layers
Top metal layer
Differential Pairs
․ Differential-Pair (DP) routing is a popular technique for high-speed PCB designs due to its noise immunity, EMI reduction, and ground bounce insensitivity
․ However, the signal pair should be transmitted in close proximity with similar wirelength to simultaneously absorb the noise
8
Problem of Chip-Package-Board Co-Design
․ Problem: Given a die with fingers, a placement of components with pins, the
numbers of BGA and PCB metal layers, and a netlist Generate and place the package and then assign signals and route
wires from component pins to fingers via bump balls, considering differential pairs
․ Objectives: Maximize routability Minimize package size, total wirelength, and the number of vias
9
10
Design Flow
Global Routing Detailed Routing
Routing Result Output
No
Yes
Layer Assignment
CPB Placement
Any-Angle RoutingRouting Network Construction
Package and PCB Routing
Bump-Ball Arrangement
Package Placement
Routed & Minimized?
Die (Fingers), Components (Pins)# Layers, Netlist, Design Rules
11
Bump-Ball Arrangement
․ Determine package size (can get the minimum rectangle size)
․ # bump balls of (r-1) rings < # fingers < # bump balls of r rings
ring r
ring r-1
Fingers
Bump ball
12
Package Placement
․ Apply linear programming (LP) to determine the location of the package
2
1
3 4
q
p r
(x1, y1)
(x2, y2)
(xc, yc)
(xp, yp)
xboundary
yboundary
c Package Center
Pin
X=0
y=0
13
Global Routing (1/2)
․ Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball
․ Apply LP to do global routing Multi-sources Single sink
f1
f2
f3
b4
b5
b6
b1
b2
b3
BGAPCB ChipPre-assigned signals Only given a netlist
b
a
c
s2
s1
Use s2 to choose only the bump pads for Type 1
t
Netlist: 1, 2, 3
Finger
es1_p1
Ball
Pin
p1
p2
na
14
Global Routing (2/2)
․ Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball
․ Apply LP to do global routing Multi-sources Single sink
f1
f2
f3
b4
b5
b6
b1
b2
b3
Pin
p1
p2
BGAPCB Chip
g
h
s2
t
Netlist: 1, 2, 3
s1
Finger
Only given a netlist
․ The signal pair should be transmitted in close proximity and similar wirelength
․ Apply LP to route the differential pairs DP constraints
Σ Σ Ψi_j(ei_g - ej_h) = 0
Σ Σ Ψi_jΨg_h(ei_g - ej_h) = 0
Differential-Pair Routing
15
34
34
34
34
s3
s4
DP node
34
34
34
34
s3
s4
Bounding box
16
Layer Assignment
․ In global routing, integrate all metal layers into one layer
․ Model the layer assignment as a flow network to distribute nets into each layer after global routing
1
3
2
1
3
2
BGA Chip
Finger
Ball
1
3
2
l
r
Layer 1
Layer 2
ts
Flow network
es2
es1 elt
ert
e1l
e2r
Can only route 2 wires in one layer
17
Detailed Routing (1/2)
․ The PCB routing does not allow any routing path with an acute angle
The router should check every turning point to avoid any acute angle
Once an acute corner is detected, the two adjacent net segments can be cut off to generate two obtuse angles