System Design with CoWare N2C - Overview
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System Design with CoWare N2C - Overview
2
Agenda
Overview– CoWare background and focus– Understanding current design flows– CoWare technology overview– Business & design results
Lunch
Technical introduction to CoWare N2C– Demos– Technical basics
Conclusion and Q&A
3
CoWare background Headquartered in Silicon Valley
– American, European, and Asian offices
– Growing quickly
– EDA-experienced senior management
– Venture capital funding in 1997
Spun-off from IMEC in 1996– Technology in development since 1992
– Ongoing R&D relationship with IMEC
CoWare: The most complete tools and methodologies for system design, hardware-software co-design and IP re-use
4
Convergence of Computing, Communication,
& Consumer
}
}Software
Hardware
Time -to- MarketVolumeRevenueProfits
EmbeddedMemory
AnalogCircuitry
DigitalLogic
EmbeddedCPU
EmbeddedDSP
System-on-a-chip
Glue software and hardware
Market Focus: system design for SOC
5
Complexity and convergence trends
64-bit RISCSPARC, MIPS R4xxx, MIPS VR10xxx...
32-bit RISCARM7 & 9, ST-50/SH-5,SH-3, MIPS R3000…
16-bit microM-core, x86…
8-bit micro68HC05, 68HC11…
AutomotiveControl
Industrial
Mil/AeroConsumerConsumer
ComputingComputing
CommunicationsCommunications"C3""C3"
ApplicationsApplications
ConsumerConsumer
ComputingComputing
CommunicationsCommunications
"C3""C3"ApplicationsApplications
105 107 108 109106
100
103
102
101
104
Throughput
(Clock
Cycles)
Cycles per
Sample
6
Americas
Europe
Asia
Consumer CommunicationSemiconductor ---- Electronic Systems ----
SOC
Key customers
Matsushita
7
OriginalProductTarget
TargetRepainted
to fitReality
Current system design process...
System LevelIntegration
SoftwareDevelopment
HardwareDesign
IPSelectionSystem
Architecture
Textual Specification
8
ProductAlways
On Target
ExecutableImplementableSpecification
Design&
Animation
IP
MappingOnto
Architecture
Co-Design&
Co-simulation
SoftwareOptimizationHardwareDesign
Co-Implementation&
Co-verification
Language: C augmented withStructure & Concurrency
Style: separation ofBehavior & Communication
Designing with CoWare N2C™
Napkin-to-Chip™
1st t
ime
right
In ½
the
time
!
Enables:Interface Synthesis™
9
Impact of system design with CoWare N2C– Organizational impact - customer relationship
Higher-level sign-off : above RT-level Availability of virtual prototypes for application developers / customers Customer commitment moves forward in time
Customer request
Marketing/Architects
HW designSW developmentHW/SW integration
Design Implementation
Customercommitment
Customer request
Marketing/Architects
HW designSW developmentHW/SW integration
Design
VirtualPrototype
Customercommitment
Implementation
Source: STMicroelectronics
10
"Chip-out" - the HW C Virtual Prototype– A software development platform
– Multi-level reference design to… Assess HW in end-application quickly Map system functionality onto HW platform Analyze architectures Co-verify the implementation
Two different CoWare N2C “use models” "System-down" - the Napkin-to-Chip™ design flow
– Executable and implementable specifications
– HW-SW Co-design
– Interface Synthesis
– Architecture Analysis
System ASSP
System ASIC
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HW: what CoWare does
• Co-execute with Co-execute with HDL simulators HDL simulators • HDL IP importHDL IP import
• Executable spec.Executable spec.• Golden systemGolden system testbenchtestbench• Multiple model Multiple model levelslevels
AboveRTL
BelowRTL
Verification Design
• Synthesis Synthesis (e.g. Synopsys Design (e.g. Synopsys Design Compiler)Compiler)• Deep-sub-micron Deep-sub-micron analysisanalysis• Physical designPhysical design
and doesn't do
• Executable and Executable and implementable implementable specificationspecification• Interface SynthesisInterface Synthesis• RTC & RTC2HDLRTC & RTC2HDL
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• Import and profile Import and profile assembler codeassembler code• Verify with software Verify with software development toolsdevelopment tools
• Executable spec.Executable spec.• Golden systemGolden system testbenchtestbench• Multiple processor Multiple processor model levelsmodel levels
C-level
Assemblerlevel
Verification Design
• CompilersCompilers• RTOS synthesis RTOS synthesis
and doesn't do
• Executable and Executable and implementable implementable specificationspecification• Interface SynthesisInterface Synthesis• Integrate with RTOSIntegrate with RTOS• Link and compileLink and compile
SW: what CoWare does
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Make a 3-D change...
Systemlevel
Implementationlevel
Verification Design
HW
SW
Inte
rfa
ce
Sy
nth
es
is
Vir
tua
l P
roto
typ
es
Execu
table
imple
men
table
spec
.
…and increase
interactivity throughout the design
flow!
Continuous refinement Multi-level models
AboveRTL
BelowRTL
Verif.Design
C-level
Assemblerlevel
Verif. Design
"Traditional" HW-SW Co-verification
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CoWare Methods & Tools
CoWare Methods & Tools
System-on-a-chip success
Digital Designers
NORWAY
Digital Designers
NORWAY
Foundry
System IntegrationBELGIUM
Foundry
System IntegrationBELGIUM
Software Developers
FRANCE
Software Developers
FRANCE
EndCustomers
EndCustomers
A PowerlineModem
System Company
System DefinitionSWITZERLAND
System Company
System DefinitionSWITZERLAND
UtilitiesUtilities
Source: Alcatel Microelectronics
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You and your customers can...
Old waymisses the target
Use executable specifications to– Share information without ambiguity– Get SW and HW teams working together
Use interface synthesis to– Explore design architecture alternatives
– Ease design of product derivatives or new product generations
Use virtual prototypes to – Review & exchange product concepts – Get HW out of the SW critical path
CoWare Napkin-to-Chip
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It’s time to move up again !
Netlist
Netlist
70 70 82 82 88 88 97 97
DesignRTL
Mask Mask
Netlist Netlist
Schematic Netlist
RTL RTL
CoWare N2CC-Based
System-LevelDesign
Implementation
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