System and SoC Verification Trends · System and SoC Verification Trends Nick Heaton, Senior Solution Architect Verification Futures 19th stNov (Windsor), 21 Nov (Grenoble), 22nd

System and SoC Verification Trends

Nick Heaton, Senior Solution Architect

Verification Futures

19th Nov (Windsor), 21st Nov (Grenoble), 22nd Nov (Munich)

2 © 2012 Cadence Design Systems, Inc. All rights reserved.

Past 10 years: IP bottom-up verification approach led by the Specman/e/eRM MDV solution

Metric Driven Verification Environment

Automatic Stimulus

Generation

Data and Assertion Checkers

BFM Signal Layer

Coverage Monitor

Stimulus Sequences

Customer’s Application Specific Components CPU subsystem

3

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Gr

ap

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cs

C

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High speed, wired interface peripherals

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Other peripherals

S

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A MI

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H

D

MI

W

L

A

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Low-speed peripheral

subsystem

Low speed peripherals

P

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Applica

tion

Acceler

ators

…

A

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…

Fabric

CPU

I $

D $

CPU

I $

D $

L2 cache

USB3.0

3

.

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P

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2

.

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PCIe

Gen

2,3

PHY

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subsystem


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Applica

tion

Acceler

ators

…

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…

Fabric

CPU

I $

D $

CPU

I $

D $

L2 cache

USB3

.0

3

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2

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tion

Acceler

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S

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CPU

I $

D $

CPU I $

D $

L2 cache

USB3.0

3

.

0

P

H

Y

2

.

0

P

H

Y

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r

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SoC XYZ

Design IP

e or SystemVerilog

RTL Simulator

Comprehensive IP and Sub-

System verification: should

work in ANY SoC context


Paradigm Shift In the Market

Ubiquity of software

Move to Standards-based protocols and IPs

Increasing complexity and # of IP’s to be integrated

Application / end-user driven requirements

Shrinking time-to-money

Mixed Signal and Low Power Verification Complexity

Debug consuming over 50% of verification task

Design

Trends

Shift from:

Serial HW/SW

Development

To:

Parallel HW/SW

Development

Shift from:

IP Creation

To:

SoC Integration

Debug is a Major Bottleneck in Verification

4

• Customers spending >50% verification effort in Debug

• Verification complexity requires advanced class and macro debug

• Debug methodology shift from signals Class / Transactions

50%

Verification

efforts

5% 10%

25%

10% Test planning

Test creation

Test execution (formal + sim + HW)

Debug

Coverage analysis


From serial to parallel HW/SW development

Block Chip Prototype Silicon

lab test Field test

ROM

Content Drivers / RTOS / Applications

Diagnostics

& Firmware HW/SW

Spec

Serial HW->SW Development

Block Chip Prototype Silicon

lab test Field test

ROM

Content Drivers / RTOS / Applications

Diagnostics

& Firmware HW/SW

Spec

Time to market

advantage of 6 to

9 months

Parallel HW->SW Development

Integrate HW/SW Early and Often

HW designed in SW context

Software exposed to Spec changes


HW/SW Requires High Performance Platforms

SDK

•Highest speed

•Ignore hardware

•Earliest in the flow

Virtual Platform

•Almost at speed

•Less accurate (or slower)

•Before RTL

•Great to debug (but less detail)

•Easy replication

RTL Simulation

•KHz range

•Accurate

•Excellent HW debug

•Little SW execution

Acceleration Emulation

•MHz Range

•RTL accurate

•After RTL is available

•Good to debug with full detail

•Expensive to replicate

FPGA Prototype

•10’s of MHz

•RTL accurate

•After stable RTL is available

•OK to debug

•More expensive than software to replicate

Prototyping Board

•Real time speed

•Fully accurate

•Post Silicon

•Difficult to debug

•Sometimes hard to replicate


• Multiple disconnected SoC simulation environments – Virtual Platform, RTL Sim, HW Acceleration/Emulation, FPGA

Prototype, Post Silicon

• Reducing SoC integration time and effort – Integrating many design IPs and SW components

– Requires significant time and effort to verify integration

– High cost to re-integrate & re-verify changes

– Debug is a major challenge to isolate the root cause

– Verification effort for SoC derivatives is too high

• Verifying that SoC can support required SW applications – Increased software content to develop, integrate, & verify

– SoC must be architected up front to support SW Use Cases

– Must verify against functional, power & performance requirements

Main Challenges Integrating and Verifying Large-Scale Multicore SoCs


SoC/SW Integration Verification Vision

System

Development

Suite

Links to Post-silicon

Environment

System Integration Automation

Application-Driven System Verification

Verification Planning & Management

System VIP

Simulation

VIP

Accelerated

VIP

Speed

Bridge

Virtual

Bridge

Unified System Debugging


System and SoC Verification Trends · System and SoC Verification Trends Nick Heaton, Senior Solution Architect Verification Futures 19th stNov (Windsor), 21 Nov (Grenoble), 22nd

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