Synthesizing and Testing LEON on ADM-XRC

Synthesizing and Testing LEON on

ADM-XRC

Anup Gangwar

Embedded Systems GroupDepartment of Computer Science & Engineering

IIT Delhi

Slide Slide 22ESG Weekly SeminarESG Weekly Seminar http://www.cse.iitd.ac.in/esprojecthttp://www.cse.iitd.ac.in/esproject

Presentation Outline

Introduction LEON processor architecture and development

toolkit ADM-XRC board architecture Why it took so long? Interfacing ZBT SRAM Building external hardware interface Booting LEON From here Acknowledgements


Introduction

What is LEON? A Sparc V8 compliant soft processor core No support for paging Has been synthesized and tested on many FPGA platforms Mainly written by Jiri Gaisler at European Space Agency Supporting toolkit (compiler, assembler, simulator) available RTEMS successfully ported to LEON with support for n/w

interface

How is this relevant to our work? Real performance/cost nos. give valuable feedback to our tools Prototyping adds credibility to our work System design experience lets us identify new problems Working demonstrations help motivate new people






The LEON Processor Architecture

FPU

Co-Proc

LEON IUPCI

User I/O

Timers/UARTs/I/O Ctrl/IRQ CtrlMemory Controller

PROM/RAM/I/O

AHB Controller

AHB/APB Bridge

AMBA AHB

AMBA APB

I-Cache D-Cache


LEON Development Tools Suite

C-CodeRTEMS Library

GCC - Ported GNU Cross Compiler System

TSIM - LEON FunctionalSimulator

Modify C Code

ObjCopy - Ported GNU Binutils System

SREC File - Containing Stripped Relocatable Symbols

Y

N Performance and Functionality Okay?


Motorola S-Records Format

S<type><length><address><data....><checksum> type => in the range [1-7]length => length of (address + data + checksum)

in hexaddress => [4-6] hex characters (16-32 bit

address)data => each hex pair represents one memory

byte

S3 => data record with 32-bit addressesS7 => Ending record for S3 records, address is the

jump address for starting execution






ADM-XRC Architecture

XCV800-BG560-6

34

I/O

pin

s o

n S

CS

I-II

s

tyle

c

on

ne

cto

r

PLX 9080

HOST PCI Bus

Clock Gen.

RAM0 RAM1 RAM2 RAM3

ADM-XRC


ADM-XRC Software API

Supported platforms are GNU-Linux and Windows NT

API Supports: Functions for configuring the Virtex device over PCI DMA mode for data transfer from/to PLX-9080 Both master/slave mode supported for PLX-9080

Examples demonstrate: Simple PCI interface RAM interface with address space segregation DMA Master and slave interfaces External I/O interfaces






Why it took so long?

Inability to comprehend the problem properly Improper documentation of ZBT memory interface Improper methodology for prototyping and testing

Synthesis being used as testing vehicle which is incorrect After thorough simulation synthesis should be a one-shot

process unless the synthesis tools are buggy External H/W interface was incorrect

Unnecessary additional logic inversion Position of Rx and Tx in 9-pin and 25-pin connectors is

interchanged LEON and memory address lines were not properly

mapped LEON address lines select individual bytes! Memory word is 32 bits here hence LEON A[1:0] need to be

left free






Galvantech ZBT SRAM Interface Signals

Galvantech 512K x 36bits

CLK

CKE#

R/W#

CE#

OE#

ADV/LD#

BW[a-d]#

Address

Data

LEGEND

CLK Clock In

CKE Sync. Clock Enable

CE Chip Enable

OE Output Enable

R/W# Read/Write Select

ADV/LD# Advance/Load

BW[a-d]# Byte Write Enables

Address Address Input

Data Data Input/Output


ZBT SRAM Read Timing Diagram

CLK

OE#

ADV/LD#

Address

Data

R/W#DON’T CARE

DON’T CARE


ZBT SRAM Write Timing Diagram

CLK

OE#

ADV/LD#

Address

Data

R/W#

DON’T CARE

DON’T CARE

DON’T CARE


LEON SRAM Read Timing Diagram

CLK

RAMOEN

RAMSN

Address

Data


LEON SRAM Write Timing Diagram

CLK

RWEN

RAMSN

Address

Data




toolkit ADM-XRC board architecture Why it took so long? Interfacing memory Building external hardware interface Booting LEON From here Acknowledgements


External Hardware Interface

Why is external hardware circuitry needed? Virtex SelectIOTM supports PCI3.3, LVTTL etc. logic levels RS-232C voltage conversion required for TxD and RxD pins

Choices for interface chips Motorola MC1488/1489

– Require dual supply, +5V, ±12V– Better noise immunity but bigger circuitry– LVTTL to RS232C and RS232C to LVTTL requires two

chips Maxim Max232

– Single power supply, +5V– Each chip contains two RS232C to LVTTL and two LVTTL

to RS232C converters– Lesser noise immunity but more compact circuitry


H/W Interface Board Layout

MAX 232(RS-232C voltage level converters)

Power LED Error LED

Probe Points

Ho

st

se

ria

l p

ort

co

nn

ec

tio

ns

15

I/O

co

nn

ec

tio

ns

fro

m A

DM

-XR

C m

ap

pe

d h

ere

Po

we

r S

up

ply

Supporting Circuitry






Boot Configuration

ADM-XRC

Host Computer

BlockRAMs containing boot-prom, Register Files, Caches etc (These are instantiated not inferred)

Xilinx Virtex XCV800-BG560-6(virtex_2k_2k_blockprom)

RAM0 RAM1 RAM2 RAM3

PL

X9

08

0

Host PCI Bus (Used for configuring Virtex)

Errorn, Resetn, UART1 and UART2 ports mapped to 34 I/O pins for interface

H/W InterfaceBoard

Host Serial Port - 1(stdin/stdout)

Host Serial Port - 2(UNIX File Descriptors 2 & 3)

Onboard ZBT SSRAMs used as LEON RAMs






From Here:

Small Scope Projects: Try various hardware synthesis configurations for LEON Build S/W and H/W estimator models for LEON

Medium Scope Projects: Build a host of coprocessors for LEON Test some PCI cards with LEON-PCI Port some real applications to LEON-RTEMS Build Ethernet interface for LEON (RTEMS support is already

present)

Large Scope Projects: Extend LEON configuration for multiprocessors Customize RTEMS for a particular application/LEON

configuration






Acknowledgements

Main ideas, motivation and support Prof. M. Balakrishnan and Prof. Anshul Kumar

Co-Proc interface, Local Bus interface, Bugs in memory interface Amarjeet Singh

Debugging, Memory interface, External RS-232C hardware interface circuitry Amit Aggarwal, Puneet Wadhawan


Thank You

Synthesizing and Testing LEON on ADM-XRC

Documents

esg weekly seminarhttp

testing leon

jump address

data record

architecture xcv800bg560

data transfer fromto

io pins

new peopleslide