Elements of Synthesis from VHDL descriptions Madhav Desai Department of Electrical Engineering IIT Bombay
Elements of Synthesis from VHDL descriptions
Madhav DesaiDepartment of Electrical Engineering
IIT Bombay
What is synthesis? Conversion of a VHDL description to a
logic network Conversion not possible in real-time
e.g. A
Local conversion Each driver is mapped to an equivalent
logic network Well defined algorithm exists.
Special cases: groups of drivers mapped to equivalent logic network Ad-hoc pattern based algorithms (for e.g.
Algorithms that infer memories).
What about global equivalence? If each driver is locally converted to
equivalent logic network, does the interconnected set of VHDL drivers behave the same as the interconnected set of logic networks? In general, unlikely BUT: if VHDL description is synchronous in
nature (with global clocks), then global equivalence can be guaranteed, subject to certain conditions.
Arbitrary VHDL descriptions cannot be converted to equivalent logic networks!!!
process(...) -- variable declarationsbegin S1; S2; S3; ... Sk;end process;
The VHDL process statement
Synthesized Process StructurePriority Encoder
Priority Encoderuses Status and Value Functions
Statement synthesis template
Incoming variables
IncomingSignals
OutgoingSignalsOutgoing Variables
Logic NetworkStatusValue
Status and Value Outputs
For each signal driven from a statement, a VALUE function and a STATUS function are created
VALUE: value driven on to the signal
STATUS: validity of the value driven on to the signal
process(a,b) variable temp: bit;begin temp := a; c
IF statement
THEN ELSE
Condition
Multiplexer
process(A,B,C) Variable A: bit;Begin X := A; if(B = '1') then X := (not X); D
If (rst = '1' ) then q
Case Statementsimilar to IF
For-loop StatementUnroll
Special attention to NEXT, EXIT while unrolling.
While-loop StatementUnroll
Special attention to NEXT, EXIT while unrolling
Signal a: integer range 0 to 5;signal b,c: bit_vector(0 to 5);process(a,b)begin for i in 0 to a loop c(i)
Subprograms
Substitution in place at the point of call.
Return Statements need special attention in Function calls.
Recursion permitted if static substitution leads to finite call depth.
IllustrationFunction foo(x: bit_vector) return bit is alias lx: bit_vector(1 to x'length) is x; variable ret_var: bit;begin ret_var := '0'; if(x'length > 1) then ret_var := lx(1) xor foo(lx(2 to x'length)); end if; return(ret_var);end foo;
This is OK, because recursion can be unrolled statically
Illustration
Function bar(x: unsigned) return bit is alias lx: unsigned(1 to x'length) is x; variable ret_var : bit;begin ret_var := '0'; if(lx > 0) then ret_var := not (bar(x 1)); end if;end bar;
Not OK: recursion depth depends on value of x, and cannot be determined statically.
If the value of all output signals and variables is a function of signal inputs and not of past values after execution of process.eg. process(a,b)
variable x: bit;begin x := a; x := x and b; c
process(a,b) variable x;begin if (a = '1') then x := a and b; end if; c
process(clk,d)begin if clk='1' then q
process(clk,reset)begin if(reset = '1') then
Q
process(clk)begin
if clk'event and clk='1' thenif enable = '1' then
Q
Bad Synchronous Descriptionsprocess(clk)begin
if (clk'event and clk='1') thenQ
Bad synchronous descriptions
process(clk)Begin
if(clk'event) then Q
Wait Statement
wait until clock = '1';
Permitted only if wait can be transformed to if.. e,g,ProcessBegin Wait until clk = '1' Q
Recap Equivalence of steady state response Local equivalence of synthesized logic to
VHDL drivers (processes). Synthesis algorithm and synthesizable
constructs Combinational processes Processes with state
Unsynthesizable constructs Non-statically unrollable loops, function calls Bad synchronous descriptions
Global equivalence? Guaranteed if some conditions are met. For example, if the original VHDL
description satisfies All processes synthesize to either
combinational logic or to edge triggered flip-flops.
There is a well defined set of clocks which trigger the flip-flops.
The delays in the clock paths are less than the flip-flop delays
The clock and data at a flip-flop are separated in time.
Summary Only a very small subset of VHDL
descriptions is synthesizable in a locally equivalent sense.
An even smaller subset is synthesizable in a globally equivalent sense
The popular edge-triggered synchronous paradigm is the best choice to create synthesizable descriptions that match local and global behaviour.
Level-triggered or asynchronous synchronous descriptions are much harder to get right.
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