Synchronous Sequential Logic Chapter 5
Jan 04, 2016
Synchronous Sequential Logic
Chapter 5
5-2Digital Circuits
5-1 Introduction
Combinational circuits contains no memory elements the outputs depends on the inputs
5-3Digital Circuits
5-2 Sequential Circuits
■ Sequential circuits
a feedback path the state of the sequential circuit (inputs, current state) (outputs, next state) synchronous: the transition happens at discrete
instants of time asynchronous: at any instant of time
5-4Digital Circuits
Synchronous sequential circuits a master-clock generator to generate a periodic
train of clock pulses the clock pulses are distributed throughout the
system clocked sequential circuits most commonly used no instability problems the memory elements: flip-flops
binary cells capable of storing one bit of information two outputs: one for the normal value and one for the
complement value maintain a binary state indefinitely until directed by an
input signal to switch states
5-5Digital Circuits
Fig. 5.2Synchronous clocked sequential circuit
5-6Digital Circuits
5-3 Latches Basic flip-flop circuit
two NOR gates
more complicated types can be built upon it directed-coupled RS flip-flop: the cross-coupled connection an asynchronous sequential circuit (S,R)= (0,0): no operation (S,R)=(0,1): reset (Q=0, the clear state) (S,R)=(1,0): set (Q=1, the set state) (S,R)=(1,1): indeterminate state (Q=Q'=0) consider (S,R) = (1,1) (0,0)
5-7Digital Circuits
SR latch with NAND gates
Fig. 5.4SR latch with NAND gates
5-8Digital Circuits
SR latch with control input En=0, no change En=1, output depends inputs S, R
S_
R_
0/1
1/S'
1/R'
Fig. 5.5SR latch with control input
5-9Digital Circuits
D Latch eliminate the undesirable conditions of the
indeterminate state in the RS flip-flop D: data gated D-latch D Q when En=1; no change when En=0
Fig. 5.6D latch
S_
R_
0/1
1/D'
1/D
5-10Digital Circuits
Fig. 5.7Graphic symbols for latches
5-11Digital Circuits
5-4 Flip-Flops A trigger
The state of a latch or flip-flop is switched by a change of the control input
Level triggered – latches Edge triggered – flip-flops
Fig. 5.8Clock response in latch and flip-flop
5-12Digital Circuits
If level-triggered flip-flops are used the feedback path may cause instability problem
Edge-triggered flip-flops the state transition happens only at the edge eliminate the multiple-transition problem
5-13Digital Circuits
Edge-triggered D flip-flop
Master-slave D flip-flop two separate flip-flops a master flip-flop (positive-level triggered) a slave flip-flop (negative-level triggered)
Fig. 5.9Master-slave D flip-flop
5-14Digital Circuits
CP = 1: (S,R) (Y,Y'); (Q,Q') holds CP = 0: (Y,Y') holds; (Y,Y') (Q,Q') (S,R) could not affect (Q,Q') directly the state changes coincide with the negative-edge
transition of CP
第三版內容,參考用 !
5-15Digital Circuits
Edge-triggered flip-flops the state changes during a clock-pulse transition
A D-type positive-edge-triggered flip-flop
Fig. 5.10D-type positive-edge-triggered flip-flop
5-16Digital Circuits
three basic flip-flops (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided
Fig. 5.10D-type positive-edge-triggered flip-flop
5-17Digital Circuits
第三版內容,參考用 !
5-18Digital Circuits
The setup time D input must be maintained at a constant value prior to the
application of the positive CP pulse The hold time
D input must not changes after the application of the positive CP pulse
The propagation delay time The interval between the trigger edge and the stabilization
of the output to a new state
50% VH
50% VH
50% VH
50% VH
5-19Digital Circuits
Summary CP=0: (S,R) = (1,1), no state change CP=: state change once CP=1: state holds
5-20Digital Circuits
Other Flip-Flops
The edge-triggered D flip-flops The most economical and efficient Positive-edge and negative-edge
Fig. 5.11Graphic symbols for edge-triggered D flip-flop
5-21Digital Circuits
JK flip-flop
D=JQ'+K'Q J=0, K=0: D=Q, no change J=0, K=1: D=0 Q =0 J=1, K=0: D=1 Q =1 J=1, K=1: D=Q' Q =Q'
Fig. 5.12JK flip-flop
5-22Digital Circuits
T flip-flop
D = T Q = TQ'+T'Q⊕ T=0: D=Q, no change T=1: D=Q' Q=Q'
Fig. 5.13T flip-flop
5-23Digital Circuits
Characteristic tables
5-24Digital Circuits
Characteristic equations D flip-flop
Q(t+1) = D JK flip-flop
Q(t+1) = JQ'+K'Q T flop-flop
Q(t+1) = T Q⊕
5-25Digital Circuits
Direct inputs asynchronous set and/or asynchronous reset
Fig. 5.14D flip-flop with asynchronous reset
5-26Digital Circuits
5-5 Analysis of Clocked Sequential Ckts A sequential circuit
(inputs, current state) (output, next state) a state transition table or state transition diagram
Fig. 5.15Example of sequential circuit
5-27Digital Circuits
State equations
A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A'(t)x(t)
A compact form A(t+1) = Ax + Bx B(t+1) = Ax
The output equation y(t) = (A(t)+B(t))x'(t) y = (A+B)x'
5-28Digital Circuits
State table State transition table
= state equations
5-29Digital Circuits
State equation
A(t + 1) =Ax + BxB(t + 1) = Axy = Ax + Bx
5-30Digital Circuits
State diagram State transition diagram
a circle: a state a directed lines connecting the circles: the
transition between the states Each directed line is labeled 'inputs/outputs‘
a logic diagram a state table a state diagram
Fig. 5.16State diagram of the circuit of Fig. 5.15
5-31Digital Circuits
Flip-flop input equations
The part of circuit that generates the inputs to flip-flops Also called excitation functions DA = Ax +Bx DB = A'x
The output equations to fully describe the sequential circuit y = (A+B)x'
5-32Digital Circuits
Analysis with D flip-flops The input equation
DA=A x y⊕ ⊕ The state equation
A(t+1)=A x y⊕ ⊕
Fig. 5.17Sequential circuit with D flip-flop
5-33Digital Circuits
Analysis with JK flip-flops Determine the flip-flop input function in terms of
the present state and input variables Used the corresponding flip-flop characteristic
table to determine the next state
Fig. 5.18Sequential circuit with JK flip-flop
5-34Digital Circuits
JA = B, KA= Bx' JB = x', KB = A'x + Ax‘ derive the state table
Or, derive the state equations using characteristic eq.
5-35Digital Circuits
State transition diagram
Fig. 5.19State diagram of the circuit of Fig. 5.18
( 1)
( 1)
A t JA K A
B t JB K B
State equation for A and B:
( 1) ( )A t BA Bx A A B AB Ax
( 1) ( )B t x B A x B B x ABx A Bx
5-36Digital Circuits
Analysis with T flip-flops The characteristic equation
Q(t+1)= T Q = TQ'+T'Q⊕
Fig. 5.20Sequential circuit with T flip-flop
5-37Digital Circuits
The input and output functions TA=Bx
TB= x y = AB
The state equations A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx B(t+1) = x B⊕
5-38Digital Circuits
State Table
5-39Digital Circuits
Mealy and Moore models
the Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15) the outputs may change if the inputs change
during the clock pulse period the outputs may have momentary false values unless the
inputs are synchronized with the clocks
The Moore model: the outputs are functions of the present state only (Fig. 5-20) The outputs are synchronous with the clocks
5-40Digital Circuits
Fig. 5.21Block diagram of Mealy and Moore state machine
5-41Digital Circuits
5-7 Synthesizable HDL Models of Sequential Circuits Behavioral Modeling
Example: Two ways to provide free-running clock
Example: Another way to describe free-running clock
5-42Digital Circuits
Behavioral Modeling
always statement
Examples:
Two procedural blocking assignments:Two nonblocking assignments:
5-43Digital Circuits
Flip-Flops and Latches
■ HDL Example 5.1
5-44Digital Circuits
Flip-Flops and Latches
■ HDL Example 5.2
5-45Digital Circuits
Characteristic Equation
Q(t + 1) = Q ⊕ TQ(t + 1) = JQ + KQ
For a T flip-flop
For a JK flip-flop
■ HDL Example 5.3
5-46Digital Circuits
HDL Example 5-3 (Continued)
5-47Digital Circuits
HDL Example 5-4
Functional description of JK flip-flop
5-48Digital Circuits
State Diagram
■ HDL Example 5.5: Mealy HDL model
5-49Digital Circuits
HDL Example 5-5 (Continued)
5-50Digital Circuits
HDL Example 5-5 (Continued)
5-51Digital Circuits
Mealy_Zero_Detector
Fig. 5.22 Simulation output of Mealy_Zero_Detector
5-52Digital Circuits
HDL Example 5-6: Moore Model FSM
5-53Digital Circuits
Simulation Output of HDL Example 5-6
Fig. 5.23 Simulation output of HDL Example 5.6
5-54Digital Circuits
Structural Description of Clocked Sequential Circuits
■ HDL Example 5.7: State-diagram-based model
5-55Digital Circuits
HDL Example 5-7 (Continued)
5-56Digital Circuits
HDL Example 5-7 (Continued)
5-57Digital Circuits
HDL Example 5-7 (Continued)
5-58Digital Circuits
HDL Example 5-7 (Continued)
5-59Digital Circuits
Simulation Output of HDL Example 5-7
Fig. 5.24 Simulation output of HDL Example 5.7
5-60Digital Circuits
5-7 State Reduction and Assignment
State Reduction reductions on the number of flip-flops and the
number of gates a reduction in the number of states may result in a
reduction in the number of flip-flops a example state diagram
Fig. 5.25 State diagram
5-61Digital Circuits
state a a b c d e f f g f g a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0
only the input-output sequences are important two circuits are equivalent
have identical outputs for all input sequences the number of states is not important
Fig. 5.25 State diagram
5-62Digital Circuits
Equivalent states two states are said to be equivalent
for each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state
one of them can be removed
5-63Digital Circuits
Reducing the state table e=f d=?
5-64Digital Circuits
the reduced finite state machine
state a a b c d e d d e d e a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0
5-65Digital Circuits
the checking of each pair of states for possible equivalence can be done systematically (9-5)
the unused states are treated as don't-care condition fewer combinational gates
Fig. 5.26 Reduced State diagram
5-66Digital Circuits
State assignment
to minimize the cost of the combinational circuits three possible binary state assignments
5-67Digital Circuits
any binary number assignment is satisfactory as long as each state is assigned a unique number
use binary assignment 1
5-68Digital Circuits
5-8 Design Procedure
the word description of the circuit behavior (a state diagram)
state reduction if necessary assign binary values to the states obtain the binary-coded state table choose the type of flip-flops derive the simplified flip-flop input equations and
output equations draw the logic diagram
5-69Digital Circuits
Synthesis using D flip-flops
An example state diagram and state table
Fig. 5.27 State diagram for sequence detector
5-70Digital Circuits
The flip-flop input equations A(t+1) = DA(A,B,x) = (3,5,7)
B(t+1) = DB(A,B,x) = (1,5,7)
The output equation y(A,B,x) = (6,7)
Logic minimization using the K map DA= Ax + Bx
DB= Ax + B'x y = AB
5-71Digital Circuits
Fig. 5.28 Maps for sequence detector
5-72Digital Circuits
Sequence detector The logic diagram
Fig. 5.29 Logic diagram of sequence detector
5-73Digital Circuits
Excitation tables
A state diagram flip-flop input functions straightforward for D flip-flops we need excitation tables for JK and T flip-flops
5-74Digital Circuits
Synthesis using JK flip-flops The same example The state table and JK flip-flop inputs
5-75Digital Circuits
JA = Bx'; KA = Bx JB = x; KB = (A x)‘⊕ y = ?
Fig. 5.30 Maps for J and K input equations
5-76Digital Circuits
Fig. 5.31 Logic diagram for sequential circuit with JK flip-flops
5-77Digital Circuits
Synthesis using T flip-flops A n-bit binary counter
the state diagram
no inputs (except for the clock input)
Fig. 5.32 State diagram of three-bit binary counter
5-78Digital Circuits
The state table and the flip-flop inputs
5-79Digital Circuits
Fig. 5.33 Maps of three-bit binary counter
5-80Digital Circuits
Logic simplification using the K map TA2 = A1A2
TA1 = A0
TA0 = 1
The logic diagram
Fig. 5.34 Logic diagram of three-bit binary counter