Synchronous Design Methodologies & Impedements to Synchronous Design

Synchronous Digital Design Methodology and GuidelinesDigital System Design

Synchronous DesignAll flip-flops clocked by one common clockReset only used for initializationRaces and hazards are no problem

Why synchronous design?Hazard The unwanted switching transients that may appear at the output of a circuit are called Hazards. The glitches that occur due to the structure of a circuit and their propagation delays are called as hazards. the hazards cause the circuit to malfunction. The main cause of Hazards is the different propagation delays at different paths.

Timing HazardStatic hazard: possibility of a brief signal value change when the signal was expected to be stable, due to timing (glitch)Dynamic hazard: possibility of multiple output transitions caused by a single input transition due to multiple signal paths with different delays

Static HazardIf d is the delay of each gate

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Analyzing Static Hazards using Karnaugh mapsA static hazard can occur when changing a single input variable causes a jump from one prime implicant to anotherSolution: include an additional prime implicant

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Eliminating hazards using Flip-Flops

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Synchronous DesignThree things must be ensured by the designer:Minimize and determine clock skewAccount for flip-flop setup and hold timesReliably synchronize asynchronous inputs

Timing Analysis>0 Setup time margin>0 Hold time margin

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Propagation delay

Combinational path delay

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Clock skew

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ExampleDetermine the maximum frequency of the following circuit with and without skew

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Clock GatingClock gating is done to disable the clock for low power consumption using a clken signalIt is wrong to gate the clock in the following way, instead use a synchronous load (enable) signal

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Asynchronous InputsIt is impossible to guarantee setup and hold timing constraints on inputs synchronized with a clock unrelated to the system clock

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Asynchronous inputsSynchronize only in one place

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MetastabilityMetastability is a phenomenon that may occur if the setup and hold time requirements of the FF are not met, leading in the output settling in an unknown value after unspecified time.

Reliable synchronizer design

ExampleDesign a synchronizer that synchronizes two inputs async1 and async2 generated with a 50 MHz clock CLK1, to a system with a 33 MHz clock CLK2 totally independent of CLK1. Draw appropriate timing diagrams.

Mean-time between failuresf: frequency of flip-flop clocka: number of asynchronous input changes per second in flip-flop inputTo, : constants depending on flip-flop electrical characteristicsAssume a 10 Mhz clock, ts = 20 ns, To = 0.4 sec, = 1.5 ns and that the asynchronous input can change 100,000 times per second, thentr = 1/f ts = 80 nsMTBF(80ns) = exp(80/1.5)/0.410^710^5= 3.610^11 s

Cascaded synchronizer

Synchronizing bus transfersDo not use dual f/f synchronizers in all bits, this will only increase the chances of metastabilitySynchronize the control signals and read the input when safe to do so

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FIFO Synchronizer basic conceptOn burst transfers, the receiver cannot afford to wait for the signal to settle.Solution: A dual-port RAM FIFOProblem: How do we synchronize the counters?

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SummaryIn order to avoid hazards and races, synchronous design is usedIn synchronous design a single common clock is used and reset is only used for initializationThe only considerations in synchronous design are the flip-flop setup and hold times, clock skew and asynchronous input synchronizationAsynchronous inputs are commonly synchronized using 2 flip-flops clocked with the synchronous system clockSynchronization should only be done in one placeIn bus transfers, synchronize only the control signals or use a FIFO

Design trade-offs

Common design trade-offsPerformanceLatencyThroughputDelay (timing)AreaGates (ASIC)Flip-flops/LUTs (FPGA)Power consumptionDynamicStaticLeakage

Design for SpeedDesign for High ThroughputDefinition: High data rate, acceptable latencyTechnique: PipeliningDesign for Low LatencyDefinition: Output available as soon as possibleTechnique: Parallelism, Removal of pipeliningDesign for TimingDefinition: High clock speed, low delay between registersTechnique: Add intermediate registers

Example 1: Design for low latency (parallelism)X = a + b + c + dDelay = 3*addDelay = 2*addLatency = 1 cycleLatency = 1 cycleThroughput = X bits/clock Throughput = X bits/clock

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Example 1: Design for delayX = a + b + c + dDelay = 1*add + RegLatency = 2 cyclesThroughput = X bits/clock

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Resource SharingY= C1* X[0] + C2 *X[1] + C3*X[2]

Is it possible to perform all multiplications with a single multiplier?Is it possible to perform all additions with a single accumulator?

Resource Sharing

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Design for low-powerPower components:Dynamic power consumption (switching): power consumed due to charging and discharging parasitic capacitances on gates and wiresStatic power consumption: Power consumed when no switchingLeakage current power consumption:

Design for powerClock GatingDual-edge triggered Flip-FlopsLowering core voltage

Clock GatingClock gating is done to disable the clock for low power consumption using a clken signalIt is wrong to gate the clock in the following way, instead use a synchronous load (enable) signal or a global clock multiplexer (if available)

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Dual-Edge Triggered Flip-FlopsDual-edge triggered flip-flops should only be used if available in the target technology Otherwise, redundant flip-flops and gating will be used to emulate the desired functionality

Single-edge triggered FFDual-edge triggered FF (same data rate)

Lowering core voltageOnly reduce core voltage within acceptable limits (5 to 10%)Power consumption in a simple resistor is proportional to the square of the voltageKeep in mind that performance will degrade too

Review questions/problemsPipelining will make your circuitA. smallerB. exhibit lower latencyC. Consume less powerD. exhibit higher throughputParallelism creates aA. latency/throughput trade-offB. Performance/area trade-offC. Area/power consumption trade-offD. performance/power consumption trade-offPipeline the following datapath for a three-cycle latency so that you get the maximum operation frequency. How much is the maximum operation frequency?