SYLLABUS Section B Real Time and Embedded Operating Systems: Real Time and Embedded Operating Systems: – Introduction, – Hardware Elements, – Structure.

SYLLABUSSection BSection B

•Real Time and Embedded Operating Systems: Real Time and Embedded Operating Systems: – Introduction, Introduction, – Hardware Elements, Hardware Elements, – Structure Structure

• Interrupt Driven, Interrupt Driven, • Nanokernel, Nanokernel, • Microkernel Microkernel and and • Monolithic kernel based models. Monolithic kernel based models.

– Scheduling – Scheduling – • Periodic, Periodic, • Aperiodic Aperiodic and and • Sporadic Tasks, Sporadic Tasks,

– Introduction to Energy Aware CPU Scheduling.Introduction to Energy Aware CPU Scheduling.

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ASSIGNMENT #1: 16 JAN 2014SECTION BSECTION B

1.1.What are the characteristics of Real Time and Embedded systems? What are the characteristics of Real Time and Embedded systems? 2.2.Describe Hardware Elements used in RE systems. Describe Hardware Elements used in RE systems. 3.3.Describe structure of Real Time and Embedded (RE) operating systems clearly specifying difference Describe structure of Real Time and Embedded (RE) operating systems clearly specifying difference between Interrupt Driven, Nanokernel, Microkernel and Monolithic kernel based models. between Interrupt Driven, Nanokernel, Microkernel and Monolithic kernel based models. 4.4.Differentiate between Periodic, Aperiodic and Sporadic Tasks. What algorithms are available for their Differentiate between Periodic, Aperiodic and Sporadic Tasks. What algorithms are available for their scheduling?scheduling?5.5.Describe Energy Aware CPU Scheduling.Describe Energy Aware CPU Scheduling.

SECTION ASECTION A1.1.What do you understand by Multi-Processor and Distributed (MPD) systems? Describe Architecture of What do you understand by Multi-Processor and Distributed (MPD) systems? Describe Architecture of Operating Systems for such systems.Operating Systems for such systems.2.2.How is Resource sharing and Load Balancing achieved in MPD systems?How is Resource sharing and Load Balancing achieved in MPD systems?3.3.What are the Design and Development Challenges in MPD Operating Systems? What are the Design and Development Challenges in MPD Operating Systems? 4.4.Write short notes on:Write short notes on:

1.1. Inter-process Communication in a typical MPD OSInter-process Communication in a typical MPD OS2.2. Availability of resources in MPD systems.Availability of resources in MPD systems.3.3. Fault Tolerance in MPD systems Fault Tolerance in MPD systems 4.4. Logical Clock Logical Clock 5.5. Mutual ExclusionMutual Exclusion6.6. Distributed File SystemDistributed File System 2

ADVANCED OPERATING SYSTEMSADVANCED OPERATING SYSTEMS

MCA 404MCA 404

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SYLLABUS

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SYLLABUSSection BSection B

•Real Time and Embedded Operating Systems: Real Time and Embedded Operating Systems: – Introduction, Introduction, – Hardware Elements, Hardware Elements, – Structure Structure


– Scheduling – Scheduling – • Periodic, Periodic, • Aperiodic Aperiodic and and • Sporadic Tasks, Sporadic Tasks,

– Introduction to Energy Aware CPU Scheduling.Introduction to Energy Aware CPU Scheduling.

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SYLLABUSSection CSection C

•Cluster and Grid Computing: Cluster and Grid Computing: – Introduction to Cluster Computing and MOSIX OS, Introduction to Cluster Computing and MOSIX OS, – Introduction to the Grid, Introduction to the Grid, – Grid Architecture, Grid Architecture,

•Computing Platforms: Computing Platforms: – Operating Systems and Network Interfaces, Operating Systems and Network Interfaces, – Grid Monitoring and Scheduling, Grid Monitoring and Scheduling, – Performance Analysis, Performance Analysis, – Case Studies.Case Studies.

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SYLLABUSSection DSection D

•Cloud Computing: Cloud Computing: – Introduction to Cloud, Introduction to Cloud, – Cloud Building Blocks, Cloud Building Blocks, – Cloud as IaaS, PaaS and SaaS, Cloud as IaaS, PaaS and SaaS, – Hardware and software virtualization, Hardware and software virtualization, – Virtualization of OSVirtualization of OS– Hypervisor KVM, Hypervisor KVM, – SAN and SAN and – NAS back-end concepts.NAS back-end concepts.

•Mobile Computing: Mobile Computing: – Introduction, Introduction, – Design Principles, Design Principles, – Structure, Platform and Features of Mobile Operating Systems (Android, IOS, Structure, Platform and Features of Mobile Operating Systems (Android, IOS,

Windows Mobile OS).Windows Mobile OS). 7

SYLLABUSReferencesReferences::•Sibsankar Haldar, Alex A. Arvind, “Operattng Systems”, Pearson Sibsankar Haldar, Alex A. Arvind, “Operattng Systems”, Pearson Education Inc.Education Inc.•Tanenbaum and Van Steen, “Distributed systems: Principles and Tanenbaum and Van Steen, “Distributed systems: Principles and Paradigms”, Pearson, 2007.Paradigms”, Pearson, 2007.•M. L. Liu,M. L. Liu, “Distributed Computing: Principles and Applications”, “Distributed Computing: Principles and Applications”, Addison Wesley, Pearson Addison Wesley, Pearson •Maozhen Li, Mark Baker,Maozhen Li, Mark Baker, “The Grid – Core Technologies”, John “The Grid – Core Technologies”, John Wiley & Sons 2005Wiley & Sons 2005

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SECTION B

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SECTION B• Real Time and Embedded Operating Systems: Real Time and Embedded Operating Systems:

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8051 MICROCONTROLLER8051 MICROCONTROLLER

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8051 MICROCONTROLLER8051 MICROCONTROLLER• PDIP - Plastic Dual-in-Line PackagePDIP - Plastic Dual-in-Line Package• CERDIP - Ceramic Dual-in-Line PackageCERDIP - Ceramic Dual-in-Line Package

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8051 SCHEMATIC DIAGRAM

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8051 SCHEMATIC DIAGRAM

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COMPARISON OF 8051 FAMILY MEMBERS

Features Features 8051 8051 8052 8052 8031 8031

• RAM (bytes)RAM (bytes) 128128 256256 128128• ROMROM 4K4K 8K8K 0K0K• TimersTimers 22 33 22• Serial portSerial port 11 11 11• I/O pinsI/O pins 3232 3232 3232• Interrupt sourcesInterrupt sources 66 88 66

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PSEN (Pin 29)PSEN (Pin 29).. (Not used for AT89S52)(Not used for AT89S52)•Program Store Enable. This is an output pin. Program Store Enable. This is an output pin. In In an 8031 based system, in which an external an 8031 based system, in which an external ROM holds the program code, ROM holds the program code, this pin is this pin is connected to the connected to the OE*OE* pin of ROM. pin of ROM. •PSEN is not activated when the device is PSEN is not activated when the device is executing out ofexecuting out of internal Program Memory. internal Program Memory. ALE/PROG (Pin 30).ALE/PROG (Pin 30). (Not used for AT89S52)(Not used for AT89S52)•Address Latch Enable. Address Latch Enable. When connecting an When connecting an 8031 to external memory8031 to external memory, Port 0 provides both , Port 0 provides both Address and Data. It is connected to G Pin Address and Data. It is connected to G Pin (Pin (Pin

11, Latch Enable)11, Latch Enable) of 74LS373 chip (D Latch). of 74LS373 chip (D Latch). •Not used for ATMEL 89S52.Not used for ATMEL 89S52.EA/VPP (Programming Voltage, Pin 31).EA/VPP (Programming Voltage, Pin 31). •EA: External Access . EA: External Access . •When EA is held high (+5V) the CPU executes When EA is held high (+5V) the CPU executes out of out of internal Program Memoryinternal Program Memory. . •Holding EA low (0V) forces the CPU to execute Holding EA low (0V) forces the CPU to execute out of external memory. In the 80C31, EA must out of external memory. In the 80C31, EA must be externally wired low. be externally wired low. •In the EPROM devices, this pin also receives In the EPROM devices, this pin also receives the the programming supply voltage programming supply voltage ((VPPVPP) during ) during EPROM programming.EPROM programming.•For AT89S52, it will be connected to Vcc.For AT89S52, it will be connected to Vcc.

*OE*OE: Output Enable: Output Enable

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Alternate Function of Port 3 PinsAlternate Function of Port 3 Pins

•P3.0P3.0 Receive Data for serial port Receive Data for serial port communication.communication.•P3.1P3.1 Transmit Data for serial port Transmit Data for serial port communication.communication.

•P3.2P3.2 Receive External Interrupt 0.Receive External Interrupt 0.•P3.3P3.3 Receive External Interrupt 1.Receive External Interrupt 1.

•P3.4P3.4 Timer 0 Interrupt (Internal)Timer 0 Interrupt (Internal)•P3.5P3.5 Timer 1 Interrupt (Internal)Timer 1 Interrupt (Internal)

•P3.6P3.6 WR (Bar)WR (Bar) Signals of external memory Signals of external memory connected in case of 8031.connected in case of 8031.•P3.7P3.7 RD (Bar)RD (Bar) Signals of external memory Signals of external memory connected in case of 8031.connected in case of 8031.

•8051 Interrupts (Five)8051 Interrupts (Five)..

– 2 external interrupts, 2 external interrupts, – 2 timer interrupts, and 2 timer interrupts, and – 1 serial interrupt. 1 serial interrupt.

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SPECIAL FUNCTION REGISTERS OF 8051SPECIAL FUNCTION REGISTERS OF 8051• SPSP: Stack Pointer; : Stack Pointer; DPLDPL: Data Pointer Lower Byte; : Data Pointer Lower Byte; DPHDPH: Data Pointer Higher Byte; : Data Pointer Higher Byte; • TCONTCON: Timer Control; : Timer Control; TMODTMOD: Timer Mode; : Timer Mode; • TL0TL0: Timer 0, Low Byte; : Timer 0, Low Byte; TH0TH0: Timer 0, Higher Byte: Timer 0, Higher Byte• TL1TL1: Timer 1, Low Byte; : Timer 1, Low Byte; TH1TH1: Timer 1, Higher Byte: Timer 1, Higher Byte• SCONSCON: Serial Communication; : Serial Communication; SBUFSBUF: Serial Buffer; : Serial Buffer; • IEIE: Interrupt Enable: Interrupt Enable• IPIP: Instruction Pointer: Instruction Pointer• PSWPSW: Program Status Word: Program Status Word• ACCACC: Accumulator: Accumulator• BB: Used by : Used by MUL AB MUL AB

andand DIV ABDIV AB• P0P0: Port 0 internal buffer: Port 0 internal buffer• P1P1: Port 1 internal buffer: Port 1 internal buffer• P2P2: Port 2 internal buffer: Port 2 internal buffer• P3P3: Port 3 internal buffer: Port 3 internal buffer

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EXAMPLE: EREXAMPLE: ERReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Writing Real Time and Embedded Operating System for 8051 Microcontroller.Microcontroller.

a.a. Write a simple operating system for 8051 microcontroller which is required Write a simple operating system for 8051 microcontroller which is required to to monitor and control monitor and control water level in a tankwater level in a tank. If the water level falls below a . If the water level falls below a critical level, it should start the water pump automatically. If the level rises critical level, it should start the water pump automatically. If the level rises above the top level, it should stop the motor. above the top level, it should stop the motor.

b.b. GuidelinesGuidelines..i.i. There would be two sensors. One for sensing lowest level and the other for sensing There would be two sensors. One for sensing lowest level and the other for sensing

highest level.highest level.ii.ii. The sensors would be connected to two pins of a port. These pins/port would be The sensors would be connected to two pins of a port. These pins/port would be

configured as input port.configured as input port.iii.iii. These sensor pins would be checked in a loop for their status.These sensor pins would be checked in a loop for their status.iv.iv. When the water level falls below the lowest level, another port pin, configured as When the water level falls below the lowest level, another port pin, configured as

output pin, would be set to 1 (Say P2.1). This pin would be connected to an electric output pin, would be set to 1 (Say P2.1). This pin would be connected to an electric relay. If both the sensors are off, give instruction SetB P2.1. which would start the relay. If both the sensors are off, give instruction SetB P2.1. which would start the water pump.water pump.

v.v. When the water level increases above upper level, the pump is stopped by another When the water level increases above upper level, the pump is stopped by another instruction: Clr P2.1instruction: Clr P2.1 20

EXAMPLE: EREXAMPLE: ERReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Writing Real Time and Embedded Operating System for 8051 Microcontroller…Microcontroller…

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EXAMPLE: EREXAMPLE: ERReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Writing Real Time and Embedded Operating System for 8051 Microcontroller…Microcontroller…

ORG 00ORG 00; Configure P1.1 and P1.2 as input pins; Configure P1.1 and P1.2 as input pinsSetBSetB P1.1P1.1SetBSetB P1.2P1.2; Now they have high voltage. When water crosses these levels,; Now they have high voltage. When water crosses these levels,; the Sensors should send low voltage (0V) on these pins.; the Sensors should send low voltage (0V) on these pins.

; Configure P2.1 as output pin; Configure P2.1 as output pinClrClr P2.1P2.1 ; Relay should be wired such that ; Relay should be wired such that

; it also stops the motor; it also stops the motorMainloop:Mainloop:

; Check Low level; Check Low levelCheckLowLevel:CheckLowLevel:

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EXAMPLE: EREXAMPLE: ERReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Microcontroller…Writing Real Time and Embedded Operating System for 8051 Microcontroller…Mainloop:Mainloop:

; Check Low level; Check Low levelCheckLowLevel:CheckLowLevel:JNBJNB P1.1, P1.1, CheckHighLevelCheckHighLevel ; P1.1 = 0, Water is above empty level; P1.1 = 0, Water is above empty levelSetBSetB P2.1P2.1 ; Tank is Empty , Start Water Pump; Tank is Empty , Start Water Pump

SJMPSJMP CheckgainCheckgain ; Bypass High level checks.; Bypass High level checks.; Let the pump keep running.; Let the pump keep running.

CheckHighLevel:CheckHighLevel: ; If water is above low level, check upper level; If water is above low level, check upper levelJB JB P1.2, CheckgainP1.2, Checkgain ; Water is below Top level; Water is below Top levelClrClr P2.1P2.1 ; Tank is Full, Stop Water Pump; Tank is Full, Stop Water Pump

Checkagain:Checkagain:SJmp MainloopSJmp Mainloop

ENDEND

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ConditionCondition High Level Sensor High Level Sensor PinPin

Low Level Sensor Low Level Sensor PinPin

Motor Relay PinMotor Relay Pin Motor StatusMotor Status

1.1. Initialisation outside Initialisation outside Mainloop: Assume Mainloop: Assume initially Tank is Emptyinitially Tank is Empty

Set it to High (1) : Set it to High (1) : InactiveInactive

Set it to High (1): Set it to High (1): InactiveInactive

Set it to Low (0)Set it to Low (0)

Initially Stop Initially Stop MotorMotor

2 2 Enter MainloopEnter Mainloop Sensor indicates Sensor indicates below top levelbelow top level

Sensor indicates Sensor indicates below low levelbelow low level

Becomes High (1)Becomes High (1)

Motor StartsMotor Starts

3 3 Now Motor is RunningNow Motor is Running High (1) : InactiveHigh (1) : Inactive High (1): InactiveHigh (1): Inactive Remains High (1)Remains High (1) Motor keeps Motor keeps runningrunning

4 4 After sometime Low After sometime Low level sensor gets level sensor gets activatedactivated

Remains High (1): Remains High (1): InactiveInactive

Becomes Low (0):Becomes Low (0):Active; Water Active; Water rises above Lower rises above Lower levellevel

Remains High (1)Remains High (1) Motor keeps Motor keeps runningrunning

5 5 Water crosses Top Water crosses Top LevelLevel

Becomes Low (0): Becomes Low (0): ActiveActive

Remains Low (0): Remains Low (0): ActiveActive

Becomes Low (0)Becomes Low (0) Motor StopsMotor Stops

6 6 Water level falls with Water level falls with usage. Falls below usage. Falls below high levelhigh level

Becomes High Becomes High (1): Inactive(1): Inactive


Remains Low (0)Remains Low (0) Motor Remains Motor Remains OffOff

7 7 Water Falls further Water Falls further and goes below low and goes below low levellevel


Becomes High (1): Becomes High (1): InactiveInactive



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EXAMPLE: EREXAMPLE: ERReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)

•Write an Write an interrupt driven operating system interrupt driven operating system to monitor and control to monitor and control water level in a tank. Water level sensors would be wired on external water level in a tank. Water level sensors would be wired on external interrupt pins (P3.2 and P3.3).interrupt pins (P3.2 and P3.3). 25

EXAMPLE: EREXAMPLE: ERReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)

2.2.Write an Write an interrupt driven operating system interrupt driven operating system to monitor and control to monitor and control water level in a tank. Water level sensors would be wired on external water level in a tank. Water level sensors would be wired on external interrupt pins (P3.2 and P3.3). Use low level sensor on P3.2 (INT0) and interrupt pins (P3.2 and P3.3). Use low level sensor on P3.2 (INT0) and High Level Sensor at Pin P3.3 (INT1). Configure your OS for interrupt High Level Sensor at Pin P3.3 (INT1). Configure your OS for interrupt handling and write ISRs for the same.handling and write ISRs for the same. 26

VECTOR ADDRESS OF INTERRUPTS IN 8051VECTOR ADDRESS OF INTERRUPTS IN 8051

Interrupt SourceInterrupt Source Vector addressVector address Interrupt priorityInterrupt priority

• External Interrupt 0 –INT0External Interrupt 0 –INT0 0003H0003H 11

• Timer 0 InterruptTimer 0 Interrupt 000BH000BH 22



• Serial InterruptSerial Interrupt 0023H0023H 55

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STRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMSSTRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMS

• Steps in executing interrupts in the case of 8051 Series of Steps in executing interrupts in the case of 8051 Series of Microcontrollers:-Microcontrollers:-1.1. Upon activation of an interrupt , the microcontroller finishes the instruction Upon activation of an interrupt , the microcontroller finishes the instruction

it is executing and saves the address of the next instruction (Program it is executing and saves the address of the next instruction (Program Counter (PC)) on the stack.Counter (PC)) on the stack.

2.2. It also saves the current status of all the interrupts internally (ie not on the It also saves the current status of all the interrupts internally (ie not on the stack).stack).

3.3. It jumps to a fixed location in memory in accordance with the Interrupt It jumps to a fixed location in memory in accordance with the Interrupt Vector Table.Vector Table.

4.4. If the ISR is only one or two instructions, these may be written there itself.If the ISR is only one or two instructions, these may be written there itself.5.5. Generally, the ISR has many instructions. In such cases, a jump instruction is Generally, the ISR has many instructions. In such cases, a jump instruction is

placed at interrupt vector address.placed at interrupt vector address.6.6. The last instruction in the ISR is RETI (Return from Interrupt).The last instruction in the ISR is RETI (Return from Interrupt).7.7. Upon executing RETI instruction, the microcontroller returns to the place Upon executing RETI instruction, the microcontroller returns to the place

where it was interrupted. First it gets the Program Counter address from where it was interrupted. First it gets the Program Counter address from the stack by popping the top two bytes of the stack into the PC. Then it the stack by popping the top two bytes of the stack into the PC. Then it starts to execute from that address. starts to execute from that address. 28


• Interrupts in 8051Interrupts in 8051.. There are Six interrupts in 8051.There are Six interrupts in 8051.1.1. ResetReset.. When the reset pin is activated, When the reset pin is activated, the 8051 jumps to the 8051 jumps to

address location 0000. This is the power-up reset. Program execution starts address location 0000. This is the power-up reset. Program execution starts from address 0000.from address 0000.

2.2. Timer Interrupts (Two)Timer Interrupts (Two).. Two interrupts are set aside for the Two interrupts are set aside for the timers, one for Timer 0 and the other for Timer 1. Memory locations 000BH timers, one for Timer 0 and the other for Timer 1. Memory locations 000BH and 001BH in the interrupt vector table belong to Timer 0 and Timer 1 and 001BH in the interrupt vector table belong to Timer 0 and Timer 1 respectively.respectively.

3.3. External Hardware Interrupts (Two)External Hardware Interrupts (Two).. Pin No 12 (P3.2) and 13 (P3.3) in Pin No 12 (P3.2) and 13 (P3.3) in Port 3 are for the external hardware interrupts. INT0 and INT1, respectively. Port 3 are for the external hardware interrupts. INT0 and INT1, respectively. These external interrupts are also referred to as EX1 and EX2. Memory These external interrupts are also referred to as EX1 and EX2. Memory locations 0003H and 0013H in the interrupt vector table are assigned to locations 0003H and 0013H in the interrupt vector table are assigned to INT0 and INT1 , respectivelyINT0 and INT1 , respectively

4.4. Serial Communication InterruptSerial Communication Interrupt. . SSerial communication has a erial communication has a single interrupt that belongs to both receive and transfer. The interrupt single interrupt that belongs to both receive and transfer. The interrupt vector table location 0023H belongs to this interrupt.vector table location 0023H belongs to this interrupt.

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• RESETRESET 0000H0000H toto 0002H0002H == 3 Bytes3 Bytes• INT 0:INT 0: 0003H 0003H toto 000AH000AH == 8 Bytes8 Bytes• Timer 0:Timer 0: 000BH 000BH toto 0012H0012H == 8 Bytes8 Bytes• INT 1:INT 1: 0013H 0013H toto 001AH001AH == 8 Bytes8 Bytes• Timer 1:Timer 1: 001BH 001BH toto 0022H0022H == 8 Bytes8 Bytes• Serial COM:Serial COM: 0023H 0023H toto 002AH002AH == 8 Bytes8 Bytes

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INTERRUPT HANDLING IN 8051INTERRUPT HANDLING IN 8051ORGORG 0000H0000HLJMPLJMP MainLoop ; Long JMP is a three byte instruction with 16 Bit addressMainLoop ; Long JMP is a three byte instruction with 16 Bit address

; ISR for Timer 0 ; ISR for Timer 0 to generate square waveto generate square waveORGORG 000BH000BH ; This ISR is very small, It is written within 8 Bytes; This ISR is very small, It is written within 8 BytesRepeatThis:RepeatThis:CPLCPL P2.1P2.1SJMPSJMP RepeatThis RepeatThisRETIRETI ; Use RETI to return from ISR ; Use RETI to return from ISR

; ISR for External Hardware Interrupt INT 1 ; ISR for External Hardware Interrupt INT 1 ORGORG 0013H0013HLJMPLJMP StartAlarm ; If the ISR is longer than 8 Bytes, jump to subroutineStartAlarm ; If the ISR is longer than 8 Bytes, jump to subroutineRETIRETI

ORGORG 0030H0030H ; After vector table space; After vector table spaceMainLoop:MainLoop:

; Keep waiting for interrupts in this loop; Keep waiting for interrupts in this loopSJMP MainLoopSJMP MainLoop ; Short JMP is a two byte instruction with Relative Address; Short JMP is a two byte instruction with Relative Address

StartAlarm:StartAlarm:SetBSetB P1.0P1.0 ; Alarm circuit connected to P1.0; Alarm circuit connected to P1.0…… …… ; Write more instructions here; Write more instructions hereRETIRETI ; Use RETI to return from ISR; Use RETI to return from ISR

ENDEND31

INSTRUCTION SETINSTRUCTION SET

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EXTERNAL INTERRUPTS HANDLING IN 8051EXTERNAL INTERRUPTS HANDLING IN 8051

• Let us understand the concept of interrupts, how interrupts work, Let us understand the concept of interrupts, how interrupts work, vector address, interrupt priority and how to write an ISR (vector address, interrupt priority and how to write an ISR (interrupt interrupt service routineservice routine).).

• ““Interruption” in English language means a deviation from the Interruption” in English language means a deviation from the normal routine. normal routine.

• We know the processor is always busy executing some kind of We know the processor is always busy executing some kind of instructions. instructions.

• What if there occurs an urgent conditionWhat if there occurs an urgent condition that we need to pause the that we need to pause the processor from its current activities for some time and make it processor from its current activities for some time and make it execute/do something else? execute/do something else?

• Also we need to resume the processor back to its operations after Also we need to resume the processor back to its operations after executing our executing our “urgent condition”“urgent condition”. .

• To meet such a demand, 8051 micro controller has got a system To meet such a demand, 8051 micro controller has got a system called “Interrupts”.called “Interrupts”.

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• An interrupt is usually a signal from the external world An interrupt is usually a signal from the external world or or a a command from the internal programcommand from the internal program (called software interrupt), (called software interrupt), which forces the processor to pause its current activities and then which forces the processor to pause its current activities and then jump to another location to execute another set of predefined jump to another location to execute another set of predefined activities. activities.

• While doing so the processor will save its currents status and While doing so the processor will save its currents status and location to a temporary storage area (location to a temporary storage area (to resume the current activities to resume the current activities after finishing the interruptafter finishing the interrupt). ).

• The process of jumping to another location, after receiving the The process of jumping to another location, after receiving the interrupt signal is known as “interrupt signal is known as “servicing the interruptservicing the interrupt”.”.

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EXTERNAL INTERRUPTS HANDLING IN 8051EXTERNAL INTERRUPTS HANDLING IN 8051Interrupt sourcesInterrupt sources•In an 8051 micro controller there are In an 8051 micro controller there are

– 2 external interrupts, 2 external interrupts, – 2 timer interrupts, and 2 timer interrupts, and – 1 serial interrupt. 1 serial interrupt.

•External interrupts are – external interrupt 0(INT0) and external interrupt 1 (INT1). External interrupts are – external interrupt 0(INT0) and external interrupt 1 (INT1). •Timer interrupts are Timer 0 interrupt and Timer 1 interrupt. Timer interrupts are Timer 0 interrupt and Timer 1 interrupt. •A serial interrupt is given for serial communication with the micro controller A serial interrupt is given for serial communication with the micro controller (transmit and receive) .(transmit and receive) .•All these four interrupts, when evoked All these four interrupts, when evoked serve or execute serve or execute a particular set of a particular set of predefined activities known as “predefined activities known as “Interrupt Service RoutinesInterrupt Service Routines”. ”. •It’s way of functioning is similar to the “subroutines” we write while developing a It’s way of functioning is similar to the “subroutines” we write while developing a complete program. complete program. •In the case of 8051, the interrupt service routines(ISR) of each interrupt must begin In the case of 8051, the interrupt service routines(ISR) of each interrupt must begin from a corresponding address in the program memory. from a corresponding address in the program memory. •This address from which an ISR begins is called the vector address of the interrupt.This address from which an ISR begins is called the vector address of the interrupt.

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Interrupt SourceInterrupt Source Vector addressVector address Interrupt priorityInterrupt priority





• Serial InterruptSerial Interrupt 0023H0023H 55

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Interrupt PriorityInterrupt Priority•All the 5 interrupts of 8051 have got different priorities. All the 5 interrupts of 8051 have got different priorities. •Interrupts are serviced according to it’s priority order. Interrupts are serviced according to it’s priority order. •From the table above, you can see that INT0 has the highest priority From the table above, you can see that INT0 has the highest priority of 1 and Timer 0 comes next with priority value 2. of 1 and Timer 0 comes next with priority value 2. •The order of priority works like this – consider a case where two The order of priority works like this – consider a case where two interrupts are raised at the same time – one from INT0 and another interrupts are raised at the same time – one from INT0 and another from Timer 1 interrupt. Now which one would be served first? from Timer 1 interrupt. Now which one would be served first? •In such a case, processor would serve the interrupt according to it’s In such a case, processor would serve the interrupt according to it’s priority. priority. •In our case INT0 is of high priority (priority order 1)and Timer 1 In our case INT0 is of high priority (priority order 1)and Timer 1 interrupt is of low priority (priority order 4). So processor will execute interrupt is of low priority (priority order 4). So processor will execute ISR of INTO first and then later, after finishing ISR of INT0, processor ISR of INTO first and then later, after finishing ISR of INT0, processor will begin executing ISR of Timer 1 interrupt.will begin executing ISR of Timer 1 interrupt.

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Interrupt Priority…Interrupt Priority…•From the figure above, you may note that INTO is an alternate From the figure above, you may note that INTO is an alternate function P3.2 and INT1 is an alternate function of P3.3. function P3.2 and INT1 is an alternate function of P3.3. •A signal received at these pins will evoke the interrupts accordingly. A signal received at these pins will evoke the interrupts accordingly. But not all signals will evoke the interrupt! But not all signals will evoke the interrupt! •The signal received at pins should be either a The signal received at pins should be either a low levellow level one or it one or it should be a should be a falling edge signal falling edge signal to evoke the corresponding interrupt. to evoke the corresponding interrupt. •However, However, to serve the interrupt upon receiving the signal at pinsto serve the interrupt upon receiving the signal at pins, , the the man who programs 8051 man who programs 8051 should preprocess a few bits of three SFRs should preprocess a few bits of three SFRs namely namely TCON, IE and IPTCON, IE and IP. . •Let’s examine them. Let’s examine them.

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8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER

http://www.circuitstoday.com/external-interrupts-handling-in-805143


1.1. TCON is a bit addressable SFR. TCON is a bit addressable SFR. 2.2. Out of the 8 bits, only the lower 4 bits are concerned with external Out of the 8 bits, only the lower 4 bits are concerned with external

interrupts. interrupts. 3.3. The upper 4 bits deals with interrupts from Timers. The upper 4 bits deals with interrupts from Timers. 4.4. The lower four bits are TCON.0 (IT0), TCON.1 (IE0), TCON.2 (IT1) The lower four bits are TCON.0 (IT0), TCON.1 (IE0), TCON.2 (IT1)

and TCON.3 (IE1). and TCON.3 (IE1). 5.5. You can refer the figure given above for a better understanding. You can refer the figure given above for a better understanding. 6.6. Out of these 4 bits, bits 0 and 1 – that means – TCON.0 and TCON.1 Out of these 4 bits, bits 0 and 1 – that means – TCON.0 and TCON.1

are concerned with external interrupt 0 (INT0), where as bits 2 and are concerned with external interrupt 0 (INT0), where as bits 2 and 3 – TCON.2 and TCON.3 are concerned with external interrupt 1 3 – TCON.2 and TCON.3 are concerned with external interrupt 1 (INT1). (INT1).

7.7. Out of these bits only TCON.0 and TCON.2 are directly manipulated Out of these bits only TCON.0 and TCON.2 are directly manipulated by the programmer while dealing with an external interruptby the programmer while dealing with an external interrupt. .

8.8. Bits TCON.1 (IE0) and TCON.3 (IE1) are manipulated by the Bits TCON.1 (IE0) and TCON.3 (IE1) are manipulated by the processor itself. processor itself. 44


9.9. Bits TCON.1 (IE0) and TCON.3 (IE1) are manipulated by the processor Bits TCON.1 (IE0) and TCON.3 (IE1) are manipulated by the processor itself. itself.

10.10. An external signal received at An external signal received at INTOINTO would set the bit TCON.1 (also known would set the bit TCON.1 (also known as IE0) and will be cleared by the processor itself, after it branches to the as IE0) and will be cleared by the processor itself, after it branches to the corresponding ISR located at corresponding ISR located at 0003H0003H. .

11.11. Similarly TCON.3 is set when an interrupt signal is received at Similarly TCON.3 is set when an interrupt signal is received at INT1INT1 and and would be cleared by processor after branching. would be cleared by processor after branching.

12.12. The other 2 bits TCON.0 and TCON.2 are used for selecting “The other 2 bits TCON.0 and TCON.2 are used for selecting “type of type of signalsignal” received.” received.

13.13. TCON.0 (or IT0) is set to 0 – if the interrupt at INT0 is to be evoked by a TCON.0 (or IT0) is set to 0 – if the interrupt at INT0 is to be evoked by a low level signal. low level signal.

14.14. If TCON.0 is set to high, then the interrupt at INT0 would be evoked by a If TCON.0 is set to high, then the interrupt at INT0 would be evoked by a falling edge signal (high to low transition). falling edge signal (high to low transition).

15.15. Same is the case with TCON.1 – if set to 0 then low level signal would Same is the case with TCON.1 – if set to 0 then low level signal would raise an interrupt at INT1 and if set to high, then a falling edge signal raise an interrupt at INT1 and if set to high, then a falling edge signal would do the job.would do the job.

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8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTERBitBit Symbol Symbol TCON Bit Function (Bit addressable as TCON.0 to TCON.7 , Direct Byte Address is 88h.)TCON Bit Function (Bit addressable as TCON.0 to TCON.7 , Direct Byte Address is 88h.)77 TF1TF1 Timer 1 Overflow flag. Set when timer rolls from all 1's to 0. Cleared when processor Timer 1 Overflow flag. Set when timer rolls from all 1's to 0. Cleared when processor

vectors to execute interrupt service routine located at program address 001Bh.vectors to execute interrupt service routine located at program address 001Bh.

66 TR1 TR1 Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer.program to halt timer.

55 TF0 TF0 Timer 0 Overflow flag. Set when timer rolls from all 1's to 0. Cleared when processor Timer 0 Overflow flag. Set when timer rolls from all 1's to 0. Cleared when processor vectors to execute interrupt service routine located at program address 000Bh.vectors to execute interrupt service routine located at program address 000Bh.

44 TR0 TR0 Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer.program to halt timer.

33 IE1 IE1 External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received on port External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3.3 (INT1). Cleared when processor vectors to interrupt service routine at program address 3.3 (INT1). Cleared when processor vectors to interrupt service routine at program address 0013h. Not related to timer operations.0013h. Not related to timer operations.

22 IT1 IT1 External interrupt 1 signal type control bit. Set to 1 by program to enable external interrupt External interrupt 1 signal type control bit. Set to 1 by program to enable external interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal on 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal on external interrupt 1 to generate an interrupt.external interrupt 1 to generate an interrupt.

11 IE0 IE0 External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received on port External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3.2 (INT0). Cleared when processor vectors to interrupt service routine at program address 3.2 (INT0). Cleared when processor vectors to interrupt service routine at program address 0003h. Not related to timer operations.0003h. Not related to timer operations.

00 IT0 IT0 External interrupt 0 signal type control bit. Set to 1 by program to enable external interrupt External interrupt 0 signal type control bit. Set to 1 by program to enable external interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal on 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal on external interrupt 0 to generate an interrupt.external interrupt 0 to generate an interrupt.

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http://www.circuitstoday.com/external-interrupts-handling-in-805147

8051 8051 ITERRUPT ENABLE (IE) ITERRUPT ENABLE (IE) SPECIAL FUNCTION REGISTERSPECIAL FUNCTION REGISTER• There are 3 bits associated with external interrupts in IE – they are bits 0, There are 3 bits associated with external interrupts in IE – they are bits 0,

2 and 7. 2 and 7. • The main purpose of this SFR is to enable/disable different interrupts The main purpose of this SFR is to enable/disable different interrupts

based on whether it’s corresponding bits are set or not. Refer the figure based on whether it’s corresponding bits are set or not. Refer the figure above.above.

• IE.7 – is known as global interrupt bit IE.7 – is known as global interrupt bit – which when set to ’0 – disables all ′– which when set to ’0 – disables all ′kinds of interrupts in 8051. kinds of interrupts in 8051.

• Only if this bit is set to ’1″, any kind of interrupt would be enabled Only if this bit is set to ’1″, any kind of interrupt would be enabled in in 8051. 8051.

• If this bit is set to 1If this bit is set to 1, programmer can then individually enable or disable , programmer can then individually enable or disable all other interrupts INT0, INT1, Timer interrupts (0 and 1) and serial all other interrupts INT0, INT1, Timer interrupts (0 and 1) and serial interrupt.interrupt.

• IE.0IE.0 – If set to ’1 – it enables INT0 and if set to ’0 – INT0 would be ′ ′ – If set to ’1 – it enables INT0 and if set to ’0 – INT0 would be ′ ′disabled. So in order to enable external interrupt 0 (INT0) – IE.7 and IE.0 disabled. So in order to enable external interrupt 0 (INT0) – IE.7 and IE.0 should be set to ’1 .′should be set to ’1 .′

• IE.2IE.2 – Similar to IE.0 – IE.1 enables/disables external interrupt 1 (INT1). – Similar to IE.0 – IE.1 enables/disables external interrupt 1 (INT1).48

8051 8051 ITERRUPT ENABLE (IE) ITERRUPT ENABLE (IE) SPECIAL FUNCTION REGISTERSPECIAL FUNCTION REGISTER• There are 3 bits associated with external interrupts in IE – they are bits 0, There are 3 bits associated with external interrupts in IE – they are bits 0,

2 and 7. 2 and 7. • The main purpose of this SFR is to enable/disable different interrupts The main purpose of this SFR is to enable/disable different interrupts

based on whether it’s corresponding bits are set or not. Refer the figure based on whether it’s corresponding bits are set or not. Refer the figure above.above.

• IE.7 – is known as global interrupt bit IE.7 – is known as global interrupt bit – which when set to ’0 – disables all ′– which when set to ’0 – disables all ′kinds of interrupts in 8051. kinds of interrupts in 8051.

• Only if this bit is set to ’1″, any kind of interrupt would be enabled Only if this bit is set to ’1″, any kind of interrupt would be enabled in in 8051. 8051.

• If this bit is set to 1If this bit is set to 1, programmer can then individually enable or disable , programmer can then individually enable or disable all other interrupts INT0, INT1, Timer interrupts (0 and 1) and serial all other interrupts INT0, INT1, Timer interrupts (0 and 1) and serial interrupt.interrupt.

• IE.0IE.0 – If set to ’1 – it enables INT0 and if set to ’0 – INT0 would be ′ ′ – If set to ’1 – it enables INT0 and if set to ’0 – INT0 would be ′ ′disabled. So in order to enable external interrupt 0 (INT0) – IE.7 and IE.0 disabled. So in order to enable external interrupt 0 (INT0) – IE.7 and IE.0 should be set to ’1 .′should be set to ’1 .′

• IE.2IE.2 – Similar to IE.0 – IE.1 enables/disables external interrupt 1 (INT1). – Similar to IE.0 – IE.1 enables/disables external interrupt 1 (INT1).49

8051 8051 ITERRUPT PRIORITY (IP) ITERRUPT PRIORITY (IP) SPECIAL FUNCTION REGISTERSPECIAL FUNCTION REGISTER

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8051 8051 ITERRUPT PRIORITY (IP) ITERRUPT PRIORITY (IP) SPECIAL FUNCTION REGISTERSPECIAL FUNCTION REGISTER

• Basic function of this SFR is to set interrupt priority (IP). Basic function of this SFR is to set interrupt priority (IP). • By default INT0 is of priority value 1 By default INT0 is of priority value 1 (which is the highest) and INT1 (which is the highest) and INT1

is of priority value 3 (which is lower than INT0). is of priority value 3 (which is lower than INT0). • The programmer can alter this priority, if he wants! The programmer can alter this priority, if he wants! • If IP.0 is set to ’0 and then IP.2 is set to ’0 – then the priority order ′ ′If IP.0 is set to ’0 and then IP.2 is set to ’0 – then the priority order ′ ′

changes. INT1 will change to high priority and INT0 will change to changes. INT1 will change to high priority and INT0 will change to lower priority compared to INT1.lower priority compared to INT1.

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HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)

• An ISR is just like any other subroutine we write inside a program, except for An ISR is just like any other subroutine we write inside a program, except for the difference that an ISR must always end with a RETI instruction and not the difference that an ISR must always end with a RETI instruction and not with a RET instruction (as in the case of subroutines). with a RET instruction (as in the case of subroutines).

• An ISR when evoked, executes a certain lines of code that does some kind of An ISR when evoked, executes a certain lines of code that does some kind of operations. operations.

• It can be anything as defined by the programmer. It can be anything as defined by the programmer. • The only condition is The only condition is that the first line of ISR must begin from the that the first line of ISR must begin from the

corresponding vector address. corresponding vector address. Vector address of INT0 is 0003H and that of Vector address of INT0 is 0003H and that of INT1 is 0013H.INT1 is 0013H.

• Note: In some cases the ISR will be too long that it wont be practical to write Note: In some cases the ISR will be too long that it wont be practical to write all codes staring from 0003H or the other vector address. all codes staring from 0003H or the other vector address.

• In such cases, ISR can be placed at any other location in program memory and In such cases, ISR can be placed at any other location in program memory and programmer must provide an unconditional jump programmer must provide an unconditional jump to the starting address of to the starting address of ISR from the corresponding vector address. ISR from the corresponding vector address.

• Example:- The ISR of INT0 has been written from location 2000H. Now Example:- The ISR of INT0 has been written from location 2000H. Now programmer must place an instruction – ‘LJMP 2000H’ at the vector address programmer must place an instruction – ‘LJMP 2000H’ at the vector address of INT0 – 0003H.of INT0 – 0003H. 52


Note:- Note:- •Whenever an evoked interrupt is acknowledged and the processor Whenever an evoked interrupt is acknowledged and the processor branches to its corresponding vector addressbranches to its corresponding vector address, it automatically disables , it automatically disables the interrupt in IE register. the interrupt in IE register. This disabled interrupt would only be re-This disabled interrupt would only be re-enabled upon executing the enabled upon executing the RETIRETI instruction placed inside the ISR. instruction placed inside the ISR. •That is the single reason, a programmer must use RETI inside an ISR That is the single reason, a programmer must use RETI inside an ISR instead of RET instruction.instead of RET instruction. •Placing RET will also do the job of returning from interrupt routine to Placing RET will also do the job of returning from interrupt routine to main program (the calling program) main program (the calling program) but the RET instruction will not re-but the RET instruction will not re-enable the disabled interrupt in IE registerenable the disabled interrupt in IE register. . •So if an RET is used, So if an RET is used, the interrupt would be permanently disabled the interrupt would be permanently disabled after its first serving of ISR (after its first serving of ISR (unless it is enabled again by the programmer at unless it is enabled again by the programmer at some other part of the same programsome other part of the same program).).

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• So in order to write an ISR for INT0, you have to keep in mind the So in order to write an ISR for INT0, you have to keep in mind the following things:-following things:-1) 1) Place the ISR for INT0 beginning from its vector address – Place the ISR for INT0 beginning from its vector address –

0003H. 0003H. If the ISR is too long, place an unconditional jump from If the ISR is too long, place an unconditional jump from 0003H to the starting address of ISR (which is placed at some 0003H to the starting address of ISR (which is placed at some other location of program memory). The ISR must end with a other location of program memory). The ISR must end with a RETI instruction.RETI instruction.

2) 2) Select the triggering signal type of interrupt by setting/clearing Select the triggering signal type of interrupt by setting/clearing TCON.0 bit. TCON.0=1 – means interrupt would be triggered by TCON.0 bit. TCON.0=1 – means interrupt would be triggered by a falling edge signal. TCON.0 =0 – means interrupt would be a falling edge signal. TCON.0 =0 – means interrupt would be triggered by a low level signal.triggered by a low level signal.

3)3) Set IE.0 =1Set IE.0 =1 to enable the external interrupt 0 (INT0) to enable the external interrupt 0 (INT0)4)4) Set IE.7=1 Set IE.7=1 to enable the global interrupt control bit.to enable the global interrupt control bit.5) 5) Optionally, programmer can alter the priority of INT0 by Optionally, programmer can alter the priority of INT0 by

setting/clearing IP.0 (Note: This step is optional.)setting/clearing IP.0 (Note: This step is optional.) 54


• Now when it comes to external interrupt 1 – INT1 – the processes Now when it comes to external interrupt 1 – INT1 – the processes are all same, except for the change in bits that are to be are all same, except for the change in bits that are to be programmed.programmed.1) 1) Place the ISR in vector address of INT1 – 0013H.Place the ISR in vector address of INT1 – 0013H. Or if the ISR is Or if the ISR is

long, place an LJMP at 0013H to the corresponding starting long, place an LJMP at 0013H to the corresponding starting address of ISR for INT1.address of ISR for INT1.

2)2) Triggering signal type is selected by setting/clearing TCON.2. Triggering signal type is selected by setting/clearing TCON.2. TCON.2 = 0 – triggered by low level signal. TCON.2 = 1 – TCON.2 = 0 – triggered by low level signal. TCON.2 = 1 – triggered by falling edge signal.triggered by falling edge signal.

3)3) Set IE.2 = 1 Set IE.2 = 1 to enable INT1to enable INT14) 4) Set IE.7 =1 Set IE.7 =1 to enable global interrupt control bit.to enable global interrupt control bit.5) 5) Interrupt priority can be altered by changing value of IP.2 Interrupt priority can be altered by changing value of IP.2

(optional). Refer the diagram of IP register given above.(optional). Refer the diagram of IP register given above.

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How to generate Software Interrupts in 8051?How to generate Software Interrupts in 8051?•Software interrupts are nothing but an interrupt generated by a Software interrupts are nothing but an interrupt generated by a program inside the controller. program inside the controller. •To generate an external interrupt, we need a signal input either at To generate an external interrupt, we need a signal input either at INT0 or INT1 pin of the 8051 micro controller. INT0 or INT1 pin of the 8051 micro controller. •We have seen that, when an interrupt signal is received at the INT0 We have seen that, when an interrupt signal is received at the INT0 pin, the TCON.1 bit would automatically get set and that is how the pin, the TCON.1 bit would automatically get set and that is how the processor knows an interrupt signal has been received at INT0 pin. processor knows an interrupt signal has been received at INT0 pin. •When TCON.1 is set, processor would immediately acknowledge the When TCON.1 is set, processor would immediately acknowledge the interrupt and branch to the corresponding ISR of INT0. interrupt and branch to the corresponding ISR of INT0. •While branching to the ISR, processor would also clear the TCON.1 While branching to the ISR, processor would also clear the TCON.1 bit. The same happens in the case of INT1 and the associated bit is bit. The same happens in the case of INT1 and the associated bit is TCON.3.TCON.3.

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How to generate Software Interrupts in 8051?How to generate Software Interrupts in 8051?•Now in order to generate a software interrupt,Now in order to generate a software interrupt, the programmer can the programmer can manipulate these bits TCON.1 and TCON.3 manually inside a program.manipulate these bits TCON.1 and TCON.3 manually inside a program. •An instruction like ‘SETB TCON.1 ′An instruction like ‘SETB TCON.1 ′ will activate the interrupt for INT0 will activate the interrupt for INT0 (without any external signal at the INT0 pin) inside the controller. (without any external signal at the INT0 pin) inside the controller. •Now the processor will acknowledge the interrupt and branch to the Now the processor will acknowledge the interrupt and branch to the corresponding location of ISR for INT0 (vector address 0003H). corresponding location of ISR for INT0 (vector address 0003H). •After branching to ISR, the processor would clear the bit TCON.1. After branching to ISR, the processor would clear the bit TCON.1. •An instruction like ‘SETB TCON.3’ An instruction like ‘SETB TCON.3’ would activate the interrupt for would activate the interrupt for INT1 and processor would branch to ISR of INT1 located at vector INT1 and processor would branch to ISR of INT1 located at vector address 0013H. address 0013H. •While branching it would automatically clear the bit TCON.3, so that While branching it would automatically clear the bit TCON.3, so that the programmer can activate the interrupt again inside a loop or some the programmer can activate the interrupt again inside a loop or some other part of the program.other part of the program.

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ORG 00ORG 00

ENDEND

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ORG 00ORG 00

Mainloop:Mainloop:

NOPNOP

SJMPSJMP MainloopMainloop

ENDEND

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HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)ORG 00ORG 00

; Vector Address for INT0; Vector Address for INT0ORGORG 0003H0003HLJMPLJMP ISR_for_INT0ISR_for_INT0

; Vector Address for TIMER0; Vector Address for TIMER0ORGORG 000BH000BHLJMPLJMP ISR_for_TIMER0ISR_for_TIMER0



; Vector Address for Serial Communication Interrupt; Vector Address for Serial Communication InterruptORGORG 0023H0023HLJMPLJMP ISR_for_SerialComISR_for_SerialCom

Mainloop:Mainloop:NOPNOPSJMPSJMP MainloopMainloopENDEND

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HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)ORG 00ORG 00

ORGORG 0003H0003H ; Vector Address for INT0; Vector Address for INT0LJMPLJMP ISR_for_INT0ISR_for_INT0

ORGORG 000BH000BHLJMPLJMP ISR_for_TIMER0ISR_for_TIMER0 ; Vector Address for TIMER0; Vector Address for TIMER0

ORGORG 0013H0013HLJMPLJMP ISR_for_INT1ISR_for_INT1 ; Vector Address for INT1; Vector Address for INT1

ORGORG 001BH001BH ; Vector Address for TIMER1; Vector Address for TIMER1LJMPLJMP ISR_for_TIMER1ISR_for_TIMER1

ORGORG 0023H0023HLJMPLJMP ISR_for_SerialComISR_for_SerialCom ; Vector Address for Serial Communication Interrupt ; Vector Address for Serial Communication Interrupt

Mainloop:Mainloop:NOPNOPSJMPSJMP MainloopMainloop

ENDEND

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HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)ORG 00ORG 00LJmp SetupInterruptsLJmp SetupInterrupts

ORGORG 0003H0003H ; Vector Address for INT0; Vector Address for INT0LJMPLJMP ISR_for_INT0ISR_for_INT0

ORGORG 000BH000BHLJMPLJMP ISR_for_TIMER0ISR_for_TIMER0 ; Vector Address for TIMER0; Vector Address for TIMER0

ORGORG 0013H0013HLJMPLJMP ISR_for_INT1ISR_for_INT1 ; Vector Address for INT1; Vector Address for INT1

ORGORG 001BH001BH ; Vector Address for TIMER1; Vector Address for TIMER1LJMPLJMP ISR_for_TIMER1ISR_for_TIMER1

ORGORG 0023H0023HLJMPLJMP ISR_for_SerialComISR_for_SerialCom ; Vector Address for Serial Communication Interrupt ; Vector Address for Serial Communication Interrupt

SetupInterrupts:SetupInterrupts:MOV IE,#10000101B MOV IE,#10000101B ;Enable External INT0 and INT1;Enable External INT0 and INT1


ENDEND63

HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)ORG 00ORG 00LJmp SetupInterruptsLJmp SetupInterruptsORGORG 0003H0003H ; Vector Address for INT0; Vector Address for INT0LJMPLJMP ISR_for_INT0ISR_for_INT0

ORGORG 000BH000BHLJMPLJMP ISR_for_TIMER0ISR_for_TIMER0 ; Vector Address for TIMER0; Vector Address for TIMER0ORGORG 0013H0013HLJMPLJMP ISR_for_INT1ISR_for_INT1 ; Vector Address for INT1; Vector Address for INT1ORGORG 001BH001BH ; Vector Address for TIMER1; Vector Address for TIMER1LJMPLJMP ISR_for_TIMER1ISR_for_TIMER1ORGORG 0023H0023HLJMPLJMP ISR_for_SerialComISR_for_SerialCom ; Vector Address for Serial Communication Interrupt ; Vector Address for Serial Communication Interrupt

SetupInterrupts:SetupInterrupts:MOV IE, #10000101B MOV IE, #10000101B ;Enable External INT0 and INT1;Enable External INT0 and INT1


ISR_for_INT0:ISR_for_INT0:SetBSetB P1.0P1.0RETIRETI


ENDEND64


;Interrupt Vector Table;Interrupt Vector Table; ; InterruptInterrupt Memory LocationMemory Location Priority Priority;; INT0 INT0 0003H0003H (8 Bytes from 0003 to 000A h) (8 Bytes from 0003 to 000A h) 1 1;; TIMER0 TIMER0 000BH000BH (8 Bytes from 000B to 0012 h) (8 Bytes from 000B to 0012 h) 2 2;; INT1 INT1 0013H0013H (8 Bytes from 0013 to 001A h) (8 Bytes from 0013 to 001A h) 3 3;; TIMER1 TIMER1 001BH001BH (8 Bytes from 001B to 0022 h) (8 Bytes from 001B to 0022 h) 4 4;; SERIAL COMMUNICATION INTERRUPT SERIAL COMMUNICATION INTERRUPT 0023H0023H 5 5;; (8 Bytes from 0023 to 002A) (8 Bytes from 0023 to 002A)






;Main Initilazation;Main InitilazationORG 30HORG 30H

SetupInterrupts: SetupInterrupts: ; preprocess a few bits 3 SFR’s namely TCON, IE and IP; preprocess a few bits 3 SFR’s namely TCON, IE and IP; 1. TCON Register is to be configured for enabling type of signal. ; 1. TCON Register is to be configured for enabling type of signal. ; Let it remain with default values.; Let it remain with default values.; 2. IE Register: Configure Interrupt Enable Register. ; 2. IE Register: Configure Interrupt Enable Register. ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1 ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1

;MOV IE,#10000100B ;MOV IE,#10000100B ;Enable External INT1;Enable External INT1MOV IE,#10000101B MOV IE,#10000101B ;Enable External INT0 and INT1;Enable External INT0 and INT1

; 3. IP Register: Special Function Register IP is to be configured ; 3. IP Register: Special Function Register IP is to be configured ; ; for changing priority of interrupts. for changing priority of interrupts.;; Let it have default values Let it have default values

Mainloop:Mainloop:

NOPNOP

SJMPSJMP MainloopMainloop


ISR_for_TIMER0:ISR_for_TIMER0:SetBSetB P1.1P1.1RETIRETI



ISR_for_SerialCom:ISR_for_SerialCom:SetBSetB P1.4P1.4RETIRETI

ENDEND

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;Interrupt Vector Table;Interrupt Vector Table; ; InterruptInterrupt Memory LocationMemory Location Priority Priority;; INT0 INT0 0003H0003H (8 Bytes from 0003 to 000A h) (8 Bytes from 0003 to 000A h) 1 1;; TIMER0 TIMER0 000BH000BH (8 Bytes from 000B to 0012 h) (8 Bytes from 000B to 0012 h) 2 2;; INT1 INT1 0013H0013H (8 Bytes from 0013 to 001A h) (8 Bytes from 0013 to 001A h) 3 3;; TIMER1 TIMER1 001BH001BH (8 Bytes from 001B to 0022 h) (8 Bytes from 001B to 0022 h) 4 4;; SERIAL COMMUNICATION INTERRUPT SERIAL COMMUNICATION INTERRUPT 0023H0023H 5 5;; (8 Bytes from 0023 to 002A) (8 Bytes from 0023 to 002A)




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HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE); Vector Address for TIMER1; Vector Address for TIMER1ORGORG 001BH001BHLJMPLJMP ISR_for_TIMER1ISR_for_TIMER1


;Main Initilazation;Main InitilazationORG 30HORG 30H

SetupInterrupts: SetupInterrupts: ; preprocess a few bits 3 SFR’s namely TCON, IE and IP; preprocess a few bits 3 SFR’s namely TCON, IE and IP; 1. TCON Register is to be configured for enabling type of signal. ; 1. TCON Register is to be configured for enabling type of signal. ; Let it remain with default values.; Let it remain with default values.; 2. IE Register: Configure Interrupt Enable Register. ; 2. IE Register: Configure Interrupt Enable Register. ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1 ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1

;MOV IE,#10000100B ;MOV IE,#10000100B ;Enable External INT1;Enable External INT1MOV IE,#10000101B MOV IE,#10000101B ;Enable External INT0 and INT1;Enable External INT0 and INT1

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HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE)HOW TO WRITE AN ISR (INTERRUPT SERVICE ROUTINE); 3. IP Register: Special Function Register IP is to be configured ; 3. IP Register: Special Function Register IP is to be configured ; ; for changing priority of interrupts. for changing priority of interrupts.;; Let it have default values Let it have default values






ISR_for_SerialCom:ISR_for_SerialCom:SetBSetB P1.4P1.4RETIRETI

ENDEND 68

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INTERRUPT HANDLING IN 8051INTERRUPT HANDLING IN 8051

• We shall consider two projects using microcontroller 8051:-We shall consider two projects using microcontroller 8051:-1.1. Security Alarm System:Security Alarm System: Real Time SystemReal Time System2.2. Temperature Controller for an Air Conditioner: Embedded System.Temperature Controller for an Air Conditioner: Embedded System.

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REAL TIME AND EMBEDDED OPERATING SYSTEMSREAL TIME AND EMBEDDED OPERATING SYSTEMS

IntroductionIntroduction• Real-time systems are special systems where Real-time systems are special systems where timeliness of responsestimeliness of responses to to

user/external requests plays a very crucial role, apart from their logical user/external requests plays a very crucial role, apart from their logical correctness. correctness.

• TraditionallyTraditionally, real-time systems often referred to large, high-powered, , real-time systems often referred to large, high-powered, expensive systems such as expensive systems such as

–air-traffic control systems, air-traffic control systems, –defence and space command and control systems, defence and space command and control systems, –space exploration systems, space exploration systems, –industrial process control systems, industrial process control systems, –industrial robots, industrial robots, –telecommunication systems, telecommunication systems, –medical equipments, medical equipments, –electricity distribution and power plant control systems. electricity distribution and power plant control systems.

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Introduction…Introduction…• As the use of computer-controlled systems has pervaded (As the use of computer-controlled systems has pervaded (extended extended

throughthrough) our daily life, ) our daily life, real-time systems are no longer limited to real-time systems are no longer limited to these large systemsthese large systems. .

• Devices such as Devices such as mobile phones, PDAs, TVs, DVD players, cameras, mobile phones, PDAs, TVs, DVD players, cameras, cars, fax machines, printers, refrigerators, dishwashers, wireless cars, fax machines, printers, refrigerators, dishwashers, wireless routers, and entertainment machines,routers, and entertainment machines, operate mostly in real-time operate mostly in real-time modes modes and, therefore, they too fall into the category of real-time and, therefore, they too fall into the category of real-time systems. systems.

• These systems/devices have one- or more programmable These systems/devices have one- or more programmable computing elements.computing elements.

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Introduction…Introduction…•A recent study indicates that A recent study indicates that more than ninety per cent of more than ninety per cent of microprocessors are embedded in consumer products microprocessors are embedded in consumer products and other real-and other real-time systems. time systems. •The vast majority of these microprocessors areThe vast majority of these microprocessors are embedded in embedded in equipment, machines, and appliances found in homes, workplaces, equipment, machines, and appliances found in homes, workplaces, automobiles, and carried by or implanted in humans, birds, and animals.automobiles, and carried by or implanted in humans, birds, and animals.•>>For many practical systems, >>For many practical systems, real-time requirement and real-time requirement and embeddedness are two necessary- and, often, related aspects. embeddedness are two necessary- and, often, related aspects. •ThereforeTherefore, in such a context, in such a context, a real-time system or an embedded , a real-time system or an embedded system is essentially the same. The term real-time emphasizes the system is essentially the same. The term real-time emphasizes the importance of the “timing” aspect of the system and the term importance of the “timing” aspect of the system and the term embeddedness the computing element embedded in the system as the embeddedness the computing element embedded in the system as the key unit, and key unit, and whose resources are often limitedwhose resources are often limited..

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Introduction…Introduction…•>>Although >>Although now the term real-time implies “fast enough” or “time-now the term real-time implies “fast enough” or “time-bound”bound”, in the beginning it was used to refer to the speed that , in the beginning it was used to refer to the speed that matched the speed of the original system being simulated.matched the speed of the original system being simulated.

•Almost all real time systems have Almost all real time systems have one or more “embedded one or more “embedded computing elements”computing elements”. . •Here the term embedded means a computing element is inserted Here the term embedded means a computing element is inserted instead of implanted as an integral part of the system. instead of implanted as an integral part of the system. •In some systems, the presence of the embedded computing element In some systems, the presence of the embedded computing element is not apparent to end users. is not apparent to end users. •The systems where programmable computing elements are The systems where programmable computing elements are embedded inside, are generally referred to as embedded systems. embedded inside, are generally referred to as embedded systems.

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Introduction…Introduction…•Also, Also, since most embedded systems operate under some level of since most embedded systems operate under some level of real-time requirementsreal-time requirements they are also real-time systemsthey are also real-time systems. . •Therefore, we do not make technical distinctions between a real-time Therefore, we do not make technical distinctions between a real-time system and an embedded system. system and an embedded system. •We use both terms interchangeably, whichever suits the context best, We use both terms interchangeably, whichever suits the context best, and often refer to them as and often refer to them as RE systemsRE systems. . •In the domain of RE systemsIn the domain of RE systems, the term “task” is used to refer to what , the term “task” is used to refer to what in traditional computing systems is termed a process. in traditional computing systems is termed a process. •Essentially, the execution of a process carries out the intended task. Essentially, the execution of a process carries out the intended task. Therefore, we use task in place of process in this chapter (Chapter 15). Therefore, we use task in place of process in this chapter (Chapter 15). •In RE systems, tasks can be scheduled In RE systems, tasks can be scheduled (arranged) (arranged) for execution. for execution.

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Introduction…Introduction…•Programmable computing elements Programmable computing elements with associated software inside a with associated software inside a larger system form the larger system form the embedded computing systemembedded computing system. . •LikewiseLikewise, programmable computing elements with associated , programmable computing elements with associated software software inside a larger real-time system inside a larger real-time system form the real-time form the real-time computing system. computing system. •In any case, these computing elements are expected to operate in a In any case, these computing elements are expected to operate in a specialized manner to satisfy specific requirements of the larger specialized manner to satisfy specific requirements of the larger systems in which they are embedded. systems in which they are embedded. •Since our focus is on the computing aspectSince our focus is on the computing aspect, hereafter, unless , hereafter, unless mentioned otherwise, a real-time (embedded) system essentially mentioned otherwise, a real-time (embedded) system essentially refers to a real-time (embedded) computing system. refers to a real-time (embedded) computing system.

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Introduction…Introduction…•Depending upon the application and its requirementsDepending upon the application and its requirements, a computing , a computing element in an RE system element in an RE system could be a general-purpose microprocessor could be a general-purpose microprocessor or or a a special-purpose microcontrollerspecial-purpose microcontroller. . •Consequently, an RE system can be simple enough to include a small Consequently, an RE system can be simple enough to include a small specialized microcontroller or require massive parallel processors with specialized microcontroller or require massive parallel processors with huge memory and computing power. huge memory and computing power. •The question of what actually constitutes an RE system, purely from The question of what actually constitutes an RE system, purely from computing point of view, is debatable.computing point of view, is debatable.•We must first understand, at least to some extent, what constitutes an We must first understand, at least to some extent, what constitutes an RE system in order to understand the operating-system-specific RE system in order to understand the operating-system-specific requirements of such systems. requirements of such systems. •In this chapter, we first take a brief look at the In this chapter, we first take a brief look at the characteristicscharacteristics and hardware and hardware organizationorganization of typical RE systems. of typical RE systems. Then, we briefly discuss some of the operating Then, we briefly discuss some of the operating system structures, important issues, and solutions to such issues.system structures, important issues, and solutions to such issues. 98


The Characteristics of an RE SystemThe Characteristics of an RE System•Although opinions about what constitute an RE system can vary, it is Although opinions about what constitute an RE system can vary, it is widely accepted that RE systems have some or all of the following widely accepted that RE systems have some or all of the following important characteristics.important characteristics.1. Application-specific.1. Application-specific. – Each real-time system is intended for a specific application. Each real-time system is intended for a specific application. – As mentioned earlier, real-time systems such as consumer As mentioned earlier, real-time systems such as consumer

electronics, medical devices, transport systems, military electronics, medical devices, transport systems, military systems, etc., are designed for specific applications. systems, etc., are designed for specific applications.

– The software for these systems must be tailor-made to suit the The software for these systems must be tailor-made to suit the applications.applications.

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The Characteristics of an RE System…The Characteristics of an RE System…2. Timeliness (Real-time constraint)2. Timeliness (Real-time constraint). .

– Most embedded systems interact with the environment through their Most embedded systems interact with the environment through their interfacing hardware components and, therefore, the components must interfacing hardware components and, therefore, the components must operate in a “real-time” frame to react in timely fashion to the physical operate in a “real-time” frame to react in timely fashion to the physical processes taking place in the environment. processes taking place in the environment.

– The term real-time means a time-bound responseThe term real-time means a time-bound response. Performance degradation . Performance degradation and/or system failure will occur if responses are not delivered within the and/or system failure will occur if responses are not delivered within the specified time. specified time.

– The systems are often “reactive” to respond to incoming events and change The systems are often “reactive” to respond to incoming events and change states at their speed. states at their speed.

– A program in a real-time system must be both logically and temporally (A program in a real-time system must be both logically and temporally (of of

limited time, related to timelimited time, related to time) correct. ) correct. – The real-time constraint of a task is specified in terms of a deadline—an The real-time constraint of a task is specified in terms of a deadline—an

absolute or a relative time by when the task must complete. absolute or a relative time by when the task must complete. – That is, real-time systems demand a limit on the response time.That is, real-time systems demand a limit on the response time.

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The Characteristics of an RE System…The Characteristics of an RE System…3. Dynamic behaviour3. Dynamic behaviour. . – Due to unpredictable interactions with the environment and Due to unpredictable interactions with the environment and

other systems, the components of real-time systems often carry other systems, the components of real-time systems often carry a high level of concurrent activities. a high level of concurrent activities.

– Many components interact with each other and compete for Many components interact with each other and compete for resources. resources.

– Asynchronous (Asynchronous (not occurring at predetermined or regular intervalsnot occurring at predetermined or regular intervals) ) events are notified to the processor through interrupts events are notified to the processor through interrupts and, and, thus, interrupts are important for all real-time systems. thus, interrupts are important for all real-time systems.

– Systems which have an interrupt mechanism are inherently Systems which have an interrupt mechanism are inherently concurrent and, therefore, their behaviour is usually highly concurrent and, therefore, their behaviour is usually highly dynamic.dynamic.

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REAL TIME AND EMBEDDED OPERATING SYSTEMSREAL TIME AND EMBEDDED OPERATING SYSTEMSThe Characteristics of an RE System…The Characteristics of an RE System…4. Reliability and fault tolerance.4. Reliability and fault tolerance.– As RE systems often operate in life-or mission-critical situations, As RE systems often operate in life-or mission-critical situations, they they

are expected to be highly reliable and fault tolerant. are expected to be highly reliable and fault tolerant. – A system is reliable if a small number of failures do not seriously A system is reliable if a small number of failures do not seriously

impair its satisfactory operation. impair its satisfactory operation. – The measure of reliability depends on how often a system will fail The measure of reliability depends on how often a system will fail

and when it indeed fails, how difficult it is to make the system and when it indeed fails, how difficult it is to make the system operational again. operational again.

– Fault tolerance is recognizing and handling such failures Fault tolerance is recognizing and handling such failures systematically. It is the ability of the system to respond gracefully to systematically. It is the ability of the system to respond gracefully to an unexpected failure situation. an unexpected failure situation.

– A reliable and fault tolerant system can respond to faults at many A reliable and fault tolerant system can respond to faults at many levels ranging from stopping gracefully to continuing to operate in a levels ranging from stopping gracefully to continuing to operate in a reduced capacity.reduced capacity.

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REAL TIME AND EMBEDDED OPERATING SYSTEMSREAL TIME AND EMBEDDED OPERATING SYSTEMSThe Characteristics of an RE System…The Characteristics of an RE System…4. Reliability and fault tolerance…4. Reliability and fault tolerance…

– A related factor is criticality, which is a measure of the cost of failure. A A related factor is criticality, which is a measure of the cost of failure. A system is called system is called safety critical safety critical if human lives or the intactness of the facilities if human lives or the intactness of the facilities or equipment directly depend on its correct timely operation. or equipment directly depend on its correct timely operation.

– Based on the severity of the cost, real-time systems are classified into two Based on the severity of the cost, real-time systems are classified into two categories: categories: hard and softhard and soft. .

– Hard real-time systems must satisfy their timing and deadline constraintsHard real-time systems must satisfy their timing and deadline constraints. . Otherwise, the system will fail. Otherwise, the system will fail.

– On the other hand, On the other hand, soft real-time systems can accept missing some deadline soft real-time systems can accept missing some deadline constraintsconstraints as long as they achieve their mission. as long as they achieve their mission.

– Most practical systems fall in between the two. Most practical systems fall in between the two. – To assure high fault tolerance, some real-time systems are equipped with To assure high fault tolerance, some real-time systems are equipped with

redundant components and, hence, require added coordination between redundant components and, hence, require added coordination between those components.those components.

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The Characteristics of an RE System…The Characteristics of an RE System…• ≫ ≫ The following excerpt from literature nicely captures the The following excerpt from literature nicely captures the importance of fault tolerance in real-time systems. importance of fault tolerance in real-time systems. •““If the software had an error rate of 0.1%, If the software had an error rate of 0.1%, then this would lead to 500 then this would lead to 500 exceptions in surgeries per week and 18 airplane crashes per day”.exceptions in surgeries per week and 18 airplane crashes per day”.

• ≫ ≫ A hard real-time system is a special purpose system which A hard real-time system is a special purpose system which guarantees completion of real-time tasks within their deadlines.guarantees completion of real-time tasks within their deadlines.

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The Characteristics of an RE System…The Characteristics of an RE System…5. Limited Testing5. Limited Testing. . – For many systems, it is usually impossible or expensive to test For many systems, it is usually impossible or expensive to test

and debug the system with their actual complete environments. and debug the system with their actual complete environments. – These systems rely on These systems rely on • careful system specifications, careful system specifications, • systematic and comprehensive analysis and design, systematic and comprehensive analysis and design, • extensive runtime procedures for fault detection and extensive runtime procedures for fault detection and

handling, handling, • testing of sub-systems, and testing of sub-systems, and • simulationsimulation..

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The Characteristics of an RE System…The Characteristics of an RE System…6. Flexible Networking6. Flexible Networking. . – Most embedded devices are increasingly expected to work Most embedded devices are increasingly expected to work

together by way of forming “together by way of forming “ad-hoc networksad-hoc networks” when needed. ” when needed. – Typical examples are Typical examples are • next generation building and factory automation systems, next generation building and factory automation systems, • automated highways, automated highways, • advanced air traffic control, advanced air traffic control, • unmanned military vehicles and the like. unmanned military vehicles and the like.

– Networking makes the timing assurance more complex, because Networking makes the timing assurance more complex, because the the combination of tasks involved combination of tasks involved when networked when networked is not known is not known at the time of design of an individual device.at the time of design of an individual device.

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The Characteristics of an RE System…The Characteristics of an RE System…7. Autonomy7. Autonomy. . – Some embedded devices are required to function Some embedded devices are required to function without without

maintenance for long durationsmaintenance for long durations. . – For example, For example, • building automation systems, building automation systems, • military equipment, military equipment, • and sensor networks deployed in forests and oceans and sensor networks deployed in forests and oceans are required to operate are required to operate for several years for several years without maintenance without maintenance

and human supervision.and human supervision.

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REAL TIME AND EMBEDDED OPERATING SYSTEMSREAL TIME AND EMBEDDED OPERATING SYSTEMSThe Characteristics of an RE System…The Characteristics of an RE System…8. Interfacing.8. Interfacing.– Unlike traditional computer systems Unlike traditional computer systems that have standard user that have standard user

interfaces such as keyboard, mouse, etc., interfaces such as keyboard, mouse, etc., embedded systems come embedded systems come withwith a range of interface devices a range of interface devices—from no interface at all to many —from no interface at all to many highly customizable interfaces. highly customizable interfaces.

– Interface devices include Interface devices include sensors, actuators, motors, switches, sensors, actuators, motors, switches, display panels, communication links, signal convertersdisplay panels, communication links, signal converters, and so forth. , and so forth.

– Unlike traditional computer systems where the processor is the Unlike traditional computer systems where the processor is the major unitmajor unit, most embedded systems are I/O dominated systems. , most embedded systems are I/O dominated systems.

– In addition, In addition, most real-time systems have one or more humans to most real-time systems have one or more humans to interact with and who control theminteract with and who control them. .

– Human-machine interfaces must be carefully designed to avoid Human-machine interfaces must be carefully designed to avoid human errors.human errors.

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The Characteristics of an RE System…The Characteristics of an RE System…9. Limited Resources.9. Limited Resources. – Most small, embedded devices are designed under space-, Most small, embedded devices are designed under space-,

weight-, and energy constraints imposed by the applications. weight-, and energy constraints imposed by the applications. – Consequently, recent research on embedded systems has Consequently, recent research on embedded systems has

heavily focused on resource limitations. heavily focused on resource limitations. – Hence, Hence, in some sensein some sense, , embedded systems are characterized as embedded systems are characterized as

the systems with limited memory, computing, and battery the systems with limited memory, computing, and battery power. power.

– Systems with restrictions of size and power are also referred to Systems with restrictions of size and power are also referred to in literature as small computers.in literature as small computers.

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The Characteristics of an RE System…The Characteristics of an RE System…•>> An embedded computer system is >> An embedded computer system is one of the components one of the components of a of a larger systemlarger system. . The larger system may include other components such The larger system may include other components such as mechanical-, chemical-, and electrical devices. as mechanical-, chemical-, and electrical devices. Further, such Further, such systems systems are designed for specific purposesare designed for specific purposes, and they , and they usually require usually require the knowledge of the specific application for which they are designedthe knowledge of the specific application for which they are designed and operated under certain real-time constraints.and operated under certain real-time constraints.

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The Characteristics of an RE System…The Characteristics of an RE System…•ConciselyConcisely, ,

– systems with emphasis on real-time constraints are generally systems with emphasis on real-time constraints are generally referred to as real-time systems, and systems embedded with referred to as real-time systems, and systems embedded with computing elements are generally referred to as embedded computing elements are generally referred to as embedded systems. systems.

– A computing system embedded in these larger host systems A computing system embedded in these larger host systems derives its name from its hostderives its name from its host, that is, , that is, eithereither as real-time as real-time computing system computing system oror embedded, depending on how the host embedded, depending on how the host system is referred. system is referred.

– In almost all cases. these systems typically have real-time In almost all cases. these systems typically have real-time constraints, resource limitations, and one or more other properties constraints, resource limitations, and one or more other properties listed above. listed above. Therefore, real—time system and embedded system Therefore, real—time system and embedded system typically refer to the same, and as mentioned previously we call typically refer to the same, and as mentioned previously we call them them RE systemsRE systems.. 111


The Characteristics of an RE System…The Characteristics of an RE System…•Processors in RE systems must react to requirements of other Processors in RE systems must react to requirements of other components in a timely manner. Other components may work either components in a timely manner. Other components may work either independently or interactively and, therefore, most of these systems independently or interactively and, therefore, most of these systems are highly concurrent.are highly concurrent.•To interact with environment, these systems come with various types To interact with environment, these systems come with various types of interfaces. of interfaces. •Liveness, timeliness, and fault-tolerance are fundamental aspects of Liveness, timeliness, and fault-tolerance are fundamental aspects of these systemsthese systems. . •One of the essential characteristics of these systems is that, One of the essential characteristics of these systems is that, in in addition to logical correctness, addition to logical correctness, they have to produce the results on they have to produce the results on time. time.

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• With this introduction to characteristics of RE systems, With this introduction to characteristics of RE systems, we identify we identify some important some important challengeschallenges of these systems and discuss some of these systems and discuss some popular approaches popular approaches to deal with them to deal with them from the “operating from the “operating systems” point of view. systems” point of view.

• To understand the requirements of operating systems specific for To understand the requirements of operating systems specific for RE systems, RE systems, we first discuss their hardware aspects.we first discuss their hardware aspects.

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SECTION B• Real Time and Embedded Operating Systems: Real Time and Embedded Operating Systems: – Introduction, Introduction, – Hardware Elements, Hardware Elements,

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HARDWARE ELEMENTSHARDWARE ELEMENTS

• From the various characteristics described above, it is obvious that From the various characteristics described above, it is obvious that special purpose hardware elements are preferred over general-special purpose hardware elements are preferred over general-purpose hardware elements to construct RE systemspurpose hardware elements to construct RE systems. .

• In this section, we briefly review In this section, we briefly review some typical hardware elements some typical hardware elements that are used to construct computing elements in RE systems.that are used to construct computing elements in RE systems.

• First, we discuss individual elements First, we discuss individual elements such as such as – processor, processor, – memory, memory, – I/O device, I/O device, – communication device, communication device, and and – other elements separately, and other elements separately, and then show then show how they can be put together to how they can be put together to

construct complete RE systems.construct complete RE systems.

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1. Processing Elements.1. Processing Elements.•The microprocessor is the key element in modern RE systems. The microprocessor is the key element in modern RE systems. Central Central processing units (CPUs) are the brains of any computing system, and in processing units (CPUs) are the brains of any computing system, and in the early era, were designed combining several integrated chips. the early era, were designed combining several integrated chips. •A microprocessor is a programmable digital electronic component A microprocessor is a programmable digital electronic component that incorporates the functions of a CPU on a single-chip. that incorporates the functions of a CPU on a single-chip. •Its functionality is characterized by a set of instructions that it Its functionality is characterized by a set of instructions that it executes. executes. •Microprocessors are very efficient means to implement digital Microprocessors are very efficient means to implement digital systems and are available in varying levels of sophistication. systems and are available in varying levels of sophistication. •Their uses range from Their uses range from simple home appliances to the largest simple home appliances to the largest mainframe computers. mainframe computers. •Most embedded systems use Most embedded systems use special purpose microprocessorsspecial purpose microprocessors..

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1. Processing Elements…1. Processing Elements…•Embedded systems are used for Embedded systems are used for numerous applications involving numerous applications involving analogue signals. analogue signals. •Typical tasks Typical tasks include include – processing various sensor values from the environment, processing various sensor values from the environment, – instrumentation, instrumentation, – speech processing, speech processing, – telecommunications, telecommunications, – and system control.and system control.

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1. Processing Elements…1. Processing Elements…•In the past, such tasks were performed using analogue techniques In the past, such tasks were performed using analogue techniques and subsequently were moved to digital techniques, called and subsequently were moved to digital techniques, called digital digital signal processingsignal processing. . •Digital signal processing involves intensive arithmetic calculations. Digital signal processing involves intensive arithmetic calculations. •To achieve high speed processing, the basic computing engine, To achieve high speed processing, the basic computing engine, called called Digital Signal Processor (DSP), Digital Signal Processor (DSP), is built around a high-speed is built around a high-speed multiplier/accumulator combination. multiplier/accumulator combination. •>> The first microprocessor Intel 4004, debuted (>> The first microprocessor Intel 4004, debuted (debut: to start; to arrive; first debut: to start; to arrive; first appearanceappearance) in 1971, was designed for a calculator, which is an embedded device. ) in 1971, was designed for a calculator, which is an embedded device. •>> Programming DSPs is a tedious task generally done in a low level, assembly or >> Programming DSPs is a tedious task generally done in a low level, assembly or closer to it. Its instructions are optimized to perform fast- and efficient arithmetic, closer to it. Its instructions are optimized to perform fast- and efficient arithmetic, particularly floating point operations. The majority of programming effort goes into particularly floating point operations. The majority of programming effort goes into ensuring proper decimal points and overflow issues. ensuring proper decimal points and overflow issues.

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1. Processing Elements…1. Processing Elements…•Many components in a real-time system are required to maintain Many components in a real-time system are required to maintain predictable performance irrespective of changing conditions in the predictable performance irrespective of changing conditions in the system. system. •For example, components such as pumps, belts, and shafts are For example, components such as pumps, belts, and shafts are expected to maintain a preset speed irrespective of changes in the expected to maintain a preset speed irrespective of changes in the load on the system. load on the system. •DSP delivers the rapid response and accurate results DSP delivers the rapid response and accurate results required for required for highly responsive control systems. highly responsive control systems. •In summary, In summary, processing elements are processing elements are either either specialized specialized microprocessors called microcontrollers microprocessors called microcontrollers or general purpose or general purpose microprocessors. microprocessors.

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2. Memory Elements. 2. Memory Elements. •Many types of memory devices are now available for embedded Many types of memory devices are now available for embedded computer systems. computer systems. •They can be classified as read-only memory (They can be classified as read-only memory (ROMROM), random access ), random access memory (memory (RAMRAM), and ), and hybrid memorieshybrid memories. . •ROMROM is non-volatile and, therefore, retains its content even when the is non-volatile and, therefore, retains its content even when the power is switched off. It is usually fast for reading, but to write on it power is switched off. It is usually fast for reading, but to write on it requires special techniques. requires special techniques. •On the other hand, On the other hand, RAMRAM is volatile and, therefore, retains its content is volatile and, therefore, retains its content only when the power is on. only when the power is on. •As technology improved, the boundary between ROMs and RAMs As technology improved, the boundary between ROMs and RAMs blurred and many recent versions of memory have attractive blurred and many recent versions of memory have attractive properties of both. properties of both.

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Memory Elements… Memory Elements… •These new types of memories are known as These new types of memories are known as hybrid memorieshybrid memories. Hybrid . Hybrid memories can be accessed (that is, read/written) like RAMs, and memories can be accessed (that is, read/written) like RAMs, and retain their content without power like ROMsretain their content without power like ROMs. .

•>> Recent advancements in memory have narrowed the gap between >> Recent advancements in memory have narrowed the gap between ROM and RAM technologies and paved the way for hybrid memories. ROM and RAM technologies and paved the way for hybrid memories. •These memories can be read and written like RAMs, and like ROMs, These memories can be read and written like RAMs, and like ROMs, maintain their content without electrical power. maintain their content without electrical power. •Some hybrids are evolved from RAMs and the others from ROMs. Some hybrids are evolved from RAMs and the others from ROMs.

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2. Memory Elements… 2. Memory Elements… •In most embedded systems, the program execution environment is In most embedded systems, the program execution environment is generally generally dynamicdynamic ( (data values change constantly and tasks are often created, data values change constantly and tasks are often created, executed, and removed from the systemsexecuted, and removed from the systems). ). •Also, since most large program codes and data are brought piecemeal Also, since most large program codes and data are brought piecemeal based on the current requirement and placed wherever memory is based on the current requirement and placed wherever memory is available, RAMs are convenient for storing such general data and available, RAMs are convenient for storing such general data and performing tasks at runtime. performing tasks at runtime. •RAM requires electrical power to retain its contentRAM requires electrical power to retain its content. Content is lost . Content is lost irretrievably when power is turned off. irretrievably when power is turned off. •Based on the lifetime of the content during power-onBased on the lifetime of the content during power-on, RAM can be , RAM can be classified classified as static RAM as static RAM (SRAM) and (SRAM) and dynamic RAM dynamic RAM (DRAM). (DRAM). •SRAMsSRAMs retain their content as long as the power is on and retain their content as long as the power is on and DRAMDRAM retains content only for a short, duration (retains content only for a short, duration (about 4 msabout 4 ms). ).

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2. Memory Elements… 2. Memory Elements… •A DRAM needs a controller to refresh its memory content A DRAM needs a controller to refresh its memory content periodically. periodically. •Dynamic random-access memory (Dynamic random-access memory (DRAMDRAM) is a type of random-access ) is a type of random-access memory that stores each bit of memory that stores each bit of data in a separate capacitor data in a separate capacitor within an within an integrated circuit. The capacitor can be either charged or discharged; integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, these two states are taken to represent the two values of a bit, conventionally called 0 and 1. conventionally called 0 and 1. Since capacitors leak chargeSince capacitors leak charge, the , the information eventually fades unless the capacitor charge is refreshed information eventually fades unless the capacitor charge is refreshed periodically. periodically. Because of this refresh requirement, it is a dynamic Because of this refresh requirement, it is a dynamic memory as opposed to SRAM memory as opposed to SRAM and other static memory.and other static memory.

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2. Memory Elements… 2. Memory Elements… •A SRAM is fast and expensive compared to a DRAM. A SRAM is fast and expensive compared to a DRAM. So, normal So, normal systems tend to have a small SRAM for critical data systems tend to have a small SRAM for critical data and code and a and code and a large DRAM to hold the rest of the code and data during executionlarge DRAM to hold the rest of the code and data during execution. . Basic DRAMs are Basic DRAMs are designed to issue memory operations sequentiallydesigned to issue memory operations sequentially, , and the synchronization is done by applying control signals and the synchronization is done by applying control signals asynchronously, not by regular clock pulses. That isasynchronously, not by regular clock pulses. That is, in DRAMs, the , in DRAMs, the instruction for the next operation is issued after the completion of the instruction for the next operation is issued after the completion of the current operation. current operation. •SynchronousSynchronous DRAMs ( DRAMs (SDRAMSSDRAMS) ) are synchronized are synchronized with clock pulses to with clock pulses to respond to incoming operations. respond to incoming operations. •SDRAMs respond to the next operation before completing the current SDRAMs respond to the next operation before completing the current operation, because operation, because they can accept operations synchronized with clock they can accept operations synchronized with clock pulses and need not wait for asynchronous control signalspulses and need not wait for asynchronous control signals. . The The purpose is to increase memory bandwidth. purpose is to increase memory bandwidth. 125


2. Memory Elements… 2. Memory Elements… •To increase the bandwidth further, memories are designed with To increase the bandwidth further, memories are designed with multiports multiports through which data can be accessed simultaneously by through which data can be accessed simultaneously by many agents, and are called mulliport memories. many agents, and are called mulliport memories. •SRAMs have been improved and work with backup battery SRAMs have been improved and work with backup battery and such and such classes of SRAMs are referred to as classes of SRAMs are referred to as non-volatile RAMs non-volatile RAMs ((NVRAMsNVRAMs). ). •When power is on, NVRAMs work like SRAMs and when power is off, When power is on, NVRAMs work like SRAMs and when power is off, they automatically draw power from the battery backup. they automatically draw power from the battery backup. •NVRAMs are more expensive than SRAMsNVRAMs are more expensive than SRAMs. . •Since a majority of the code Since a majority of the code and, perhaps, and, perhaps, some data some data too do not too do not change over time in most embedded systems, these systems make change over time in most embedded systems, these systems make extensive use of ROM memories to hold critical- and stable code and extensive use of ROM memories to hold critical- and stable code and data. Also, the code and relevant data must be retained even when data. Also, the code and relevant data must be retained even when the power is off. the power is off.

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2. Memory Elements… 2. Memory Elements… •Based on the technique employed to write and the number of times it Based on the technique employed to write and the number of times it can be rewritten, can be rewritten, ROMs can be classified ROMs can be classified into three familiesinto three families: : factory factory programmed programmed (also Called masked ROM), (also Called masked ROM), programmable ROM (PROM)programmable ROM (PROM), , and and erasable-and programmable ROM (EPROM)erasable-and programmable ROM (EPROM). . •Masked ROMs Masked ROMs come with a particular code written (hardwired) in it and are come with a particular code written (hardwired) in it and are produced when large quantities of a single program are required for applications. produced when large quantities of a single program are required for applications. The contents of a masked ROM must be specified before production of the chip. The contents of a masked ROM must be specified before production of the chip. •The next family of ROMs is the The next family of ROMs is the PROMPROM which, once fabricated, can be programmed which, once fabricated, can be programmed only once (also known as only once (also known as one-time programmable one-time programmable ROM (OTP-ROM)). ROM (OTP-ROM)). After that, its After that, its content never changes. content never changes. •EPROMEPROM is the third family. It works same way as the PROM except that it can be is the third family. It works same way as the PROM except that it can be reprogrammed many times. Its content is erased with ultraviolet (UV) light and, reprogrammed many times. Its content is erased with ultraviolet (UV) light and, therefore, is therefore, is often referred to as UV-EPROMoften referred to as UV-EPROM. EPROMs required UV light to erase . EPROMs required UV light to erase their content before reprogramming which required electrical power. their content before reprogramming which required electrical power.

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2. Memory Elements… 2. Memory Elements… •Electrically erasable and programmable ROMs Electrically erasable and programmable ROMs ((EEPROMsEEPROMs) use electricity for ) use electricity for both erasing and reprogramming. Again, these earlier EEPROM memories both erasing and reprogramming. Again, these earlier EEPROM memories required removal from the computer for reprogramming (erasing and writing required removal from the computer for reprogramming (erasing and writing new programs) in the lab and new programs) in the lab and needed nigh voltages for reprogrammingneeded nigh voltages for reprogramming. . •The modern EEPROMThe modern EEPROM, , called flash memorycalled flash memory, requires only low voltage for , requires only low voltage for reprogramming and, therefore, uses the standard system voltage for reprogramming and, therefore, uses the standard system voltage for reprogramming. reprogramming. This facilitates reprogramming inside a typical embedded This facilitates reprogramming inside a typical embedded system. system. •In the beginning, the entire flash memory needed to be erased for In the beginning, the entire flash memory needed to be erased for reprogramming. reprogramming. •Modern flash memories Modern flash memories allow selective erasure of content in blocksallow selective erasure of content in blocks for for reprogramming while other blocks are protected. Important- and stable reprogramming while other blocks are protected. Important- and stable codes such as the boot-up code can be kept in protected blocks and the codes such as the boot-up code can be kept in protected blocks and the remaining blocks used for updates and other programs. remaining blocks used for updates and other programs.

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3. Special I/O Devices.3. Special I/O Devices.•In addition to traditional I/O devices such as keyboard, mouse, In addition to traditional I/O devices such as keyboard, mouse, monitor, printer, communication channel, etcmonitor, printer, communication channel, etc., RE systems often come ., RE systems often come with a variety of other I/O componentswith a variety of other I/O components such as such as – sensors, sensors, – touch screens, touch screens, – radars, radars, – GPS, GPS, – LED display panels. LED display panels.

•Particularly, Particularly, most RE systems are connected to many action- or most RE systems are connected to many action- or activation devicesactivation devices, usually mechanical devices, to perform intended , usually mechanical devices, to perform intended functions of the system. These devices are collectively called functions of the system. These devices are collectively called actuatorsactuators. .

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Special I/O Devices… Special I/O Devices… •These varieties of I/O interfaces make the software design of RE These varieties of I/O interfaces make the software design of RE systems highly complex. systems highly complex.

•>> Most embedded systems are >> Most embedded systems are not equipped withnot equipped with hard disks to keep hard disks to keep data safedata safe. . Flash memories replace hard disks in embedded devices. Flash memories replace hard disks in embedded devices. Note Note that for historical reasons these hybrid memories are referred to that for historical reasons these hybrid memories are referred to as ROM memories, although they are read-write random access as ROM memories, although they are read-write random access memories. memories. •>> RE systems may be divided into >> RE systems may be divided into purely cyclic, mostly cyclic, purely cyclic, mostly cyclic, asynchronous but predictable asynchronous but predictable and and asynchronous and unpredictableasynchronous and unpredictable, , based on the timing attributes of the tasks. based on the timing attributes of the tasks.

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3. Special I/O Devices… 3. Special I/O Devices… •Purely cyclic tasks Purely cyclic tasks are typically are typically real-time monitoring and control real-time monitoring and control tasks. tasks. •Mostly cyclic tasks Mostly cyclic tasks are cyclic and usually have are cyclic and usually have additional additional responsibility responsibility to attend to occasional external events. Most process to attend to occasional external events. Most process control systems belong to this category. control systems belong to this category. •Applications such as Applications such as multimedia, radar signal processing, and multimedia, radar signal processing, and surveillance although performing their tasks repetitively in a surveillance although performing their tasks repetitively in a predictable manner predictable manner are not periodicare not periodic. . •Most of the complex real-time systems such as Most of the complex real-time systems such as intelligent control intelligent control systems usually do not fall into any of the above three categories and, systems usually do not fall into any of the above three categories and, therefore, may be considered asynchronous and unpredictable therefore, may be considered asynchronous and unpredictable systems. systems.

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3. Special I/O Devices… 3. Special I/O Devices… •>> Most embedded systems are I/O intensive. The system must often >> Most embedded systems are I/O intensive. The system must often provide deterministic response for non-deterministic events. provide deterministic response for non-deterministic events. •Most RE systems use Most RE systems use – interrupt devices, interrupt devices, – real-time clocks, real-time clocks, – hardware timers, hardware timers, – and watchdog timers. and watchdog timers.

•Real-time clocks provide accurate record of elapsed time. Real-time clocks provide accurate record of elapsed time. •The software timers the operating systems provide are often not The software timers the operating systems provide are often not accurate. accurate.

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3. Special I/O Devices… 3. Special I/O Devices… •Hardware timers Hardware timers are now used to provide accurate time support for are now used to provide accurate time support for individual applications where software timers are not sufficient. individual applications where software timers are not sufficient. •Watchdog timers Watchdog timers are used as the last line of defence against program are used as the last line of defence against program malfunction. malfunction. •When timeout occursWhen timeout occurs, it generates a non-maskable interrupt , it generates a non-maskable interrupt for a for a recovery program.recovery program. The recovery program then takes suitable actions. The recovery program then takes suitable actions.

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4. Communication and Other Elements. 4. Communication and Other Elements. •As in traditional computing systems. RE systems also use collections As in traditional computing systems. RE systems also use collections of wires called buses for the CPU, the memory, and other devices for of wires called buses for the CPU, the memory, and other devices for communication. They communicate using suitably defined protocols. communication. They communicate using suitably defined protocols. •Two standard interfaces Two standard interfaces dominantly are used to connect external dominantly are used to connect external devices: devices: parallelparallel and and serialserial communication interfaces. communication interfaces. •The system communicates with the external world through these The system communicates with the external world through these interfaces. To control the communications, special devices such as the interfaces. To control the communications, special devices such as the direct memory access (DMA) controller direct memory access (DMA) controller (for direct communication (for direct communication between I/O devices and memory) and the between I/O devices and memory) and the interrupt controller interrupt controller (for (for coordinated communication between CPU and other devices) are coordinated communication between CPU and other devices) are used. used. •Other basic devices used in RE systems Other basic devices used in RE systems include analogue to digital include analogue to digital converters (converters (ADCsADCs) and digital to analogue converter () and digital to analogue converter (DACsDACs). ).

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5. Real-time Embedded Hardware Systems.5. Real-time Embedded Hardware Systems.•Using the elements discussed above, many types of RE systems can Using the elements discussed above, many types of RE systems can be designed. be designed. •Based on its use and sophistication, a programmable computing Based on its use and sophistication, a programmable computing device, built from these components, is called either a device, built from these components, is called either a microcontrollermicrocontroller or a or a microcomputermicrocomputer. . •At a higher levelAt a higher level, , microcontrollers are designed for special purpose microcontrollers are designed for special purpose computing and computing and microcomputers are designed for general purposemicrocomputers are designed for general purpose computing. computing. •Essentially, microcomputer means a computer with micro-processor Essentially, microcomputer means a computer with micro-processor for its CPU. At a lower level, a computer has a CPU, a memory, I/O for its CPU. At a lower level, a computer has a CPU, a memory, I/O devices, and busses for communication between the CPU, the devices, and busses for communication between the CPU, the memory, and the I/O devices. memory, and the I/O devices.

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5. Real-time Embedded Hardware Systems …5. Real-time Embedded Hardware Systems …•Many practical computers have other units such as timers, interrupt Many practical computers have other units such as timers, interrupt controllers, device controllers, etc. controllers, device controllers, etc. •The two popular architectures The two popular architectures used for transfer of data and used for transfer of data and instructions during execution instructions during execution are are Von Neumann Von Neumann (or Princeton) (or Princeton) architecture architecture andand Harvard architectureHarvard architecture. . •Von Neumann architecture uses Von Neumann architecture uses one bus for both data and one bus for both data and instructions,instructions, while while Harvard architecture uses Harvard architecture uses separate busesseparate buses. . •A RE system can use A RE system can use microcontrollersmicrocontrollers, , microcomputersmicrocomputers, or both. , or both. •As integrated technology advances, more units such as timers, I/O As integrated technology advances, more units such as timers, I/O ports and interfaces, device controllers, and memories, and memory ports and interfaces, device controllers, and memories, and memory management units (MMUs) management units (MMUs) are added into a single chip, are added into a single chip, creating creating single-chip microcontrollerssingle-chip microcontrollers, and , and single-chip microcomputers. single-chip microcomputers.

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5. Real-time Embedded Hardware Systems …5. Real-time Embedded Hardware Systems …•>> >> Von Neumann architecture Von Neumann architecture has simplicity and generality whereas has simplicity and generality whereas Harvard architecture offers high throughputHarvard architecture offers high throughput. . •Most DSPs use Harvard architecture and Most DSPs use Harvard architecture and most microprocessors use most microprocessors use von Neumann architecture.von Neumann architecture.•Sophisticated single-chip microcontrollers are called Sophisticated single-chip microcontrollers are called system-on-chipsystem-on-chip — an application-specific system design in a single chip. — an application-specific system design in a single chip. These designs These designs have both have both microprocessors and DSPs microprocessors and DSPs as their core elements. as their core elements. •With this preamble to hardware, we now introduce the operating With this preamble to hardware, we now introduce the operating systems for RE systems.systems for RE systems.

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SECTION B• Real Time and Embedded Operating Systems: Real Time and Embedded Operating Systems: – Introduction, Introduction, – Hardware Elements, Hardware Elements, – Structure Structure

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ORGORG

LJMP InitialisationLJMP Initialisation ; Bypass code for handling interrupts; Bypass code for handling interrupts; Interrupts Section; Interrupts SectionORGORG 0003H0003HLJMPLJMP ISR_for_INT0ISR_for_INT0

ORGORG 0013H0013HLJMPLJMP ISR_for_INT1ISR_for_INT1; ….; ….

ORGORG 0030H0030H ; Initialisation section; Initialisation sectionInitialisation:Initialisation:

;…. Initialise various ports and registers, setup interrupts etc;…. Initialise various ports and registers, setup interrupts etcMainLoop:MainLoop:

; Code for sensing periodic inputs, random events may also be sensed in loop; Code for sensing periodic inputs, random events may also be sensed in loop; Conditional jumps; Conditional jumpsAcallAcall Action1Action1 ; Calling other subroutines based on sensed input; Calling other subroutines based on sensed inputSJMP MainLoopSJMP MainLoop

ISR_for_INT0:ISR_for_INT0: ; Routines for servicing interrupts.; Routines for servicing interrupts.SETBSETB P2.1P2.1RETIRETI

Action1:Action1: ; Other actions; Other actionsSetBSetB P2.2P2.2 ;.. Code here;.. Code hereRETRET

ENDEND140

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ORGORG








ENDEND

SectionsSections1.1.ORGIN (Begin) and END for the complete operating system. Every ORGIN (Begin) and END for the complete operating system. Every line of code will be inside this boundary unless routines from line of code will be inside this boundary unless routines from secondary storage are to be called.secondary storage are to be called.2.2.Interrupts Section:Interrupts Section:

a.a. Defines origin (address) for each hardware interrupt as per Defines origin (address) for each hardware interrupt as per Interrupt Vector Table.Interrupt Vector Table.

b.b. Includes Jump to respective Interrupt Service Routines (ISRs). Includes Jump to respective Interrupt Service Routines (ISRs). 3.3.Initialisation SectionInitialisation Section.. This part is outside operating system This part is outside operating system mainloop. Following initialisations are done here:-mainloop. Following initialisations are done here:-

a.a. Initialise Input ports or pins for sensors (temperature, pressure, Initialise Input ports or pins for sensors (temperature, pressure, flow rate, voltage, current etc), keypads (for user input) and flow rate, voltage, current etc), keypads (for user input) and other inputs.other inputs.

b.b. Initialise Output ports or pins for LCD, LED or other output Initialise Output ports or pins for LCD, LED or other output devices.devices.

c.c. Initialise other variables and data structures.Initialise other variables and data structures.d.d. Initialise communication parametersInitialise communication parameters

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ORGORG








ENDEND

SectionsSections4. 4. Main Loop Section.Main Loop Section.

a.a. Remain in an endless loop.Remain in an endless loop.b.b. Hardware responds to interrupts while processor is waiting for Hardware responds to interrupts while processor is waiting for

other inputs. Code for other inputs is here.other inputs. Code for other inputs is here.c.c. Depending on the input, the program calls corresponding Depending on the input, the program calls corresponding

action routines.action routines.5.5.Interrupt Service RoutinesInterrupt Service Routines.. There is a separate routine for servicing There is a separate routine for servicing each interrupt.each interrupt.6.6.Other Service Routines.Other Service Routines. This section contains all other This section contains all other action subroutines.action subroutines.7.7.User Input RoutinesUser Input Routines.. These routines contain code for action on These routines contain code for action on user inputs. They may be called by ISRs or from OS mainloop.user inputs. They may be called by ISRs or from OS mainloop.

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SYLLABUSSYLLABUSReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Writing Real Time and Embedded Operating System for 8051 Microcontroller.Microcontroller.

a.a. Write a simple operating system for 8051 microcontroller which is required Write a simple operating system for 8051 microcontroller which is required to to monitor and control monitor and control water level in a tankwater level in a tank. If the water level falls below a . If the water level falls below a critical level, it should start the water pump automatically. If the level rises critical level, it should start the water pump automatically. If the level rises above the top level, it should stop the motor. above the top level, it should stop the motor.

b.b. GuidelinesGuidelines..i.i. There would be two sensors. One for sensing lowest level and the other for sensing There would be two sensors. One for sensing lowest level and the other for sensing

highest level.highest level.ii.ii. The sensors would be connected to two pins of a port. These pins/port would be The sensors would be connected to two pins of a port. These pins/port would be

configured as input port.configured as input port.iii.iii. These sensor pins would be checked in a loop for their status.These sensor pins would be checked in a loop for their status.iv.iv. When the water level falls below the lowest level, another port pin, configured as When the water level falls below the lowest level, another port pin, configured as

output pin, would be set to 1 (Say P2.1). This pin would be connected to an electric output pin, would be set to 1 (Say P2.1). This pin would be connected to an electric relay. If both the sensors are off, give instruction SetB P2.1. which would start the relay. If both the sensors are off, give instruction SetB P2.1. which would start the water pump.water pump.

v.v. When the water level increases above upper level, the pump is stopped by another When the water level increases above upper level, the pump is stopped by another instruction: Clr P2.1instruction: Clr P2.1 145

SYLLABUSSYLLABUSReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Writing Real Time and Embedded Operating System for 8051 Microcontroller…Microcontroller…

146

SYLLABUSSYLLABUSReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Writing Real Time and Embedded Operating System for 8051 Microcontroller…Microcontroller…

ORG 00ORG 00; Configure P1.1 and P1.2 as input pins; Configure P1.1 and P1.2 as input pinsSetBSetB P1.1P1.1SetBSetB P1.2P1.2; Now they have high voltage. When water crosses these levels,; Now they have high voltage. When water crosses these levels,; the Sensors should send low voltage (0V) on these pins.; the Sensors should send low voltage (0V) on these pins.


; it also stops the motor; it also stops the motorMainloop:Mainloop:

; Check Low level; Check Low levelCheckLowLevel:CheckLowLevel:

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SYLLABUSSYLLABUSReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)1.1.Writing Real Time and Embedded Operating System for 8051 Microcontroller…Writing Real Time and Embedded Operating System for 8051 Microcontroller…MainloopMainloop::

; Check Low level; Check Low level CheckLowLevel:CheckLowLevel:

JNBJNB P1.1, P1.1, CheckHighLevelCheckHighLevel ; P1.1 = 0, Water is above empty level; P1.1 = 0, Water is above empty levelSetBSetB P2.1P2.1 ; Tank is Empty , Start Water Pump; Tank is Empty , Start Water Pump

SJMPSJMP CheckAgainCheckAgain ; Bypass High level checks.; Bypass High level checks.; Let the pump keep running.; Let the pump keep running.

CheckHighLevel:CheckHighLevel: ; If water is above low level, check upper level; If water is above low level, check upper levelJB JB P1.2, CheckAgainP1.2, CheckAgain ; Water is below Top level; Water is below Top levelClrClr P2.1P2.1 ; Tank is Full, Stop Water Pump; Tank is Full, Stop Water Pump

CheckAagain:CheckAagain:SJmp MainloopSJmp Mainloop

ENDEND

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ConditionCondition High Level Sensor High Level Sensor PinPin

Low Level Sensor Low Level Sensor PinPin

Motor Relay PinMotor Relay Pin Motor StatusMotor Status

1.1. Initialisation outside Initialisation outside Mainloop: Assume Mainloop: Assume initially Tank is Emptyinitially Tank is Empty

Set it to High (1) : Set it to High (1) : InactiveInactive

Set it to High (1): Set it to High (1): InactiveInactive

Set it to Low (0)Set it to Low (0)

Initially Stop Initially Stop MotorMotor

2 2 Enter MainloopEnter Mainloop Sensor indicates Sensor indicates below top levelbelow top level

Sensor indicates Sensor indicates below low levelbelow low level



3 3 Now Motor is RunningNow Motor is Running High (1) : InactiveHigh (1) : Inactive High (1): InactiveHigh (1): Inactive Remains High (1)Remains High (1) Motor keeps Motor keeps runningrunning

4 4 After sometime Low After sometime Low level sensor gets level sensor gets activatedactivated


Becomes Low (0):Becomes Low (0):Active; Water Active; Water rises above Lower rises above Lower levellevel

Remains High (1)Remains High (1) Motor keeps Motor keeps runningrunning

5 5 Water crosses Top Water crosses Top LevelLevel

Becomes Low (0): Becomes Low (0): ActiveActive


Becomes Low (0)Becomes Low (0) Motor StopsMotor Stops

6 6 Water level falls with Water level falls with usage. Falls below usage. Falls below high levelhigh level

Becomes High Becomes High (1): Inactive(1): Inactive


Remains Low (0)Remains Low (0) Motor Remains Motor Remains OffOff

7 7 Water Falls further Water Falls further and goes below low and goes below low levellevel


Becomes High (1): Becomes High (1): InactiveInactive



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SYLLABUSSYLLABUSReal Time and Embedded Operating System (RTES or ER)Real Time and Embedded Operating System (RTES or ER)

•Write an Write an interrupt driven operating system interrupt driven operating system to monitor and control to monitor and control water level in a tank. Water level sensors would be wired on external water level in a tank. Water level sensors would be wired on external interrupt pins (P3.2 and P3.3).interrupt pins (P3.2 and P3.3). 150

INTERRUPT DRIVEN OS FOR WATER TANKINTERRUPT DRIVEN OS FOR WATER TANKORG 00ORG 00LJMPLJMP InitialiseInitialise ; Bypass Interrupt Vector Table; Bypass Interrupt Vector Table

; Vector Address for INT0 is 0003H; Vector Address for INT0 is 0003HORGORG 0003H0003HLJMPLJMP ISR_for_INT0ISR_for_INT0 ; ISR: Abbreviation for Interrupt Service Routine; ISR: Abbreviation for Interrupt Service Routine

; Vector Address for INT1 is 0013H; Vector Address for INT1 is 0013HORGORG 0013H0013HLJMPLJMP ISR_for_INT1ISR_for_INT1

ORG 0030HORG 0030H

InitialiseInitialise::; Configure P3.2 and P3.3 as input pins; Configure P3.2 and P3.3 as input pinsSetBSetB P3.2P3.2 ; Interrupt pin; Interrupt pinSetBSetB P3.3P3.3 ; Normal Pin; Normal Pin; Now they have high voltage. When water crosses these levels,; Now they have high voltage. When water crosses these levels,; the Sensors should send low voltage (0V) on these pins.; the Sensors should send low voltage (0V) on these pins.


; it also stops the motor; it also stops the motor

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INTERRUPT DRIVEN OS FOR WATER TANK…INTERRUPT DRIVEN OS FOR WATER TANK…; Setup Interrupts; Setup Interrupts; preprocess a few bits of three SFR’s namely TCON, IE and IP; preprocess a few bits of three SFR’s namely TCON, IE and IP; 1. TCON Register is to be configured for enabling type of signal. ; 1. TCON Register is to be configured for enabling type of signal. ; Let it remain with default values.; Let it remain with default values.; 2. ; 2. IEIE Register: Configure Register: Configure Interrupt Enable Interrupt Enable Register. Register. ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1 ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1

;MOV IE, #10000001B ;MOV IE, #10000001B ;Enable External INT0;Enable External INT0;MOV IE, #10000100B ;MOV IE, #10000100B ;Enable External INT1;Enable External INT1MOV IE, #10000101B MOV IE, #10000101B ;Enable External INT0 and INT1;Enable External INT0 and INT1

; 3. IP Register: Special Function Register IP is to be configured ; 3. IP Register: Special Function Register IP is to be configured ; for changing priority of interrupts.; for changing priority of interrupts.;; Let it have default values Let it have default values

Mainloop:Mainloop:

; Microcontroller keeps running in this loop. ; Microcontroller keeps running in this loop. ; When an interrupt is received, its subroutine would be run.; When an interrupt is received, its subroutine would be run.NOPNOP

SJmp SJmp MainloopMainloop 152

INTERRUPT DRIVEN OS FOR WATER TANK…INTERRUPT DRIVEN OS FOR WATER TANK…MainloopMainloop::

; Microcontroller keeps running in this loop. ; Microcontroller keeps running in this loop. ; When an interrupt is received, its subroutine would be run.; When an interrupt is received, its subroutine would be run.NOPNOPSJmp MainloopSJmp Mainloop

ISR_for_INT0:ISR_for_INT0:

JNB P3.3, StopPump ; Interrupt Pin P3.3 indicates water is already above topJNB P3.3, StopPump ; Interrupt Pin P3.3 indicates water is already above top

; Otherwise, water is lower than lowest level. Therefore Motor is to be started.; Otherwise, water is lower than lowest level. Therefore Motor is to be started. ; Sensor and circuit should send a low voltage on P3.2; Sensor and circuit should send a low voltage on P3.2SetBSetB P2.1P2.1SJMPSJMP DoneDone

StopPump:StopPump:CLRCLR P2.1P2.1 ; Stop Pump; Stop Pump

Done:Done:RETIRETI

ISR_for_INT1:ISR_for_INT1:; Water is higher than lowest level. Therefore Motor is to be stopped.; Water is higher than lowest level. Therefore Motor is to be stopped.; Sensor and circuit should send a low voltage on P3.3; Sensor and circuit should send a low voltage on P3.3ClrClr P2.1P2.1RETIRETI

ENDEND 153

ADD TIMER INTERRUPTADD TIMER INTERRUPT

INTERRUPT DRIVEN OS FOR WATER TANKINTERRUPT DRIVEN OS FOR WATER TANKORG 00ORG 00LJMPLJMP InitialiseInitialise

; Vector Address for INT0; Vector Address for INT0ORGORG 0003H0003HLJMPLJMP ISR_for_INT0ISR_for_INT0 ; ISR: Abbreviation for Interrupt Service Routine; ISR: Abbreviation for Interrupt Service Routine

; Vector Address for Timer0; Vector Address for Timer0ORGORG 000BH000BHLJMPLJMP ISR_for_Timer0ISR_for_Timer0 ; ISR: Abbreviation for Interrupt Service Routine; ISR: Abbreviation for Interrupt Service Routine


ORG 0030HORG 0030H

InitialiseInitialise::; Configure P3.2 and P2.0 as input pins; Configure P3.2 and P2.0 as input pinsSetBSetB P3.2P3.2 ; Interrupt pin; Interrupt pinSetBSetB P3.3P3.3 ; Normal Pin; Normal Pin; Now they have high voltage. When water crosses these levels,; Now they have high voltage. When water crosses these levels,; the Sensors should send low voltage (0V) on these pins.; the Sensors should send low voltage (0V) on these pins.


; it also stops the motor; it also stops the motor

INTERRUPT DRIVEN OS FOR WATER TANK…INTERRUPT DRIVEN OS FOR WATER TANK…; Setup Interrupts; Setup Interrupts; preprocess a few bits of three SFR’s namely TCON, IE and IP; preprocess a few bits of three SFR’s namely TCON, IE and IP; 1. TCON Register is to be configured for enabling type of signal. ; 1. TCON Register is to be configured for enabling type of signal. ; Let it remain with default values.; Let it remain with default values.; 2. IE Register: Configure Interrupt Enable Register. ; 2. IE Register: Configure Interrupt Enable Register. ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 0 for Enabling External Interrupt 0 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 2 for Enabling External Interrupt 1 or Clear it to disable ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1 ; Set Bit 7 to enable interrupts. Interrupts would be serviced only if Bit 7 = 1

;MOV IE, #10000001B ;MOV IE, #10000001B ;Enable External INT0;Enable External INT0;MOV IE, #10000100B ;MOV IE, #10000100B ;Enable External INT1;Enable External INT1;MOV IE, #10000101B ;MOV IE, #10000101B ;Enable External INT0 and INT1;Enable External INT0 and INT1MOV IE,#10000111B MOV IE,#10000111B ;Enable INT0, Timer0 and INT1;Enable INT0, Timer0 and INT1

; 3. IP Register: Special Function Register IP is to be configured ; 3. IP Register: Special Function Register IP is to be configured ; for changing priority of interrupts.; for changing priority of interrupts.;; Let it have default values Let it have default values

Mainloop:Mainloop:


SJmp SJmp MainloopMainloop

INTERRUPT DRIVEN OS FOR WATER TANK…INTERRUPT DRIVEN OS FOR WATER TANK… Mainloop:Mainloop:


;Set Timer0 parameters and Start Timer;Set Timer0 parameters and Start TimerMOV TMOD, #01HMOV TMOD, #01H ; Set TMOD for Mode1: 16 Bit Timer Mode; Set TMOD for Mode1: 16 Bit Timer ModeMOV TH0, #0FFHMOV TH0, #0FFH ; Set values in Timer0 Register High byte ; Set values in Timer0 Register High byte MOV TL0, #0F9HMOV TL0, #0F9H ; Set values in Timer0 Register Low byte; Set values in Timer0 Register Low byteSETB TR0SETB TR0 ; Start Timer 0 ->FFF9->FFFA->FFFB…->FFFF; Start Timer 0 ->FFF9->FFFA->FFFB…->FFFF

; Assume Task further is a long job.; Assume Task further is a long job.; Timer will keep running. ; Timer will keep running. ; After Timer 0 overflow, its interrupt would get activated.; After Timer 0 overflow, its interrupt would get activated.NOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOP

SJmp SJmp MainloopMainloop

INTERRUPT DRIVEN OS FOR WATER TANK…INTERRUPT DRIVEN OS FOR WATER TANK…MainloopMainloop::

; Microcontroller keeps running in this loop. ; Microcontroller keeps running in this loop. ; When an interrupt is received, its subroutine would be run.; When an interrupt is received, its subroutine would be run.NOPNOPSJmp SJmp MainloopMainloop


JNB P3.3, StopPumpJNB P3.3, StopPump; Water is lower than lowest level. Therefore Motor is to be started.; Water is lower than lowest level. Therefore Motor is to be started.SetBSetB P2.1P2.1 ; Sensor and circuit should send a low voltage on P3.1; Sensor and circuit should send a low voltage on P3.1SJMPSJMP DoneDone

StopPump:StopPump:CLRCLR P2.1P2.1 ; Stop Pump; Stop Pump

Done:Done:RETIRETI


; Water is higher than lowest level. Therefore Motor is to be stopped.; Water is higher than lowest level. Therefore Motor is to be stopped.ClrClr P2.1P2.1 ; Sensor and circuit should send a low voltage on P3.2; Sensor and circuit should send a low voltage on P3.2RETIRETI

INTERRUPT DRIVEN OS FOR WATER TANK…INTERRUPT DRIVEN OS FOR WATER TANK… ISR_for_Timer0:ISR_for_Timer0:

; Stop Timer 0, Clear its Flag; Stop Timer 0, Clear its FlagClr TR0Clr TR0Clr TF0Clr TF0

; Action: ... Create a low to high pulse on P2.0; Action: ... Create a low to high pulse on P2.0CLR P2.0CLR P2.0NOPNOPSetB P2.0SetB P2.0

RETIRETI

ENDEND

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Operating Systems for RE SystemsOperating Systems for RE Systems•A general purpose computer A general purpose computer has a relatively simple but powerful has a relatively simple but powerful architecture which interacts with the outside world through a small architecture which interacts with the outside world through a small set of well-defined I/O interfaces. set of well-defined I/O interfaces. •Its hardware resources are well known Its hardware resources are well known and and outside interactions are outside interactions are not difficult to controlnot difficult to control. . •Operating systems for such general purpose computers Operating systems for such general purpose computers are are widespread and relatively well understood. widespread and relatively well understood. •Since RE systems are special purpose systems and diverseSince RE systems are special purpose systems and diverse, , their their software including operating systems is often tailor-madesoftware including operating systems is often tailor-made, less , less standardized, and, therefore, not all that well understood.standardized, and, therefore, not all that well understood.

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Operating Systems for RE Systems…Operating Systems for RE Systems…•Certainly, titles such as real-time operating system and embedded Certainly, titles such as real-time operating system and embedded operating system are often used in the computing world. operating system are often used in the computing world. •However, However, due to the diverse nature of RE systemsdue to the diverse nature of RE systems, , there is no such there is no such thing called a real-time operating system or embedded operating thing called a real-time operating system or embedded operating system defined with all functionalitiessystem defined with all functionalities. . •However, However, some of the issues and functionalities of real-time operating some of the issues and functionalities of real-time operating systems are studied well, usually in isolationsystems are studied well, usually in isolation, often under the title of , often under the title of real-time and embedded operating systems. real-time and embedded operating systems. •In recent times, the subject has gained more popularity In recent times, the subject has gained more popularity and and many many operating systems are released as operating systems are released as eithereither real-time real-time oror embedded embedded operating systems. operating systems. •Some of these systems are direct modifications of traditional Some of these systems are direct modifications of traditional operating systemsoperating systems and and others borrow key ideas others borrow key ideas from traditional from traditional operating systems.operating systems. 162


Operating Systems for RE Systems…Operating Systems for RE Systems…•EssentiallyEssentially, , most RE systems are I/O dominated systems most RE systems are I/O dominated systems and are and are often often part of physical systemspart of physical systems, and physical systems are intrinsically , and physical systems are intrinsically concurrent and temporal (concurrent and temporal (temporal: relating to or limited by timetemporal: relating to or limited by time). ). •In general-purpose systems, I/Os are usually dealt with well-defined In general-purpose systems, I/Os are usually dealt with well-defined interrupt handling. interrupt handling. •UsuallyUsually, I/O interfacing in RE systems involves both , I/O interfacing in RE systems involves both interrupt-interrupt- and and exceptionexception handling. handling. •The exceptions The exceptions introduced by the environment through I/O are hard to introduced by the environment through I/O are hard to visualize at the design stage visualize at the design stage but anyhow required to be addressed but anyhow required to be addressed properly. properly. •In the context of general purpose operating systemsIn the context of general purpose operating systems, exception , exception handling usually deals with detecting a set of well-defined internal handling usually deals with detecting a set of well-defined internal problems such as arithmetic and stack overflows, memory and array problems such as arithmetic and stack overflows, memory and array bound violations. etc. bound violations. etc. 163


Operating Systems for RE Systems…Operating Systems for RE Systems…•Operating systems designed for RE systemsOperating systems designed for RE systems, in addition, must deal , in addition, must deal with with external failures external failures as well as their as well as their induced internal failuresinduced internal failures. . •Even improper handling of internal failures may lead to external Even improper handling of internal failures may lead to external failures with serious consequences. failures with serious consequences. •Services provided by traditional non-real-time operating systems Services provided by traditional non-real-time operating systems have many similarities with the services provided by real-time and have many similarities with the services provided by real-time and embedded operating systems (REOS). embedded operating systems (REOS). •The fundamental difference The fundamental difference is the need for “deterministic” timing is the need for “deterministic” timing behaviour in the case of real-time computing. behaviour in the case of real-time computing. •Deterministic timing implies Deterministic timing implies that operating systems should respond that operating systems should respond to requests within a known- and expected amount of time. to requests within a known- and expected amount of time. •Non-deterministic behaviour is common in traditional operating Non-deterministic behaviour is common in traditional operating systems. systems.

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Operating Systems for RE Systems…Operating Systems for RE Systems…•Overall, it is hard to come up with a comprehensive answer Overall, it is hard to come up with a comprehensive answer to the to the question of what is REOS. question of what is REOS. •Perhaps, the simplest answer would be "an operating system Perhaps, the simplest answer would be "an operating system designed for RE systems".designed for RE systems".•>> The most important activities in consumer electronics are: >> The most important activities in consumer electronics are:

(1) control driven — implemented by periodic tasks; (1) control driven — implemented by periodic tasks; (2) data driven — audio, video, graphics applications; and (2) data driven — audio, video, graphics applications; and (3) Interactive - asynchronous event-based applications. (3) Interactive - asynchronous event-based applications.

•>> >> An REOS is expected to support An REOS is expected to support priorities, interrupts, timers, priorities, interrupts, timers, concurrent executions, intertask communication, and predictable concurrent executions, intertask communication, and predictable synchronization, and mechanisms to assure bounded latencies, it must synchronization, and mechanisms to assure bounded latencies, it must be correct, reliable, and must assure safety. be correct, reliable, and must assure safety.

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Operating Systems for RE Systems…Operating Systems for RE Systems…•>> >> RE systems may be divided into RE systems may be divided into

– purely cyclic, purely cyclic, – mostly cyclic,mostly cyclic,– asynchronous but predictable, asynchronous but predictable, – and asynchronous and unpredictable, based on the timing attributes of the and asynchronous and unpredictable, based on the timing attributes of the

tasks. tasks. •Purely cyclic tasks Purely cyclic tasks are typically real-time monitoring and control tasks. are typically real-time monitoring and control tasks. •Mostly cyclic tasks Mostly cyclic tasks are cyclic and usually have additional responsibility to attend to are cyclic and usually have additional responsibility to attend to occasional external events. Most process control systems belong to this category. occasional external events. Most process control systems belong to this category. Applications such as Applications such as multimedia, radar signal processing, and surveillance although multimedia, radar signal processing, and surveillance although performing their tasks _ repetitively in a predictable manner are not periodic. performing their tasks _ repetitively in a predictable manner are not periodic. Most Most of the complex real- time systems of the complex real- time systems such as intelligent control systems usually do not such as intelligent control systems usually do not fall into any of the above three categories and, therefore, fall into any of the above three categories and, therefore, may be considered may be considered asynchronous and unpredictable systems. asynchronous and unpredictable systems.

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Operating Systems for RE Systems…Operating Systems for RE Systems…•However, it often refers to a collection of components or a design However, it often refers to a collection of components or a design approach for real-time software systems. approach for real-time software systems. •Providing operating system support to a wide range of RE systems is a Providing operating system support to a wide range of RE systems is a complex task. complex task. •RE systems use RE systems use home-grown simple control software instead of home-grown simple control software instead of general purpose operating systems such as UNIX, Linux, and Windows general purpose operating systems such as UNIX, Linux, and Windows with added real-time supports. with added real-time supports. •In relation to other types of operating systems such as batch- and In relation to other types of operating systems such as batch- and interactive operating systems, based on the speed of response as the interactive operating systems, based on the speed of response as the criterioncriterion, RE systems may be considered as systems where the , RE systems may be considered as systems where the response is expected within a short but "definite" or “bounded” time. response is expected within a short but "definite" or “bounded” time.

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Operating Systems for RE Systems…Operating Systems for RE Systems…•In addition, these systems must facilitate In addition, these systems must facilitate ways to handle unexpected ways to handle unexpected errors, missed deadlines, inevitable failures, and may operate under errors, missed deadlines, inevitable failures, and may operate under resource constraints. resource constraints. •Many commercial real-time operating systems are available to run on Many commercial real-time operating systems are available to run on common processors and have sizable user base. common processors and have sizable user base. •They include They include

– Windows CE (Embedded Compact), Windows CE (Embedded Compact), – LynxOS(The LynxOS RTOS is a Unix-like real-time operating system from LynxOS(The LynxOS RTOS is a Unix-like real-time operating system from

LynuxWorks), LynuxWorks), – pSOS (Portable Software On Silicon is a real time operating system (RTOS), pSOS (Portable Software On Silicon is a real time operating system (RTOS),

created in about 1982 by Alfred Chao), created in about 1982 by Alfred Chao), – Jbed (Jbed, a small, fast Java Virtual Machine for embedded real-time Jbed (Jbed, a small, fast Java Virtual Machine for embedded real-time

systems, includes a complete real-time operating system.), systems, includes a complete real-time operating system.),

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Operating Systems for RE Systems…Operating Systems for RE Systems…•They include They include

– ……– QNX (QNX is a commercial Unix-like real-time operating system, aimed QNX (QNX is a commercial Unix-like real-time operating system, aimed

primarily at the embedded systems market.), primarily at the embedded systems market.), – VRTX (Versatile Real-Time Executive (VRTX) is a real-time operating system VRTX (Versatile Real-Time Executive (VRTX) is a real-time operating system

developed and marketed by the company Mentor Graphics. VRTX is suitable developed and marketed by the company Mentor Graphics. VRTX is suitable for both traditional board-based embedded systems and SoC (System on a for both traditional board-based embedded systems and SoC (System on a Chip) architectures.), Chip) architectures.),

– Symbian (Symbian OS is an operating system for mobile phones primarily Symbian (Symbian OS is an operating system for mobile phones primarily used on Nokia advanced or data enabled smart phones. Symbian OS runs used on Nokia advanced or data enabled smart phones. Symbian OS runs exclusively on ARM processors), exclusively on ARM processors),

– and VxWorks (VxWorks is a real-time operating system developed as and VxWorks (VxWorks is a real-time operating system developed as proprietary software by Wind River Systems of Alameda, California, USA. proprietary software by Wind River Systems of Alameda, California, USA. First released in 1987, VxWorks is designed for use in embedded systems.). First released in 1987, VxWorks is designed for use in embedded systems.).

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Operating Systems for RE Systems…Operating Systems for RE Systems…•They all have many similarities and are generally conform to real-They all have many similarities and are generally conform to real-time POSIX API standard. time POSIX API standard. •POSIX, an acronym for "Portable Operating System Interface", is a family of POSIX, an acronym for "Portable Operating System Interface", is a family of standards specified by the IEEE for maintaining compatibility between operating standards specified by the IEEE for maintaining compatibility between operating systems. POSIX defines the application programming interface (API), along with systems. POSIX defines the application programming interface (API), along with command line shells and utility interfaces, for software compatibility with variants command line shells and utility interfaces, for software compatibility with variants of Unix and other operating systems.of Unix and other operating systems.

•Some design philosophies areSome design philosophies are: : – keep it simple and effective, keep it simple and effective, – provide effective interrupt handling, provide effective interrupt handling, – offer efficient scheduling and memory management, offer efficient scheduling and memory management, – and provide mechanisms to solve task coordination issues. and provide mechanisms to solve task coordination issues.

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Operating Systems for RE Systems…Operating Systems for RE Systems…•The approach of “The approach of “one-size-fit-allone-size-fit-all" " for RE systems cannot be the best for RE systems cannot be the best one for obvious reasons. one for obvious reasons. •Next, we look at some Next, we look at some basic structures of REOSbasic structures of REOS and then some of the and then some of the main components. main components.

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The Structure of REOS The Structure of REOS •From the discussion so far, it is easy to infer that most REOSs are From the discussion so far, it is easy to infer that most REOSs are interrupt-driven. interrupt-driven. •Timers and peripherals Timers and peripherals (such as I/O, sensors, etc) (such as I/O, sensors, etc) trigger interrupts.trigger interrupts. •Based on the source, Based on the source, interrupts play two crucial roles. interrupts play two crucial roles. – In the case of timer interruptsIn the case of timer interrupts, they mark the specific instants of , they mark the specific instants of

initiation and completion of certain time-critical tasks. initiation and completion of certain time-critical tasks. – Peripheral interrupts Peripheral interrupts inform the CPU of some asynchronous inform the CPU of some asynchronous

events, which usually require immediate attention for the events, which usually require immediate attention for the system to function properly. system to function properly.

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The Structure of REOS …The Structure of REOS …•RE system's functionalities are traditionally abstracted into tasks, and RE system's functionalities are traditionally abstracted into tasks, and these tasks undergo these tasks undergo various states various states such as such as ready (activated), ready (activated), suspended; waitingsuspended; waiting, etc. , etc. •These states are mostly managed by hardware interrupts. These states are mostly managed by hardware interrupts. •Again, Again, RE systems vary from RE systems vary from a simple controller to a complex a simple controller to a complex networked control system. networked control system. •Simple controller activities can be abstracted as tasks and then Simple controller activities can be abstracted as tasks and then managed through an interrupt handler, but not the complex managed through an interrupt handler, but not the complex networked control systems. networked control systems. •Here we review some Here we review some popular modelspopular models used to build real-time used to build real-time software. software.

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• Interrupt Driven, Interrupt Driven,

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1. A Basic Interrupt-driven Task Model.1. A Basic Interrupt-driven Task Model.•This is the simplest model This is the simplest model and often used to design simple real-time and often used to design simple real-time software. software. •This model considers each system activity as a task This model considers each system activity as a task and and the code for the code for each task is written as an interrupt routineeach task is written as an interrupt routine, also known as interrupt , also known as interrupt service routine (service routine (ISRISR). ). •The interfaces The interfaces to boards and panels to boards and panels are written as interfacing are written as interfacing routinesroutines that can be used as ISRsthat can be used as ISRs. . •Then a simple control routine is used to coordinate their activities. Then a simple control routine is used to coordinate their activities. •Hardware timers are used to generate Hardware timers are used to generate necessary interrupts during necessary interrupts during execution. execution.

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1. A Basic Interrupt-driven Task Model… 1. A Basic Interrupt-driven Task Model… •When an interrupt occurs, it is handled by the following steps. When an interrupt occurs, it is handled by the following steps.

1. The context of the current task is saved. 1. The context of the current task is saved. 2. The interrupt is identified and its associated ISR is invoked. 2. The interrupt is identified and its associated ISR is invoked. 3. The saved context is restored and the execution of the interrupted task is 3. The saved context is restored and the execution of the interrupted task is resumed. resumed.

•ln some systemsln some systems, lSRs are not preemptible, and , lSRs are not preemptible, and in others in others lSRs can be lSRs can be preempted by higher priority interrupts. preempted by higher priority interrupts. •If several interrupts are pendingIf several interrupts are pending, then they are served in the order , then they are served in the order according of their priorities. according of their priorities. •The key aspect The key aspect of this model is that the tasks (lSRs) are designed of this model is that the tasks (lSRs) are designed carefully for speed and predictability. carefully for speed and predictability. •The related approach of minimal operating system is called The related approach of minimal operating system is called exokernel-basedexokernel-based design design. .

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1. A Basic Interrupt-driven Task Model …1. A Basic Interrupt-driven Task Model …•Exokernel Exokernel is an operating system kernel developed by the is an operating system kernel developed by the MIT MIT Parallel and Distributed Operating Systems groupParallel and Distributed Operating Systems group, and also a class of , and also a class of similar operating systems.similar operating systems.•The Massachusetts Institute of Technology (MIT) is a The Massachusetts Institute of Technology (MIT) is a private research university in research university in Cambridge, Massachusetts known traditionally for research and education in the physical Cambridge, Massachusetts known traditionally for research and education in the physical sciences and engineering, and more recently in biology, economics, linguistics, and sciences and engineering, and more recently in biology, economics, linguistics, and management as well.management as well.

•The purpose is that the operating system should provide only very The purpose is that the operating system should provide only very basic support such as basic support such as

– allocating resources to tasks, allocating resources to tasks, – protecting tasks from each other, protecting tasks from each other, – revoking access to resources, etc., revoking access to resources, etc., ((Revoke: To void or annul by recalling, Revoke: To void or annul by recalling,

withdrawing, or reversingwithdrawing, or reversing))

leaving the rest of the higher-level policies to the application developers. leaving the rest of the higher-level policies to the application developers.

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http://en.wikipedia.org/wiki/Private_university


1. A Basic Interrupt-driven Task Model …1. A Basic Interrupt-driven Task Model …•Above all, Above all, the operating system the operating system should not provide should not provide any service any service abstractions by hiding all hardware resources from applications. abstractions by hiding all hardware resources from applications. •This approach advocates This approach advocates

– application-level management of application-level management of physical resources, physical resources, – and enables users to have custom abstractions where they can choose to and enables users to have custom abstractions where they can choose to

implement the level of abstraction they want. implement the level of abstraction they want.

•The advantage is superior performanceThe advantage is superior performance, , but it is hard to write but it is hard to write applications on exokernel-based systemsapplications on exokernel-based systems. .

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180


• Interrupt Driven, Interrupt Driven, • Nanokernel, Nanokernel,

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2. The Nanokernel-based Model. 2. The Nanokernel-based Model. •In the previous modelIn the previous model, , the entire code the entire code involved in time- and interrupt involved in time- and interrupt management management must be developed from scratchmust be developed from scratch. . •lt is a tedious job developing large applications. lt is a tedious job developing large applications. •The nanokernel approach is considered the The nanokernel approach is considered the first step first step towards towards providing software support for real-time application development and providing software support for real-time application development and execution. execution. •The term nanokernel The term nanokernel is not standardizedis not standardized. . •However, However, the the objectiveobjective is is to classify the tasks as to classify the tasks as

– regular regular and and – time-critical. time-critical.

•Then, the Then, the time-critical tasks are handled through the interrupt-driven time-critical tasks are handled through the interrupt-driven technique as discussed above technique as discussed above and the and the regular tasks are handled regular tasks are handled through the kernel. through the kernel.

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NANOKERNEL BASICSNANOKERNEL BASICSMainloopMainloop::

; Assume P1 is configured as input port. It can receive 8 ; Assume P1 is configured as input port. It can receive 8 inputs.inputs.

Input0:Input0: ; If user presses a key, the corresponding pin drops to 0 volt.; If user presses a key, the corresponding pin drops to 0 volt.JBJB P1.0, Input1P1.0, Input1 ; High voltage on a pin means no input, 0 means it has ; High voltage on a pin means no input, 0 means it has

input.input.

ACallACall Action0Action0SJMPSJMP NextRound NextRound

Input1:Input1: JBJB P1.1, Input2P1.1, Input2ACallACall Action1Action1

SJMPSJMP NextRound NextRound Input2:Input2:JBJB P1.2, NextRoundP1.2, NextRoundACallACall Action2Action2SJMPSJMP NextRound NextRound

NextRound:NextRound:SJmp MainloopSJmp Mainloop

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NANOKERNEL BASICSNANOKERNEL BASICSMainloopMainloop:: ; Assume P2 is configured as input port. It can receive 8 inputs.; Assume P2 is configured as input port. It can receive 8 inputs.

Input0:Input0: ; If user presses a key, the corresponding pin drops to 0 volt.; If user presses a key, the corresponding pin drops to 0 volt.JBJB P2.0, Input1P2.0, Input1 ; High voltage on a pin means no input, 0 means it has input.; High voltage on a pin means no input, 0 means it has input.

ACallACall Action0Action0SJMPSJMP NextRound NextRoundInput1:Input1: JBJB P2.1, Input2P2.1, Input2ACallACall Action1Action1

SJMPSJMP NextRound NextRoundInput2:Input2:JBJB P2.2, NextRoundP2.2, NextRoundACallACall Action2Action2SJMPSJMP NextRound NextRound

NextRound:NextRound:SJmp MainloopSJmp Mainloop

Action0:Action0: ; Assume P2 is configured as output port. A high voltage on a pin indicates alarm.; Assume P2 is configured as output port. A high voltage on a pin indicates alarm.SetBSetB P2.0P2.0 ; Raise Alarm0 or start Motor0 etc. ; Raise Alarm0 or start Motor0 etc.RETRET

Action1:Action1:SetBSetB P2.1P2.1 ; Raise Alarm1 or start Motor1; Raise Alarm1 or start Motor1RETRET

Action2:Action2:SetBSetB P2.2P2.2 ; Raise Alarm2 or start Motor2; Raise Alarm2 or start Motor2RETRETENDEND

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2. The Nanokernel-based Model… 2. The Nanokernel-based Model… •The kernel provides the following minimal set of services: The kernel provides the following minimal set of services:

1.1. task creation and deletion; task creation and deletion; 2.2. task scheduling; task scheduling; 3.3. timing and interrupt management. timing and interrupt management.

•For the basic timing mechanismFor the basic timing mechanism, , the kernel uses a separate timer (tick) the kernel uses a separate timer (tick) interrupt routineinterrupt routine. . •At a conceptual level, At a conceptual level, this model includes this model includes a hardware abstraction layer a hardware abstraction layer for the (internal and external) devices. for the (internal and external) devices. •The design and implementation of this interface is entirely the The design and implementation of this interface is entirely the responsibility of the programmer. responsibility of the programmer. •From a layered view, From a layered view,

– the kemel is in layer 1, the kemel is in layer 1, – the interfacing and interrupt software is in layer 2, the interfacing and interrupt software is in layer 2, – and applications are in layer 3.and applications are in layer 3. 185


2. The Nanokernel-based Model… 2. The Nanokernel-based Model… •>> >> Interrupts enable hardware components to communicate their Interrupts enable hardware components to communicate their requests effectively to the processor requests effectively to the processor that eventually transfers the that eventually transfers the control to the operating system to attend the requests. control to the operating system to attend the requests. •>> Real-time tasks must be kept simple, efficient, and error free. >> Real-time tasks must be kept simple, efficient, and error free. •>> >> Exokernel, developed at MITExokernel, developed at MIT, is based on the philosophy that , is based on the philosophy that applications know how to manage the system resources better than applications know how to manage the system resources better than operating systems do. Operating systems must be simple and operating systems do. Operating systems must be simple and predictable, should be close enough to bare hardware, and support predictable, should be close enough to bare hardware, and support only the multiplexing capability of resources among applications only the multiplexing capability of resources among applications securely. securely.

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The Nanokernel-based Model… The Nanokernel-based Model… •>> >> The microkernel-based system is concerned with the design The microkernel-based system is concerned with the design approach,approach, not necessarily meaning a smaller system in overall size. not necessarily meaning a smaller system in overall size. The objective is to examine- and design operating systems from both The objective is to examine- and design operating systems from both simplistic- and performance points of view. simplistic- and performance points of view.

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MICROKERNEL VS MICROKERNEL VS MONOLITHIC KERNELMONOLITHIC KERNEL• A monolithic kernel A monolithic kernel is a kernel where is a kernel where – all services all services ((file system, VFS, device drivers, etcfile system, VFS, device drivers, etc) ) as well as as well as – core functionality core functionality ((scheduling, memory allocation, etc.scheduling, memory allocation, etc.) )

are a tight knit group sharing the same space. This directly are a tight knit group sharing the same space. This directly opposes a opposes a microkernelmicrokernel..

• A microkernel prefers an approach A microkernel prefers an approach where core where core functionality is isolated from system services functionality is isolated from system services and device and device drivers drivers ((which are basically just system serviceswhich are basically just system services).).

• VFSVFS: Virtual File System. Linux has basic file system as Extt2, Extt3, : Virtual File System. Linux has basic file system as Extt2, Extt3, Ext4 etc. FAT32, NTFS etc are visible to linux through VFS.Ext4 etc. FAT32, NTFS etc are visible to linux through VFS.

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Interrupt HandlingInterrupt Handling•For each interrupt, there is a fixed location in memory that holds the For each interrupt, there is a fixed location in memory that holds the address of its ISR. Fixed location has been set by the hardware. address of its ISR. Fixed location has been set by the hardware. Memory space available from this address is limited. Therefore, only a Memory space available from this address is limited. Therefore, only a jump instruction is written there by the programmer. A complete jump instruction is written there by the programmer. A complete subroutine is written starting at the new memory location. subroutine is written starting at the new memory location.

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• Steps in executing interrupts in the case of 8051 Series of Steps in executing interrupts in the case of 8051 Series of Microcontrollers:-Microcontrollers:-1.1. Upon activation of an interrupt , the microcontroller finishes the instruction Upon activation of an interrupt , the microcontroller finishes the instruction

it is executing and saves the address of the next instruction (Program it is executing and saves the address of the next instruction (Program Counter (PC)) on the stack.Counter (PC)) on the stack.

2.2. It also saves the current status of all the interrupts internally (ie not on the It also saves the current status of all the interrupts internally (ie not on the stack).stack).

3.3. It jumps to a fixed location in memory in accordance with the Interrupt It jumps to a fixed location in memory in accordance with the Interrupt Vector Table.Vector Table.

4.4. If the ISR is only one or two instructions, these may be written there itself.If the ISR is only one or two instructions, these may be written there itself.5.5. Generally, the ISR has many instructions. In such cases, a jump instruction is Generally, the ISR has many instructions. In such cases, a jump instruction is

placed at interrupt vector address.placed at interrupt vector address.6.6. The last instruction in the ISR is RETI (Return from Interrupt).The last instruction in the ISR is RETI (Return from Interrupt).7.7. Upon executing RETI instruction, the microcontroller returns to the place Upon executing RETI instruction, the microcontroller returns to the place

where it was interrupted. First it gets the Program Counter address from where it was interrupted. First it gets the Program Counter address from the stack by popping the top two bytes of the stack into the PC. Then it the stack by popping the top two bytes of the stack into the PC. Then it starts to execute from that address. starts to execute from that address. 191


• Interrupts in 8051Interrupts in 8051.. There are Six interrupts in 8051.There are Six interrupts in 8051.1.1. ResetReset.. When the reset pin is activated, When the reset pin is activated, the 8051 jumps to the 8051 jumps to

address location 0000. This is the power-up reset. Program execution starts address location 0000. This is the power-up reset. Program execution starts from address 0000.from address 0000.

2.2. Timer Interrupts (Two)Timer Interrupts (Two).. Two interrupts are set aside for the Two interrupts are set aside for the timers, one for Timer 0 and the other for Timer 1. Memory locations 000BH timers, one for Timer 0 and the other for Timer 1. Memory locations 000BH and 001BH in the interrupt vector table belong to Timer 0 and Timer 1 and 001BH in the interrupt vector table belong to Timer 0 and Timer 1 respectively.respectively.

3.3. External Hardware Interrupts (Two)External Hardware Interrupts (Two).. Pin No 12 (P3.2) and 13 (P3.3) in Pin No 12 (P3.2) and 13 (P3.3) in Port 3 are for the external hardware interrupts. INT0 and INT1, respectively. Port 3 are for the external hardware interrupts. INT0 and INT1, respectively. These external interrupts are also referred to as EX1 and EX2. Memory These external interrupts are also referred to as EX1 and EX2. Memory locations 0003H and 0013H in the interrupt vector table are assigned to locations 0003H and 0013H in the interrupt vector table are assigned to INT0 and INT1 , respectivelyINT0 and INT1 , respectively

4.4. Serial Communication InterruptSerial Communication Interrupt. . SSerial communication has a erial communication has a single interrupt that belongs to both receive and transfer. The interrupt single interrupt that belongs to both receive and transfer. The interrupt vector table location 0023H belongs to this interrupt.vector table location 0023H belongs to this interrupt.

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• RESETRESET 0000H0000H toto 0002H0002H == 3 Bytes3 Bytes• INT 0:INT 0: 0003H 0003H toto 000AH000AH == 8 Bytes8 Bytes• Timer 0:Timer 0: 000BH 000BH toto 0012H0012H == 8 Bytes8 Bytes• INT 1:INT 1: 0013H 0013H toto 001AH001AH == 8 Bytes8 Bytes• Timer 1:Timer 1: 001BH 001BH toto 0022H0022H == 8 Bytes8 Bytes• Serial COM:Serial COM: 0023H 0023H toto 002AH002AH == 8 Bytes8 Bytes

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INTERRUPT HANDLING IN 8051INTERRUPT HANDLING IN 8051ORGORG 0000H0000HLJMPLJMP MainLoop ; Long JMP is a three byte instruction with 16 Bit addressMainLoop ; Long JMP is a three byte instruction with 16 Bit address

; ISR for Timer 0 ; ISR for Timer 0 to generate square waveto generate square waveORGORG 000BH000BH ; This ISR is very small, It is written within 8 Bytes; This ISR is very small, It is written within 8 BytesCPLCPL P2.1P2.1RETIRETI ; Use RETI to return from ISR ; Use RETI to return from ISR

; ISR for External Hardware Interrupt INT 1 ; ISR for External Hardware Interrupt INT 1 ORGORG 0013H0013HLJMPLJMP StartAlarm ; If the ISR is longer than 8 Bytes, jump to subroutineStartAlarm ; If the ISR is longer than 8 Bytes, jump to subroutineRETIRETI

ORGORG 0030H0030H ; After vector table space; After vector table spaceMainLoopMainLoop

; Keep waiting for interrupts in this loop; Keep waiting for interrupts in this loopSJMP MainLoopSJMP MainLoop ; Short JMP is a two byte instruction with Relative Address; Short JMP is a two byte instruction with Relative Address

StartAlarm:StartAlarm:SetBSetB P1.0P1.0 ; Alarm circuit connected to P1.0; Alarm circuit connected to P1.0;…;… …… ; Write more instructions here; Write more instructions hereRETIRETI ; Use RETI to return from ISR; Use RETI to return from ISR

ENDEND194

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• Interrupt Driven, Interrupt Driven, • Nanokernel, Nanokernel, • Microkernel Microkernel

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3. The Microkernel-based Model. 3. The Microkernel-based Model. •This model is the next improvement over the nanokernel model. This model is the next improvement over the nanokernel model. •Essentially Essentially more functions are added to the kernelmore functions are added to the kernel, and interfaces for , and interfaces for board devices board devices is provided as a package called is provided as a package called board support packageboard support package ((BSPBSP). ). •At the kernel level, the following At the kernel level, the following threethree additional functionalities are additional functionalities are provided: provided:

1.1. mechanisms such as mechanisms such as semaphore and monitor semaphore and monitor are supported for process are supported for process synchronization; (synchronization; (a semaphore is a variable that is used for controlling access, by multiple processes, to a common resource in a parallel programming or a multi user environment.))

2.2. primitives such as primitives such as channel and mailbox channel and mailbox are supported for inter-process are supported for inter-process communication; communication;

3.3. functions such as functions such as allocation and deallocation allocation and deallocation are supported for dynamic are supported for dynamic memory allocation. memory allocation.

•The purpose of The purpose of BSPBSP is to minimize the effort involved in developing is to minimize the effort involved in developing interface softwareinterface software. . 197

STRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMSSTRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMS3.3. The Microkernel-based Model. The Microkernel-based Model. • At the kernel level, the following At the kernel level, the following threethree additional functionalities are provided: additional functionalities are provided:

1.1. mechanisms such as mechanisms such as semaphore and monitor semaphore and monitor are supported for process synchronization; are supported for process synchronization; 2.2. primitives such as primitives such as channel and mailbox channel and mailbox are supported for inter-process communication; are supported for inter-process communication; 3.3. functions such as functions such as allocation and deallocation allocation and deallocation are supported for dynamic memory are supported for dynamic memory

allocation. allocation. 1.1. Semaphor.Semaphor. A semaphore is a variable that is used for controlling access, by multiple A semaphore is a variable that is used for controlling access, by multiple

processes, to a common resource processes, to a common resource in a in a parallel programming parallel programming or a or a multi user environmentmulti user environment..2.2. MonitorMonitor.. Monitors are high-level programming language concepts that make mutual exclusion Monitors are high-level programming language concepts that make mutual exclusion

of critical section “automatic” and therefore less error-prone. They require compiler support.of critical section “automatic” and therefore less error-prone. They require compiler support.3.3. Channel and MailboxChannel and Mailbox. .

1.1. ChannelChannel.. Communication happens when a sender does put(Chan, Msg) and a Communication happens when a sender does put(Chan, Msg) and a receiver does get(Chan). Obviously the receiver cannot proceed until the sender has a receiver does get(Chan). Obviously the receiver cannot proceed until the sender has a message for it, but with channels the sender cannot proceed until the receiver asks for the message for it, but with channels the sender cannot proceed until the receiver asks for the message. message.

2.2. MailboxMailbox.. A mailbox is a variable which can be in two states: empty (when it A mailbox is a variable which can be in two states: empty (when it cannot be read), and full (when it cannot be written).cannot be read), and full (when it cannot be written).

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3. The Microkernel-based Model… 3. The Microkernel-based Model… •The embedded operating system The embedded operating system QNXQNX (“Quick UNIX”) and (“Quick UNIX”) and SymbianSymbian are microkeenel-based operating systems. are microkeenel-based operating systems. •Symbian has many layers with Symbian has many layers with

– a nanokemel a nanokemel for innermost layer, for innermost layer, – the the Symbian OS kernel Symbian OS kernel for the next level, for the next level, – then the then the microkernel serversmicrokernel servers, , – and finally and finally user applications user applications in the in the outermost layer. outermost layer.

•Symbian OS Design RulesSymbian OS Design Rules– User data is sacredUser data is sacred– User time is preciousUser time is precious– All resources are scarceAll resources are scarce

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3. The Microkernel-based Model… 3. The Microkernel-based Model… •The microkernel is a popular term now and, rather than offering a The microkernel is a popular term now and, rather than offering a policy, policy, its objective is confined to its objective is confined to offering only the basic mechanisms offering only the basic mechanisms necessary to implement the operating system policies. necessary to implement the operating system policies. •The terms nanokernel and picokernels were used to refer to kernels The terms nanokernel and picokernels were used to refer to kernels smaller than the microkernel. smaller than the microkernel. •With the above generic characterization of the microkernel, the With the above generic characterization of the microkernel, the nanokernel, picokernel, and exokernel were subsumed (included) by nanokernel, picokernel, and exokernel were subsumed (included) by the microkernel paradigm. the microkernel paradigm. •The plan was for the microkernel to implement the essential core- The plan was for the microkernel to implement the essential core- operating system primitives so that the operating system services operating system primitives so that the operating system services could be implemented on the top of the kernel. could be implemented on the top of the kernel. •However, this objective was not completely realized in most However, this objective was not completely realized in most implementations in practice. implementations in practice.

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3. The Microkernel-based Model… 3. The Microkernel-based Model… •Typically, the functions such as Typically, the functions such as

– task management, task management, – inter-task communication, inter-task communication, – task address space management, task address space management, – and hardware abstraction and hardware abstraction are implemented in the kernel level. are implemented in the kernel level.

•Other services Other services are implemented on the next level to run usually at are implemented on the next level to run usually at the user level. the user level. •The first conceptual breakthrough towards the real microkernel was The first conceptual breakthrough towards the real microkernel was the external pager implemented in the Mach microkernel developed the external pager implemented in the Mach microkernel developed at Carnegie Mellon University. at Carnegie Mellon University. •In Mach, the kernel manages the physical- and virtual memory but In Mach, the kernel manages the physical- and virtual memory but forwards page faults to specific user-level tasks called pagers. forwards page faults to specific user-level tasks called pagers.

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3. The Microkernel-based Model… 3. The Microkernel-based Model… •After a page fault, it is the pagers’ responsibility to bring the After a page fault, it is the pagers’ responsibility to bring the corresponding page from the disk to the kemel space. corresponding page from the disk to the kemel space. •The next conceptual step was The next conceptual step was the the idea of handling interrupts as IPC idea of handling interrupts as IPC messages messages and and including I/O ports in the address spacesincluding I/O ports in the address spaces. . •The kemel captures the interruptThe kemel captures the interrupt, , converts it into an IPC messageconverts it into an IPC message, , and sends it to the appropriate user level process and sends it to the appropriate user level process associated with that associated with that interrupt to handle it.interrupt to handle it.•Usually, Usually, the device drivers are the intenupt handlers the device drivers are the intenupt handlers and are kept in and are kept in the user space. the user space.

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MICROKERNEL VS MICROKERNEL VS MONOLITHIC KERNELMONOLITHIC KERNEL• A monolithic kernel A monolithic kernel is a kernel where is a kernel where – all services all services ((file system, VFS, device drivers, etcfile system, VFS, device drivers, etc) ) as well as as well as – core functionality core functionality ((scheduling, memory allocation, etc.scheduling, memory allocation, etc.) )

are a tight knit group sharing the same space. This directly are a tight knit group sharing the same space. This directly opposes a opposes a microkernelmicrokernel..

• A microkernel prefers an approach A microkernel prefers an approach where core where core functionality is isolated from system services functionality is isolated from system services and device and device drivers drivers ((which are basically just system serviceswhich are basically just system services).).

• VFSVFS: Virtual File System. Linux has basic file system as Extt2, Extt3, : Virtual File System. Linux has basic file system as Extt2, Extt3, Ext4 etc. FAT32, NTFS etc are visible to linux through VFS.Ext4 etc. FAT32, NTFS etc are visible to linux through VFS.

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4. The Monolithic-kernel-based Model. 4. The Monolithic-kernel-based Model. •No standards exist for this modelNo standards exist for this model. . •Any design not following the above philosophies may be considered Any design not following the above philosophies may be considered under this model. under this model. •Typically, Typically, added functionalities in this model are the followingadded functionalities in this model are the following: :

1.1. sophisticated CPU scheduling; sophisticated CPU scheduling; 2.2. solutions for priority inversion issues; solutions for priority inversion issues; 3.3. improved memory management —allocation and protection improved memory management —allocation and protection

(isolating the applications software from the kernel by supporting the two (isolating the applications software from the kernel by supporting the two operating modes adding an isolation barrier between the individual tasks); operating modes adding an isolation barrier between the individual tasks);

4.4. file handling; file handling; 5.5. graphics handling: and graphics handling: and

6.6. networking. networking. 207


4. The Monolithic-kernel-based Model… 4. The Monolithic-kernel-based Model… •Generally, Generally, an operating system an operating system may be considered as its may be considered as its kernel with kernel with the remaining partthe remaining part. . •In this modelIn this model, , since there is no separation within the operating since there is no separation within the operating system as kernel and the remaining partsystem as kernel and the remaining part, , the entire operating system the entire operating system may be viewed as a monolithic structure and hence referred to as may be viewed as a monolithic structure and hence referred to as monolithic kernel based systems. monolithic kernel based systems. •RT-Linux is a monolithic kernel based real-time operating system RT-Linux is a monolithic kernel based real-time operating system and and Linux kernels are highly portable and easily configurable. Linux kernels are highly portable and easily configurable.

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4. The Monolithic-kernel-based Model… 4. The Monolithic-kernel-based Model… •In summary, In summary,

1.1. multitasking and preemption, multitasking and preemption, 2.2. predictable performance and synchronization, predictable performance and synchronization, 3.3. support for a range of priority levels and priority determination, support for a range of priority levels and priority determination, 4.4. and bounded latency on task switching and interrupt handling and bounded latency on task switching and interrupt handling are some of the basic operating system requirements for real-time systems. are some of the basic operating system requirements for real-time systems.

•With this introduction to REOS, With this introduction to REOS, we next focus on individual topics we next focus on individual topics such as such as

– scheduling, scheduling, – memory management, memory management, – synchronization, synchronization, – and file systems. and file systems.

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4. The Monolithic-kernel-based Model… 4. The Monolithic-kernel-based Model… •>> Despite the appeal and advantages of the microkemel paradigm, it >> Despite the appeal and advantages of the microkemel paradigm, it was not widely accepted until recently. Further, most of the earlier was not widely accepted until recently. Further, most of the earlier microkemels were evolved from monolithic kemels and, therefore, did microkemels were evolved from monolithic kemels and, therefore, did not have many essential characteristics of the real microkemel. not have many essential characteristics of the real microkemel. •>> Real-time software designers generally perceive separate kemel >> Real-time software designers generally perceive separate kemel spaces and separate process address spaces as disadvantageous for spaces and separate process address spaces as disadvantageous for time- critical applications. time- critical applications.

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4. The Monolithic-kernel-based Model… 4. The Monolithic-kernel-based Model… •A monolithic kernel is an operating system architecture where A monolithic kernel is an operating system architecture where the the entire operating system is working in kernel space entire operating system is working in kernel space and is alone and is alone in in supervisor mode. supervisor mode. •The monolithic model differs from other operating system The monolithic model differs from other operating system architectures (such as the microkernel architecture)architectures (such as the microkernel architecture) in that it alone in that it alone defines a high-level virtual interface over computer hardware. defines a high-level virtual interface over computer hardware. •A set of primitives or system calls implement all operating system A set of primitives or system calls implement all operating system services such as process management, concurrency, and memory services such as process management, concurrency, and memory management. management. •Device drivers can be added to the kernel as modules.Device drivers can be added to the kernel as modules.

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4. The Monolithic-kernel-based Model… 4. The Monolithic-kernel-based Model…

Kernel SpaceKernel Space•System memorySystem memory in Linux can be divided into two distinct regions: in Linux can be divided into two distinct regions: kernel spacekernel space and and user spaceuser space. . •Kernel space is where the Kernel space is where the kernelkernel (i.e., the core of the operating (i.e., the core of the operating system) system) executesexecutes (i.e., runs) and provides its (i.e., runs) and provides its servicesservices. . •Memory consists of Memory consists of RAMRAM (random access memory) cells, whose (random access memory) cells, whose contents can be contents can be accessedaccessed (i.e., read and written to) at extremely high (i.e., read and written to) at extremely high speeds but are retained only temporarily (i.e., while in use or, at most, speeds but are retained only temporarily (i.e., while in use or, at most, while the power supply remains on). Its purpose is to hold programs while the power supply remains on). Its purpose is to hold programs and data that are currently in use and thereby serve as a high speed and data that are currently in use and thereby serve as a high speed intermediary between the CPU (central processing unit) and the much intermediary between the CPU (central processing unit) and the much slower slower storagestorage, which most commonly consists of one or more hard , which most commonly consists of one or more hard disk drives (HDDs). disk drives (HDDs).

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4. The Monolithic-kernel-based Model… 4. The Monolithic-kernel-based Model…

User SpaceUser Space•User space is that set of memory locations in which User space is that set of memory locations in which user processesuser processes (i.e., everything (i.e., everything other than the kernel) run. A other than the kernel) run. A processprocess is an executing instance of a program. is an executing instance of a program. •One of the roles of the kernel One of the roles of the kernel is to manage individual user processes is to manage individual user processes within this within this space space and to prevent them from interfering with each other. and to prevent them from interfering with each other. •Kernel space can be accessed by user processes only through the use of Kernel space can be accessed by user processes only through the use of system system callscalls.. •System calls are requests in a Unix-like operating system by an System calls are requests in a Unix-like operating system by an active processactive process for a for a service performed by the kernel, such as service performed by the kernel, such as input/outputinput/output (I/O) or process creation. (I/O) or process creation. •An active process is a process that is currently progressing in the CPU, as contrasted An active process is a process that is currently progressing in the CPU, as contrasted with a process that is waiting for its next turn in the CPU. with a process that is waiting for its next turn in the CPU. •I/O is any program, operation or device that transfers data to or from a CPU and to I/O is any program, operation or device that transfers data to or from a CPU and to or from a peripheral device (such as disk drives, keyboards, mice and printers). or from a peripheral device (such as disk drives, keyboards, mice and printers).

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– Scheduling:Scheduling:

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SCHEDULINGSCHEDULINGCPU Scheduling CPU Scheduling •Real-time task scheduling is one of the interesting topics Real-time task scheduling is one of the interesting topics and is and is deeply studied in the context of real-time systems. deeply studied in the context of real-time systems. •The interest in the topic started with the seminal (The interest in the topic started with the seminal (related to origin or seedsrelated to origin or seeds) ) work of Liu and Layland in 1973. Since then, many algorithms have work of Liu and Layland in 1973. Since then, many algorithms have been proposed for real-time scheduling. been proposed for real-time scheduling. •Recently, the field is receiving renewed interest due to the Recently, the field is receiving renewed interest due to the pervasiveness of embedded devices in the consumer market and the pervasiveness of embedded devices in the consumer market and the advancement of technological innovations. advancement of technological innovations. •Real-time task scheduling is an important responsibility of real-time Real-time task scheduling is an important responsibility of real-time systems. systems.

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SCHEDULINGSCHEDULINGCPU Scheduling… CPU Scheduling… •Examples of real-time tasks include Examples of real-time tasks include

– control of temperature control of temperature in a chemical plant, in a chemical plant, – collecting readings collecting readings from sensor nodes periodically, from sensor nodes periodically, – monitoringmonitoring systems for nuclear reactors, etc. systems for nuclear reactors, etc.

•Based on their importance, real-time tasks are usually prioritized.Based on their importance, real-time tasks are usually prioritized.

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SCHEDULINGSCHEDULINGCPU Scheduling… CPU Scheduling… •>> >> •Priority is very important in REOS, Priority is very important in REOS, and nothing should prevent the and nothing should prevent the execution of the highest priority tasks in the system. execution of the highest priority tasks in the system. •>> >> •Ignoring context switch cost Ignoring context switch cost in task scheduling is not appropriate for in task scheduling is not appropriate for most modem systems. most modem systems. •Real-time scheduling algorithms are generally preemptiveReal-time scheduling algorithms are generally preemptive, and , and preemption introduces the context switchpreemption introduces the context switch. . •In addition to the context switch, In addition to the context switch, preemption also involves activities such aspreemption also involves activities such as processing interrupts, manipulating task queuesprocessing interrupts, manipulating task queues, etc. , etc. •This cost is significantly high if the system uses caches in single- or multi-This cost is significantly high if the system uses caches in single- or multi-levels—and cache memory is used in almost all systems today. levels—and cache memory is used in almost all systems today.

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SCHEDULINGSCHEDULINGCPU Scheduling… CPU Scheduling… •Since timely execution of these tasks is of paramount importance, Since timely execution of these tasks is of paramount importance, the the real-time CPU scheduler must make sure that the tasks meet their real-time CPU scheduler must make sure that the tasks meet their deadlines. deadlines. •Schedulability analysis Schedulability analysis is a fundamental aspect of real-time is a fundamental aspect of real-time scheduling. That is, checking whether a set of given tasks can be scheduling. That is, checking whether a set of given tasks can be executed in the system executed in the system without missing the deadlines without missing the deadlines is crucial for is crucial for many life critical systems before the tasks are actually scheduled in many life critical systems before the tasks are actually scheduled in the system. the system. •A set of tasks is said to be A set of tasks is said to be schedulableschedulable if if enough CPU time is available enough CPU time is available to execute all these tasks before their deadlines. to execute all these tasks before their deadlines. •For this reasonFor this reason, scheduling in real-time systems is not the same as , scheduling in real-time systems is not the same as scheduling in traditional operating systems. scheduling in traditional operating systems.

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SCHEDULINGSCHEDULINGCPU Scheduling… CPU Scheduling… •Each real-time task is assigned a priority and a deadlineEach real-time task is assigned a priority and a deadline. . Also, most Also, most real-time tasks are executed periodically. real-time tasks are executed periodically. Sometimes, execution Sometimes, execution priorities are derived from deadlines and/or periods. priorities are derived from deadlines and/or periods. •Most real-time scheduling algorithms are “priority-based preemptive Most real-time scheduling algorithms are “priority-based preemptive scheduling”. scheduling”. This scheme allows only the highest priority task among This scheme allows only the highest priority task among the ready tasks to run at any moment. When a task with priority higher the ready tasks to run at any moment. When a task with priority higher than currently running task becomes ready, then the current task is than currently running task becomes ready, then the current task is preempted and the new higher priority task is allowed to run preempted and the new higher priority task is allowed to run immediately. immediately. •The crux of these classes of algorithms is The crux of these classes of algorithms is how these task priorities are how these task priorities are determined and when.determined and when. Accordingly, Accordingly, real-time scheduling algorithmsreal-time scheduling algorithms can can be classified into be classified into two categoriestwo categories: : – fixedfixed (static) (static) priority algorithms priority algorithms and and – dynamic priority algorithmsdynamic priority algorithms. . 222

SCHEDULINGSCHEDULING• Earlier studies on real-time scheduling assumed a simple but Earlier studies on real-time scheduling assumed a simple but

powerful model in which tasks are assumed to be periodic. powerful model in which tasks are assumed to be periodic. • For exampleFor example, a task is designed to , a task is designed to read a temperature sensor value read a temperature sensor value

in a plant every 50 secondsin a plant every 50 seconds or or scan a security area every l0 secondsscan a security area every l0 seconds. . • These tasks are activated These tasks are activated periodicallyperiodically to complete their missions. If to complete their missions. If

a task's relative activation time (period) is not known then it is a a task's relative activation time (period) is not known then it is a non-periodicnon-periodic task. task.

• If a non-periodic task If a non-periodic task is is either either soft soft or or has no deadline then it is has no deadline then it is called called aperiodicaperiodic task. task.

• A non-periodic task A non-periodic task with a hard deadline with a hard deadline is called is called sporadic task sporadic task ((sporadic: recurring in scattered and irregular or unpredictable instancessporadic: recurring in scattered and irregular or unpredictable instances)). .

• We start with We start with scheduling of periodic tasksscheduling of periodic tasks. .

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKS

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks Scheduling Periodic Tasks •The periodic task model is the simplest but sufficient for many The periodic task model is the simplest but sufficient for many applications. applications. •The following The following assumptionsassumptions are made for this system: are made for this system:

1.1. All tasks run periodically on a All tasks run periodically on a single CPUsingle CPU. . 2.2. Deadlines are at the end of their periodDeadlines are at the end of their period. That is, for a period p, the . That is, for a period p, the

deadlines are at p, 2p, 3p, …. deadlines are at p, 2p, 3p, …. 3.3. The tasks are independentThe tasks are independent..4.4. The execution time for each task is fixed. The execution time for each task is fixed. 5.5. The context switch time is ignoredThe context switch time is ignored. .

•Liu and Layland introduced two real-time scheduling algorithmsLiu and Layland introduced two real-time scheduling algorithms, , called called rat monotonic rat monotonic (RM) (RM) (increasing) (increasing) and and earliest deadline first earliest deadline first (EDF)(EDF), in , in 1973. 1973. •RM is a fixed priority scheduling algorithm RM is a fixed priority scheduling algorithm which assigns higher which assigns higher priorities to tasks with shorter periods (Higher frequency)priorities to tasks with shorter periods (Higher frequency). . 225

SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… •RM is a fixed priority scheduling algorithm RM is a fixed priority scheduling algorithm which assigns higher which assigns higher priorities to tasks with shorter periods (Higher Frequency)priorities to tasks with shorter periods (Higher Frequency). . •EDF EDF ((Earliest Deadline FirstEarliest Deadline First) ) is a dynamic priority scheduling algorithm is a dynamic priority scheduling algorithm which assigns which assigns higher priorities to tasks with the current earliest higher priorities to tasks with the current earliest deadlinedeadline. . •It is easy to see that RM and EDF are simple, and they are proved to It is easy to see that RM and EDF are simple, and they are proved to be optimal in their respective classes. be optimal in their respective classes.

•>> >> •RM and EDF algorithms are widely studied and extensively analyzed. RM and EDF algorithms are widely studied and extensively analyzed. •Surprisingly, Surprisingly, almost all other algorithms proposed in literature later almost all other algorithms proposed in literature later are only variations of these two basic algorithmsare only variations of these two basic algorithms. .

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… •RM is used for most practical applications. RM is used for most practical applications. •The reasons for favouring RM over EDF are based on the beliefs that The reasons for favouring RM over EDF are based on the beliefs that – RM is easier to implement, RM is easier to implement, – introduces lesser runtime overhead, introduces lesser runtime overhead, – is easier to analyze, is easier to analyze, – more predictable in overloaded conditions, more predictable in overloaded conditions, – and has lesser jitter in task execution; and has lesser jitter in task execution; the variation in task the variation in task

execution delays is called execution delays is called jitterjitter. .

•>> If jitter occurs, many undesirable consequences may result in the >> If jitter occurs, many undesirable consequences may result in the system. So, reducing jitter is one objective of real-time scheduling. system. So, reducing jitter is one objective of real-time scheduling.

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… 1. Priority Scheduling Algorithm.1. Priority Scheduling Algorithm.

– The objective The objective of priority scheduling algorithms is simply that: of priority scheduling algorithms is simply that: • at any time, at any time, the scheduler selects the highest priority ready taskthe scheduler selects the highest priority ready task; and ; and • the selected task runs until either it completes its execution for that the selected task runs until either it completes its execution for that

period or another task with priority higher than it becomes ready for period or another task with priority higher than it becomes ready for execution. execution.

– An implementation scheme An implementation scheme for a priority scheduler is described as follows. for a priority scheduler is described as follows. • The scheduler maintains essentially The scheduler maintains essentially two queuestwo queues: : ready queue ready queue and and wait wait

queuequeue. . • The The ready queue ready queue contains tasks which are ready to run and the contains tasks which are ready to run and the wait wait

queuequeue contains contains tasks that have already run and are waiting tasks that have already run and are waiting for their next for their next period to start again. period to start again.

• The The ready queue is ordered by ready queue is ordered by task prioritytask priority and the and the wait queue is ordered wait queue is ordered by the by the earliest start timeearliest start time. .

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… 1. Priority Scheduling Algorithm…1. Priority Scheduling Algorithm…

• When the scheduler isWhen the scheduler is invokedinvoked, , it examines tasks in the it examines tasks in the wait queue wait queue to see to see if any task should be moved to the if any task should be moved to the ready queue ready queue at that point of time. at that point of time.

• Then it compares the Then it compares the head taskhead task at the ready queue at the ready queue to to currently running currently running tasktask. .

• If the priority of the head task is higher than that of the running taskIf the priority of the head task is higher than that of the running task, , then the scheduler invokes a context switch. then the scheduler invokes a context switch.

• The scheduler is invoked by an The scheduler is invoked by an interruptinterrupt from either an from either an external eventexternal event or or a a timertimer. .

• The start time of a task might trigger a timer interrupt. The start time of a task might trigger a timer interrupt. • Other efficient implementations are possible. Other efficient implementations are possible.

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… 2. Rate Monotonic Scheduling Algorithm.2. Rate Monotonic Scheduling Algorithm. – The crux (The crux (a vital, basic, decisive, or pivotal pointa vital, basic, decisive, or pivotal point) of the RM scheduling ) of the RM scheduling

algorithm lies in the way the priorities are computed. algorithm lies in the way the priorities are computed. – RM computes priorities based on task periods. RM computes priorities based on task periods. – A task with a shorter period has higher priority. A task with a shorter period has higher priority. That is, That is, the task the task

with the higher rate of occurrences has higher prioritywith the higher rate of occurrences has higher priority, , hence hence the name rate monotonicthe name rate monotonic. .

– Since the period of each task is fixed, Since the period of each task is fixed, once their priorities are once their priorities are computed and assigned in advancecomputed and assigned in advance, , the priorities stay static.the priorities stay static.

– For the following discussion, we use For the following discussion, we use the notation T(the notation T(ee,,pp) ) to to denote a denote a task Ttask T with with execution requirement of e time units execution requirement of e time units and and period p time unitsperiod p time units. .

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… 2. Rate Monotonic Scheduling Algorithm.2. Rate Monotonic Scheduling Algorithm.

– Consider three periodic tasks T1(1,4), T2(2,5), and T3(3,10), as shown in Consider three periodic tasks T1(1,4), T2(2,5), and T3(3,10), as shown in Figure 15.1Figure 15.1. ( . ( T1(1,4) means: execution time = 1 Unit, Periodicity every four units of time. T1(1,4) means: execution time = 1 Unit, Periodicity every four units of time. ))

– The The down arrow indicatesdown arrow indicates both the ending of the previous period and both the ending of the previous period and starting of the new period. starting of the new period.

– Tasks are activated at every starting period. Tasks are activated at every starting period. According to RMAccording to RM, , T1 has the T1 has the highest rate of 1/4 highest rate of 1/4 and, therefore, has the highest priority; and, therefore, has the highest priority; T2 has the next T2 has the next highest rate of 1/5 highest rate of 1/5 and, therefore, has the next higher priority; and and, therefore, has the next higher priority; and T3 has T3 has the lowest rate of 1/10the lowest rate of 1/10 and hence has the lowest priority. All three tasks are and hence has the lowest priority. All three tasks are ready for execution at time 0ready for execution at time 0. .

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We use We use the notation the notation T(T(ee,,pp)) to denote to denote a a task Ttask T with with execution requirement of execution requirement of e time units e time units and and period p time unitsperiod p time units

SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… 2. Rate Monotonic Scheduling Algorithm.2. Rate Monotonic Scheduling Algorithm. •>> In fixed priority scheduling, task priorities are assumed to be fixed throughout >> In fixed priority scheduling, task priorities are assumed to be fixed throughout the execution, Dynamic priority scheduling computes the priorities during runtime. the execution, Dynamic priority scheduling computes the priorities during runtime.

•At time 0, since T1 has the highest priority, it starts its execution and At time 0, since T1 has the highest priority, it starts its execution and completes at time 1. completes at time 1. •At time 1, T2, the currently highest priority ready task, can start its At time 1, T2, the currently highest priority ready task, can start its execution and completes it at time 3. execution and completes it at time 3.

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SCHEDULING PERIODIC TASKSSCHEDULING PERIODIC TASKSScheduling Periodic Tasks… Scheduling Periodic Tasks… 2. Rate Monotonic Scheduling Algorithm.2. Rate Monotonic Scheduling Algorithm. •

•Now, at time 3, Now, at time 3, T3 can start its executionT3 can start its execution, , but at time 4 the highest priority task T1 will but at time 4 the highest priority task T1 will be again ready be again ready and that will preempt T3, and run until time 5. and that will preempt T3, and run until time 5. •Since T2 arrives at time 5, T3 has to wait until T2 completes its execution at time 7. Since T2 arrives at time 5, T3 has to wait until T2 completes its execution at time 7. •Now, T3 can have 1 unit of execution at time 7 before Now, T3 can have 1 unit of execution at time 7 before T1 arrives at time 8T1 arrives at time 8. . •Then after T1 finishes at time 9, T3 can complete its execution for the first period at Then after T1 finishes at time 9, T3 can complete its execution for the first period at time 10. time 10. •In this example, In this example, T3 is preempted twice in its first periodT3 is preempted twice in its first period, but eventually completes its , but eventually completes its execution on time. execution on time. 234

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RATE MONOTONIC SCHEDULING ALGORITHMRATE MONOTONIC SCHEDULING ALGORITHM• Consider another example (Example 2). Consider another example (Example 2). • Three periodic tasks are T1(2,4), T2(2,6), and T3(3,Three periodic tasks are T1(2,4), T2(2,6), and T3(3,1212), as shown if Figure 15.2. ), as shown if Figure 15.2.

• According to RM, T1 has the highest priority: T2 has the next highest priority; and According to RM, T1 has the highest priority: T2 has the next highest priority; and the task T3 has the lowest priority. the task T3 has the lowest priority.

• All three tasks are ready for execution at time 0. All three tasks are ready for execution at time 0. • Now, in the time interval Now, in the time interval 0 to 120 to 12, T1 must execute 3 times, T2 must execute 2 , T1 must execute 3 times, T2 must execute 2

times, and T3 must execute 1 time. times, and T3 must execute 1 time. • So we need So we need 6 6 (3x2=6) (3x2=6) + 4 + 4 (2x2=4) (2x2=4) + 3 + 3 (3x1=3(3x1=3) = 13 units of execution time) = 13 units of execution time in in 12 12

units of real timeunits of real time, which is not possible., which is not possible. 236

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RATE MONOTONIC SCHEDULING ALGORITHMRATE MONOTONIC SCHEDULING ALGORITHM• Consider another example (Example 2)… Consider another example (Example 2)… • Three periodic tasks are T1(2,4), T2(2,6), and T3(3,12), as shown if Figure 15.2. Three periodic tasks are T1(2,4), T2(2,6), and T3(3,12), as shown if Figure 15.2.

• Another related metric Another related metric is is utilizationutilization that is computed as the sum of execution that is computed as the sum of execution ratios of the tasks. ratios of the tasks.

• That isThat is, in the above example, utilization is , in the above example, utilization is 2/4+2/6+ 3/12 = 2/4+2/6+ 3/12 = 13/1213/12. . • If the utilization is above 100 per centIf the utilization is above 100 per cent, , the tasks cannot be scheduled to meet the tasks cannot be scheduled to meet

deadlines.deadlines. This is a necessary condition in theory, This is a necessary condition in theory, but not a sufficient conditionbut not a sufficient condition. . • Therefore, Therefore, these three tasks are not schedulablethese three tasks are not schedulable and some task, naturally the and some task, naturally the

lowest priority task, cannot meet its deadline. lowest priority task, cannot meet its deadline. 237

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RATE MONOTONIC SCHEDULING ALGORITHMRATE MONOTONIC SCHEDULING ALGORITHM• Consider another example (Example 2)… Consider another example (Example 2)… • Three periodic tasks are T1(2,4), T2(2,6), and T3(3,12), as shown if Figure 15.2. Three periodic tasks are T1(2,4), T2(2,6), and T3(3,12), as shown if Figure 15.2.

• Having less than 100 per cent utilization does not imply that the task set is Having less than 100 per cent utilization does not imply that the task set is schedulableschedulable. It has to be verified practically. . It has to be verified practically.

• For a given task setFor a given task set, the , the least common multiplierleast common multiplier aka LCM aka LCM of all the task periods of all the task periods is called the is called the hyperperiodhyperperiod of the task set. of the task set.

• For the task set shown in For the task set shown in Figure 15.2, Figure 15.2, the hyperperiod is 12the hyperperiod is 12. . • Since all tasks will have their Since all tasks will have their start times simultaneously at the beginningstart times simultaneously at the beginning of the of the

next hyperperiod, the schedule just repeats itself in each hyperperiodnext hyperperiod, the schedule just repeats itself in each hyperperiod. Therefore, . Therefore, it is enough to verify task schedulability for one hyperperiod. it is enough to verify task schedulability for one hyperperiod. 238

/2/2 44 66 1212

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RATE MONOTONIC SCHEDULING ALGORITHMRATE MONOTONIC SCHEDULING ALGORITHMExample 3 (Task Utilisation < 100% but Task Set Not Schedulable)Example 3 (Task Utilisation < 100% but Task Set Not Schedulable)•Three periodic tasks are T1(1,3), T2(1,4), and T3(2,5), as shown if Figure 15.3. Three periodic tasks are T1(1,3), T2(1,4), and T3(2,5), as shown if Figure 15.3.

•According to RM According to RM T1 has the highest priority; T2 has the next highest priority; and T3 T1 has the highest priority; T2 has the next highest priority; and T3 has the lowest priority. has the lowest priority. •All three tasks are ready for execution at time 0. All three tasks are ready for execution at time 0. •The hyperperiod for The hyperperiod for Example Task Set 3, illustrated in Figure 15.3, is 60Example Task Set 3, illustrated in Figure 15.3, is 60,, and and task task utilizationutilization 1/3 + 1/4 + 2/5 = 1/3 + 1/4 + 2/5 = 0.98330.9833. . •Although the utilization is 98.33 per cent, Although the utilization is 98.33 per cent, which is less than 100 per centwhich is less than 100 per cent, , this task this task set is not schedulable under RMset is not schedulable under RM. .

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RATE MONOTONIC SCHEDULING ALGORITHMRATE MONOTONIC SCHEDULING ALGORITHM• Consider the following example (Example 3)… Consider the following example (Example 3)… • Three periodic tasks are T1(1,3), T2(1,4), and T3(2,5), as shown if Figure 15.3. Three periodic tasks are T1(1,3), T2(1,4), and T3(2,5), as shown if Figure 15.3.

• Tasks Tasks T1T1 and and T2T2 take time intervals take time intervals 0-10-1 and and 1-21-2, and task , and task T3T3 the the time interval time interval 2-32-3, , thenthen T1 and T2 T1 and T2 again take time intervals again take time intervals 3-43-4 and and 4-54-5, respectively. , respectively.

• Now, T3, having executed for only 1 unit of timeNow, T3, having executed for only 1 unit of time, , misses its misses its deadline deadline (it has to complete execution for 2 units of time (it has to complete execution for 2 units of time before before time 5time 5) ) for the first periodfor the first period. . 241

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SCHEDULINGSCHEDULINGProcessor Utilisation Under RM AlgorithmProcessor Utilisation Under RM Algorithm•>> >> •Processor utilization (U) Processor utilization (U) for any feasible schedule under RM generally for any feasible schedule under RM generally decreases as the number of tasks (n) increases decreases as the number of tasks (n) increases

U = n (2U = n (21/n1/n - 1) - 1) •When the number of tasks increasesWhen the number of tasks increases, the , the CPU utilization reaches to CPU utilization reaches to about 69 per cent. about 69 per cent. •The theoretical limit of 69 per cent indicates that RM The theoretical limit of 69 per cent indicates that RM couldcould waste as waste as much as about 31 per cent of CPU time.much as about 31 per cent of CPU time. •The next algorithm could bring down the CPU wastage time close to 0 The next algorithm could bring down the CPU wastage time close to 0 percentpercent..

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SCHEDULINGSCHEDULINGScheduling Periodic Tasks… Scheduling Periodic Tasks…

3. Earliest-Deadline-First Scheduling Algorithm.3. Earliest-Deadline-First Scheduling Algorithm.•The purpose of EDF is to The purpose of EDF is to assign priorities to tasks dynamicallyassign priorities to tasks dynamically, based , based on the current order of their deadlines. on the current order of their deadlines. •The The highest-priority task is the one whose deadline is earliesthighest-priority task is the one whose deadline is earliest. . •Clearly, Clearly, the priorities must be recalculated at every scheduling point.the priorities must be recalculated at every scheduling point. •Similar to RM, Similar to RM, at any momentat any moment, the highest priority task is executed, , the highest priority task is executed, but the priority of the task changes over time. but the priority of the task changes over time. •We have shown that We have shown that Example Task Set 3Example Task Set 3 is not schedulable under RM. is not schedulable under RM. •This task set is This task set is schedulable under EDFschedulable under EDF as shown below. as shown below.

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EXAMPLEEXAMPLE: TASK SET UNSCHEDULABLE UNDER RM: TASK SET UNSCHEDULABLE UNDER RM• Non schedulable under RM… Non schedulable under RM… • Three periodic tasks are T1(1,3), T2(1,4), and T3(2,5), as shown if Figure 15.3. Three periodic tasks are T1(1,3), T2(1,4), and T3(2,5), as shown if Figure 15.3.

• The hyperperiod for The hyperperiod for Example Task Set 3, illustrated in Figure 15.3, is 60Example Task Set 3, illustrated in Figure 15.3, is 60,, and task and task utilization 1/3 + 1/4 + 1/5 = utilization 1/3 + 1/4 + 1/5 = 0.98330.9833. . Although the utilization is 98.33 per cent, Although the utilization is 98.33 per cent, which is less than 100 per cent, which is less than 100 per cent, this task set is not schedulable under RMthis task set is not schedulable under RM. .

• Tasks T1 and T2 take time intervals 0-1 and 1-2, and task T3 the time interval 2-3, Tasks T1 and T2 take time intervals 0-1 and 1-2, and task T3 the time interval 2-3, then T1 and T2 take again take time intervals 3-4 and 4-5, respectively. then T1 and T2 take again take time intervals 3-4 and 4-5, respectively.

• Now, T3, Now, T3, having executed for only 1 unit of timehaving executed for only 1 unit of time, , misses its deadline misses its deadline (it has to (it has to complete execution for 2 units of time before time 5) for the first period. complete execution for 2 units of time before time 5) for the first period. 245

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SCHEDULINGSCHEDULING3. Earliest-Deadline-First Scheduling Algorithm…3. Earliest-Deadline-First Scheduling Algorithm…•This task set is NOT schedulable under RM as shown below. This task set is NOT schedulable under RM as shown below.

•We shall now We shall now consider this task set with EDFconsider this task set with EDF..•At any point of time, At any point of time, EDF schedules the task with the EDF schedules the task with the earliest earliest deadlinedeadline. . •When two or more tasks have the same deadlineWhen two or more tasks have the same deadline, one task is chosen , one task is chosen randomly for scheduling. randomly for scheduling. •The hyperperiod (i.e., the LCM of 3, 4, and 5) for this example is 60. The hyperperiod (i.e., the LCM of 3, 4, and 5) for this example is 60. 246

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SCHEDULINGSCHEDULING3. Earliest-Deadline-First Scheduling Algorithm…3. Earliest-Deadline-First Scheduling Algorithm…•This task set is This task set is schedulable under EDF schedulable under EDF as shown below. as shown below.

•DeadlinesDeadlines: Each task must finish within its period (: Each task must finish within its period (last time unit must last time unit must start before next periodstart before next period).).•T1T1 has deadlines at has deadlines at 22 (3-1=2)(3-1=2), , 5, 85, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, , 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 41, 44, 47, 50, 53, 56, 5959 •T2T2 has deadlines at has deadlines at 33 (4-1=3)(4-1=3), , 7, 117, 11, 15, 19, 23, 27, 31, 35, 39, 15, 19, 23, 27, 31, 35, 39, , 43, 47, 43, 47, 51, 55, 51, 55, 5959 •T3T3 has deadlines at has deadlines at 44 (5-1=4)(5-1=4), , 9, 149, 14, 19, 24, 29, 34, , 19, 24, 29, 34, 39, 44, 49, 54, 39, 44, 49, 54, 5959 248

T1(1,3), T2(1,4), and T3(2,5)T1(1,3), T2(1,4), and T3(2,5)

SCHEDULINGSCHEDULING3. Earliest-Deadline-First Scheduling Algorithm…3. Earliest-Deadline-First Scheduling Algorithm…•This task set is schedulable under EDF as shown below. This task set is schedulable under EDF as shown below.

•T1T1 has deadlines at has deadlines at 22, , 5, 85, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, , 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 47, 50, 53, 56, 5959 •T2 has deadlines at T2 has deadlines at 3, 7, 113, 7, 11, 15, 19, 23, 27, 31, 35, , 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59 39, 43, 47, 51, 55, 59

•T3 has deadlines at T3 has deadlines at 4, 9, 144, 9, 14, 19, 24, 29, 34, 39, 44, 49, 54, 59 , 19, 24, 29, 34, 39, 44, 49, 54, 59 •We use the notation We use the notation S(S(TT,,tt,d,d) to denote a ) to denote a tasktask TT that is that is SScheduled at cheduled at timetime tt for the for the duration of d duration of d time units. time units. 249

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..Earliest-Deadline-First Scheduling Algorithm…Earliest-Deadline-First Scheduling Algorithm…•This task set is schedulable under EDF as shown below. This task set is schedulable under EDF as shown below.

•We use the notation We use the notation S(S(TT,t,,t,dd)) to denote a to denote a task Ttask T that is that is SScheduled cheduled atat time ttime t for the for the duration of d duration of d time units. time units.

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•T1T1 has deadlines at 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, has deadlines at 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 5959 •T2T2 has deadlines at 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, has deadlines at 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 43, 47, 51, 55, 5959 •T3T3 has deadlines at 4, 9, 14, 19, 24, 29, 34, 39, 44, 49, 54, has deadlines at 4, 9, 14, 19, 24, 29, 34, 39, 44, 49, 54, 5959

Deadline Deadline (DL)-2(DL)-2 3 4 5 7 8



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•T1T1 has deadlines at has deadlines at 2, 5, 8, 112, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, , 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 5959 •T2T2 has deadlines at has deadlines at 3, 7, 113, 7, 11, 15, 19, 23, 27, 31, 35, 39, , 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 43, 47, 51, 55, 5959 •T3T3 has deadlines at has deadlines at 4, 9, 144, 9, 14, 19, 24, 29, 34, 39, 44, 49, 54, , 19, 24, 29, 34, 39, 44, 49, 54, 5959

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•T1T1 has deadlines at has deadlines at 2, 5, 8, 112, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, , 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 5959 •T2T2 has deadlines at has deadlines at 3, 7, 113, 7, 11, 15, 19, 23, 27, 31, 35, 39, , 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 43, 47, 51, 55, 5959 •T3T3 has deadlines at has deadlines at 4, 9, 144, 9, 14, 19, 24, 29, 34, 39, 44, 49, 54, , 19, 24, 29, 34, 39, 44, 49, 54, 5959

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SCHEDULINGSCHEDULING3. Earliest-Deadline-First Scheduling Algorithm…3. Earliest-Deadline-First Scheduling Algorithm…•Consider Consider the the next example for further comparison next example for further comparison between RM and EDF.between RM and EDF.

•Two periodic tasks are Two periodic tasks are T1(1,3) and T2(3,5)T1(1,3) and T2(3,5). .

•According to RM, T1 has higher priority than T2. According to RM, T1 has higher priority than T2. •The The priorities change over time in EDFpriorities change over time in EDF. . •Processor Utilisation: Processor Utilisation: U = 1/3 + 3/5 = 14/15 < 1U = 1/3 + 3/5 = 14/15 < 1

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SCHEDULINGSCHEDULING3. Earliest-Deadline-First Scheduling Algorithm…3. Earliest-Deadline-First Scheduling Algorithm…•Consider Consider the the next example for further comparison next example for further comparison between RM and EDF.between RM and EDF.

•Two periodic tasks are Two periodic tasks are T1(1,3) and T2(3,5)T1(1,3) and T2(3,5). .

•In RM, the schedule would be: In RM, the schedule would be: S(T1,0,1), S(T2,1,2), S(T1,3,1), S(T2,4,1), S(T2,5,1), S(T1,6,1), S(T1,0,1), S(T2,1,2), S(T1,3,1), S(T2,4,1), S(T2,5,1), S(T1,6,1), S(T2,7,2), S(T1,9,1), S(T2,10,2), S(T1,12,1), S(T2,13,1), …S(T2,7,2), S(T1,9,1), S(T2,10,2), S(T1,12,1), S(T2,13,1), …

•In EDFIn EDF,, at time 0, the priority of T1 is higher than that of T2. The scheduler runs T1 at time 0, the priority of T1 is higher than that of T2. The scheduler runs T1 in interval 0-1, in interval 0-1, runs T2 in runs T2 in interval 1-3interval 1-3. At this point T1 comes back. . At this point T1 comes back. Since task T1 at Since task T1 at this time has a deadline (this time has a deadline (at time 6at time 6)) that is later than the deadline of task T2 ( that is later than the deadline of task T2 (at time at time 55), it would be more appropriate to continue T2.), it would be more appropriate to continue T2.

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Periodicity T1: 0,3,6,9,12,…Periodicity T1: 0,3,6,9,12,…Deadlines T1: 3,6,9,12,…Deadlines T1: 3,6,9,12,…PeriodicityPeriodicity T2: 0,5,10,15,…T2: 0,5,10,15,…Deadlines T2: 5,10,15,…Deadlines T2: 5,10,15,…

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S(S(TT,t,,t,dd)) to denote a to denote a task Ttask T that is that is SScheduled cheduled atat time time tt for the for the duration of d duration of d time units.time units.

SCHEDULINGSCHEDULING3. Earliest-Deadline-First Scheduling Algorithm…3. Earliest-Deadline-First Scheduling Algorithm…•In addition, this would reduce one preemption. In addition, this would reduce one preemption. •So the schedule for EDF would be: So the schedule for EDF would be:

•EDFEDF.. S(T1,0,1), S(T2,1,3), S(T1,4,1), S(T2,5,1), S(T1,6,1), S(T2,7,2), S(T1,0,1), S(T2,1,3), S(T1,4,1), S(T2,5,1), S(T1,6,1), S(T2,7,2), S(T1,9,1), S(T2,10,3), S(T1,13,1), … S(T1,9,1), S(T2,10,3), S(T1,13,1), … •The schedules are depicted in Figure 15.4, and we can see that the time The schedules are depicted in Figure 15.4, and we can see that the time interval interval 14-15 is free 14-15 is free and and the schedule will repeat itself starting from the schedule will repeat itself starting from time 15time 15, the beginning of the next hyperperiod. , the beginning of the next hyperperiod. 256

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Periodicity T1: 0,3,6,9,12,…Periodicity T1: 0,3,6,9,12,…Deadlines T1: 3,6,9,12,…Deadlines T1: 3,6,9,12,…PeriodicityPeriodicity T2: 0,5,10,15,…T2: 0,5,10,15,…Deadlines T2: 5,10,15,…Deadlines T2: 5,10,15,…

S(S(TT,t,,t,dd)) to denote a to denote a task Ttask T that is that is SScheduled cheduled atat time time tt for the for the duration of d duration of d time units.time units.

SCHEDULINGSCHEDULINGRM vs EDFRM vs EDF•Traditionally RM is considered favourable over EDF. Traditionally RM is considered favourable over EDF. •Recently, the validity of some of these Recently, the validity of some of these acclaimed attractive acclaimed attractive properties of RM properties of RM have been questioned.have been questioned.•In addition, In addition, it is observed it is observed that most of the advantages of RM over that most of the advantages of RM over EDF considered in literature are either very slim or incorrect when the EDF considered in literature are either very slim or incorrect when the algorithms are compared with respect to their development from algorithms are compared with respect to their development from scratch scratch rather than developing on the top of a generic priority based rather than developing on the top of a generic priority based kernelkernel. . •Some recent operating systems provide such support for the Some recent operating systems provide such support for the development of user level schedulers.development of user level schedulers.

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SCHEDULINGSCHEDULINGRM vs EDF… RM vs EDF… •One unattractive property of RM is One unattractive property of RM is that that it experiences a large number it experiences a large number of preemptions compared to EDF of preemptions compared to EDF and, therefore, introduces and, therefore, introduces high high overheadoverhead. The undesirable preemption-related overhead may cause . The undesirable preemption-related overhead may cause – higher processor overhead in real-time systems, higher processor overhead in real-time systems, – high energy consumption in embedded systems, and high energy consumption in embedded systems, and – may even make the task set unschedulable. may even make the task set unschedulable.

•In summaryIn summary, it is clear that , it is clear that – RM is simpler than EDF RM is simpler than EDF and and – RM experiences more preemptions than EDFRM experiences more preemptions than EDF. .

•Now, the question is Now, the question is how to reduce the pre-emptions without losing how to reduce the pre-emptions without losing the simplicity of RM. the simplicity of RM. •The next algorithm The next algorithm is directed towards answering this question. is directed towards answering this question.

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SCHEDULINGSCHEDULING4. Activation Adjusted Scheduling Algorithm. 4. Activation Adjusted Scheduling Algorithm. •Preemption of tasks occurs when Preemption of tasks occurs when a higher priority task is activated a higher priority task is activated during the execution of a lower priority taskduring the execution of a lower priority task. . •Consequently, Consequently, a lower priority task would experience more a lower priority task would experience more preemptionspreemptions as it stays longer in the ready queue. as it stays longer in the ready queue. •Therefore, to reduce preemptions, it is necessary to Therefore, to reduce preemptions, it is necessary to reduce the reduce the lifetime of lower priority taskslifetime of lower priority tasks waiting in the ready queue waiting in the ready queue. . •One way One way to reduce the lifetime of lower priority tasks, if possible, is to reduce the lifetime of lower priority tasks, if possible, is to delay the activation of higher priority tasksto delay the activation of higher priority tasks. This would increase the . This would increase the chance of lower priority tasks using the CPU as much as they can and chance of lower priority tasks using the CPU as much as they can and complete their executions quicker. complete their executions quicker. •The activation delays can be computed offline The activation delays can be computed offline similar to computing similar to computing worst case response time and incorporated in the periods worst case response time and incorporated in the periods to arrive at to arrive at the “adjusted-activation” timesthe “adjusted-activation” times. .

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SCHEDULINGSCHEDULING4. Activation Adjusted Scheduling Algorithm… 4. Activation Adjusted Scheduling Algorithm… •The actual computation of delay times is beyond the scope of this The actual computation of delay times is beyond the scope of this discussion. discussion. •Once the delays are computed offline Once the delays are computed offline and activation times are and activation times are adjusted, the remaining actions of the algorithm coincide with RM. adjusted, the remaining actions of the algorithm coincide with RM. •This is the objective of the activation-adjusted scheduling algorithm. This is the objective of the activation-adjusted scheduling algorithm. •We illustrate this idea using the following We illustrate this idea using the following exampleexample. . •ThreeThree periodic tasks are periodic tasks are T1(1,3), T2(3,9), and T3(2,12)T1(1,3), T2(3,9), and T3(2,12). . •According to RMAccording to RM, the priority order, from highest to lowest, is T1, T2, , the priority order, from highest to lowest, is T1, T2, and T3. and T3. •This task set has This task set has hyperperiod hyperperiod 36 (LCM of 3,9,12=36). 36 (LCM of 3,9,12=36).

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SCHEDULINGSCHEDULING4. Activation Adjusted Scheduling Algorithm… 4. Activation Adjusted Scheduling Algorithm… •The delay times computed for T1, T2 and T3 respectively are 2, 4, and The delay times computed for T1, T2 and T3 respectively are 2, 4, and 0 0 (Only Higher priority tasks are to be delayed for execution)(Only Higher priority tasks are to be delayed for execution). . •That is, That is, – task task T1 can be activated at T1 can be activated at time 2, 5, 8, 11, … instead of at times time 2, 5, 8, 11, … instead of at times

0, 3, 6, 9, …., 0, 3, 6, 9, …., (delayed by 2 time units)(delayed by 2 time units) and and – T2 can be activated at T2 can be activated at times 4, 13, 22, 31, ... instead of at times times 4, 13, 22, 31, ... instead of at times

0, 9, 18, 27,…0, 9, 18, 27,… (delayed by 4 time units) (delayed by 4 time units)

– There is no change in the activation time for task T3. There is no change in the activation time for task T3. •Changes in activation times reduce the number of preemptions. Changes in activation times reduce the number of preemptions. •We leave the analysis and computation of reduction in preemptions We leave the analysis and computation of reduction in preemptions for this example as an exercise. for this example as an exercise. •Next we look at some scheduling algorithm for the systems with non Next we look at some scheduling algorithm for the systems with non periodic tasks. periodic tasks.

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T1(1,3), T2(3,9), and T3(2,12).T1(1,3), T2(3,9), and T3(2,12).

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T1(1,3), T2(3,9), and T3(2,12)T1(1,3), T2(3,9), and T3(2,12)

Try Normal RMTry Normal RM•task task T1 is activated at T1 is activated at times 0, 3, 6, 9, …., times 0, 3, 6, 9, …., and and •T2 can be activated at T2 can be activated at times 1, 10, 19, 28, ... times 1, 10, 19, 28, ... •T3 can be activated at 5, 14, 25, …. T3 can be activated at 5, 14, 25, ….

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6 Preemptions6 Preemptions

ADJUST ACTIVATION (START TIME)ADJUST ACTIVATION (START TIME)

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• T2 can be activated at T2 can be activated at times 4, 13, 22, 31, ... instead of at times 0, 9, 18, 27,times 4, 13, 22, 31, ... instead of at times 0, 9, 18, 27,…… (delayed by 4 time units) (delayed by 4 time units)

• There is no change in the activation time for task T3: There is no change in the activation time for task T3: 0, 12, 24, 36, 0, 12, 24, 36, ….. …..

5 Preemptions5 Preemptions

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SCHEDULING APERIODIC AND SPORADIC TASKS SCHEDULING APERIODIC AND SPORADIC TASKS

Scheduling Aperiodic and Sporadic Tasks Scheduling Aperiodic and Sporadic Tasks •A A non-periodicnon-periodic task that is task that is either soft* either soft* or has no deadline or has no deadline is called an is called an aperiodic taskaperiodic task, and , and that which has a hard deadlinethat which has a hard deadline is called a is called a sporadic sporadic tasktask. . •These tasks are driven by These tasks are driven by asynchronous eventsasynchronous events. . •They They could be driven by could be driven by the environment in response to an external the environment in response to an external event — or because of internal change of the system state. event — or because of internal change of the system state. •For exampleFor example, ,

• an operator may want to read a specific value from the system an operator may want to read a specific value from the system or change to or change to manual drive for cruise (moving around slowly) control. manual drive for cruise (moving around slowly) control.

• Within the system Within the system an internal device might show some an internal device might show some fault state fault state requiring requiring operation mode change. operation mode change.

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• Hard real-time systems must satisfy their timing and deadline constraintsHard real-time systems must satisfy their timing and deadline constraints. . Otherwise, the system will fail. Otherwise, the system will fail.

• * On the other hand, * On the other hand, soft real-time systems can accept missing some deadline soft real-time systems can accept missing some deadline constraintsconstraints as long as they achieve their mission. as long as they achieve their mission.

SCHEDULING APERIODIC AND SPORADIC TASKS …SCHEDULING APERIODIC AND SPORADIC TASKS …

Scheduling Aperiodic and Sporadic Tasks… Scheduling Aperiodic and Sporadic Tasks… •Consider a system that has Consider a system that has periodicperiodic, , aperiodicaperiodic, and , and sporadicsporadic tasks. tasks. •The ready tasks The ready tasks of each class of each class are maintained are maintained in a separate queuein a separate queue. . •Assume that Assume that a periodic task scheduling algorithm a periodic task scheduling algorithm is employed to is employed to execute tasks execute tasks from the periodic task queuefrom the periodic task queue. . •We will see how aperiodic and sporadic tasks are executed in this We will see how aperiodic and sporadic tasks are executed in this environment. environment. •When a sporadic task becomes ready for executionWhen a sporadic task becomes ready for execution, it is tested to , it is tested to check whether the periodic tasks and other accepted sporadic tasks check whether the periodic tasks and other accepted sporadic tasks can be completed without missing their deadlines. can be completed without missing their deadlines. •If so the new sporadic task is acceptedIf so the new sporadic task is accepted. . OtherwiseOtherwise, it is rejected , it is rejected immediately. immediately.

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SCHEDULINGSCHEDULING

Scheduling Aperiodic and Sporadic Tasks… Scheduling Aperiodic and Sporadic Tasks… •Now the issue is how to schedule Now the issue is how to schedule the accepted sporadic tasksthe accepted sporadic tasks. . •One of the simplest approaches One of the simplest approaches to schedule the accepted sporadic tasks to schedule the accepted sporadic tasks is as follows. is as follows. •Transform the Transform the accepted sporadic tasks accepted sporadic tasks for the scheduling purpose at for the scheduling purpose at that instancethat instance and and thenthen adapt the scheduler of the periodic tasks adapt the scheduler of the periodic tasks to to schedule these temporary periodic tasks along with regular periodic schedule these temporary periodic tasks along with regular periodic tasks. tasks. •Since aperiodic tasks can tolerate delayed executionSince aperiodic tasks can tolerate delayed execution, , they need not be they need not be rejected right awayrejected right away. . •The scheduler tries to complete the aperiodic tasks as soon as possible The scheduler tries to complete the aperiodic tasks as soon as possible without missing any deadline of the accepted sporadic- and periodic without missing any deadline of the accepted sporadic- and periodic tasks. tasks. •There are There are many ways many ways this can be achieved. this can be achieved. Some are discussed in next Some are discussed in next two subsectionstwo subsections.. 268

SCHEDULINGSCHEDULINGScheduling Aperiodic and Sporadic Tasks…Scheduling Aperiodic and Sporadic Tasks…

1. Background Approach. 1. Background Approach. •This is the simplest approach in that This is the simplest approach in that it allows aperiodic tasks to run it allows aperiodic tasks to run only when periodic and sporadic task queues are emptyonly when periodic and sporadic task queues are empty. . •This approach produces the appropriate schedule, This approach produces the appropriate schedule, but the response but the response of aperiodic tasks may suffer unnecessary delayof aperiodic tasks may suffer unnecessary delay. . •Consider that RM is used for scheduling periodic tasksConsider that RM is used for scheduling periodic tasks. . An aperiodic An aperiodic task T’ arrives task T’ arrives for execution at time 96 which requires 3 units of for execution at time 96 which requires 3 units of execution time. execution time. •At that moment there are At that moment there are twotwo periodic tasks periodic tasks T1(5,12) and T2(6,16) T1(5,12) and T2(6,16) that become ready for execution. that become ready for execution. •The background approach The background approach will schedule T’ at time 107 (96+5+6=107) will schedule T’ at time 107 (96+5+6=107) after both T1 and T2 complete their executions. after both T1 and T2 complete their executions.

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BACKGROUND APPROACHBACKGROUND APPROACH• There are TwoThere are Two periodic tasks periodic tasks T1(5,12) and T2(6,16) that T1(5,12) and T2(6,16) that

become ready for execution at time 96. become ready for execution at time 96. • T’ arrives T’ arrives for execution at time 96 which requires for execution at time 96 which requires 3 units of 3 units of

execution time.execution time.• The background approach The background approach will schedule T’ at time 107 will schedule T’ at time 107

((96+5+6=10796+5+6=107) after both T1 and T2 complete their ) after both T1 and T2 complete their executions. executions.

• Hyperperiod = LCM of 12 and 16 = 48Hyperperiod = LCM of 12 and 16 = 48

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• 96+12 = 108. T1 can be delayed upto 108-5=103 or 96+16=112, T2 can be delayed upto 96+12 = 108. T1 can be delayed upto 108-5=103 or 96+16=112, T2 can be delayed upto 112-6=106.112-6=106.

• T’ can be started at 96 without causing any delay.T’ can be started at 96 without causing any delay.


1. Background Approach… 1. Background Approach… •Instead, T’ can be executed immediately at time 96 Instead, T’ can be executed immediately at time 96 leaving enough leaving enough time for T1 and T2 to meet their deadlines. time for T1 and T2 to meet their deadlines. •This would reduce the response time for T’ without causing any This would reduce the response time for T’ without causing any deadline miss. deadline miss. •Between T1 and T2, RM will schedule T1 first. Between T1 and T2, RM will schedule T1 first. •So T2 can be delayed for a maximum of 10 units (that is, until at time So T2 can be delayed for a maximum of 10 units (that is, until at time 106) so that it can run between 106 and 112 to meet the deadline 112. 106) so that it can run between 106 and 112 to meet the deadline 112. •In such a case, T1 can be delayed for 5 units In such a case, T1 can be delayed for 5 units (that is, until at time 101) (that is, until at time 101) so that it can run between 101 and 106, meeting the deadline 108. so that it can run between 101 and 106, meeting the deadline 108.

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1. Background Approach… 1. Background Approach… •In the above exampleIn the above example, , tasks T1 and T2 can be delayed at least for 5 tasks T1 and T2 can be delayed at least for 5 units of time units of time without causing a deadline miss. without causing a deadline miss. •The interval that each task can be delayed without causing deadline The interval that each task can be delayed without causing deadline miss is called the “miss is called the “slack timeslack time”. ”. •Slack time computation grows more involved as the number of tasks Slack time computation grows more involved as the number of tasks increases. increases. •The algorithm which uses slack time The algorithm which uses slack time to delay periodic- and sporadic to delay periodic- and sporadic tasks tasks and execute aperiodic tasks to shorten the response time is and execute aperiodic tasks to shorten the response time is called called slack-stealing algorithmslack-stealing algorithm. .

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2. Polling Approach. 2. Polling Approach. •In this approach, a new task called In this approach, a new task called periodic server periodic server with with period p and period p and execution time e execution time e is created for the purpose of executing aperiodic is created for the purpose of executing aperiodic tasks. tasks. •The periodic server behaves very The periodic server behaves very similar to a periodic task similar to a periodic task for for scheduling purposesscheduling purposes but is used only to execute but is used only to execute aperiodicaperiodic tasks tasks. . •The simplest version of periodic server called “poller” or “polling The simplest version of periodic server called “poller” or “polling server” server” is invoked periodically is invoked periodically to check (i.e., poll) to check (i.e., poll) the aperiodic task the aperiodic task queuequeue. . •If the queue is emptyIf the queue is empty, the polling server suspends itself immediately , the polling server suspends itself immediately and waits until the next polling period starts. and waits until the next polling period starts. Otherwise, it executes Otherwise, it executes aperiodic tasks for aperiodic tasks for e e time units time units or until the aperiodic task queue or until the aperiodic task queue becomes empty, becomes empty, whichever occurs sooner.whichever occurs sooner.

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2. Polling Approach… 2. Polling Approach… •Here Here ee is called the is called the eexecution budget of the server and, for the polling xecution budget of the server and, for the polling server, it is a fixed value. That is, it gets the same budget for every server, it is a fixed value. That is, it gets the same budget for every polling period. The budget is the CPU time given to the periodic server polling period. The budget is the CPU time given to the periodic server to execute aperiodic tasks. to execute aperiodic tasks. •Based on the manner the budget value is changed—that is, consumed Based on the manner the budget value is changed—that is, consumed and replenished—different periodic servers can be constructed. and replenished—different periodic servers can be constructed. •In the case of the polling server, the budget is replenished at the In the case of the polling server, the budget is replenished at the beginning of each polling period and is consumed for executing beginning of each polling period and is consumed for executing aperiodic tasks. aperiodic tasks. •The The unused budget is reset to 0 unused budget is reset to 0 when the aperiodic task queue when the aperiodic task queue becomes empty. becomes empty.

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2. Polling Approach… 2. Polling Approach… •Consider a typical example of the polling server that has budget 10 Consider a typical example of the polling server that has budget 10 when it starts its execution and finds the aperiodic task is empty. Now, when it starts its execution and finds the aperiodic task is empty. Now, the budget is reset to 0 and its execution is suspended immediately. the budget is reset to 0 and its execution is suspended immediately. •Assume that, at this momentAssume that, at this moment, an aperiodic task with execution , an aperiodic task with execution requirement requirement 2 time units 2 time units arrives at the aperiodic task queue. arrives at the aperiodic task queue. •It has to wait for the next polling period It has to wait for the next polling period and that will increase its and that will increase its response time. response time. •The response time of aperiodic tasks could be shortened if the budget The response time of aperiodic tasks could be shortened if the budget is preserved when the queue is empty and the periodic server allowed is preserved when the queue is empty and the periodic server allowed to execute later in the period if any aperiodic task arrives. The to execute later in the period if any aperiodic task arrives. The algorithm with this approach is called budget-preserving or algorithm with this approach is called budget-preserving or bandwidth-preserving server. bandwidth-preserving server.

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VariationsVariations •The main components of periodic servers are the budget The main components of periodic servers are the budget consumption- and budget replenishment rules. consumption- and budget replenishment rules. •We list some basic consumption and replenishment rules. We list some basic consumption and replenishment rules. • Replenishment Rules: Replenishment Rules:

• R1: The execution budget of the server is set to R1: The execution budget of the server is set to ee at the beginning of at the beginning of each period. each period.

• Consumption Rules: Consumption Rules: • C1: The budget is consumed at the rate of one per unit time when time C1: The budget is consumed at the rate of one per unit time when time

server executes. The budget is reset to 0 when it suspends itself. server executes. The budget is reset to 0 when it suspends itself. • C2: The budget is consumed at the rate of one per unit time when the C2: The budget is consumed at the rate of one per unit time when the

server executes. server executes.

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VariationsVariations … …•The polling server uses R1 and C1. The polling server uses R1 and C1. •The periodic server based on rules R1 and C2 is called The periodic server based on rules R1 and C2 is called deferrabledeferrable serverserver. . •The difference is that in deferrable servers the The difference is that in deferrable servers the unconsumed budget is unconsumed budget is preserved until the end of the periodpreserved until the end of the period. . •Recall the previous example given for polling server. Recall the previous example given for polling server. •The periodic server is invoked when the new aperiodic task arrives The periodic server is invoked when the new aperiodic task arrives and it then executes the aperiodic task.and it then executes the aperiodic task.•This might delay lower priority periodic tasks for longer than usualThis might delay lower priority periodic tasks for longer than usual. . •A new class of algorithms called A new class of algorithms called sporadic servers sporadic servers solves this problem solves this problem by ensuring that each sporadic server with period p and budget e by ensuring that each sporadic server with period p and budget e never demands more processor time than a periodic task with the never demands more processor time than a periodic task with the same period and execution time in any time interval. same period and execution time in any time interval. 279


VariationsVariations … …•This is achieved by suitable consumption and replenishment rules. This is achieved by suitable consumption and replenishment rules. •The discussion of sporadic servers is beyond our. The discussion of sporadic servers is beyond our. •There are many variations to the deferrable serverThere are many variations to the deferrable server. . •One interesting variation is combining background approach with it. One interesting variation is combining background approach with it. That is, That is, allow the deferrable server to execute aperiodic tasks when the allow the deferrable server to execute aperiodic tasks when the periodic task queue is emptyperiodic task queue is empty. . •Such servers are called background serversSuch servers are called background servers. . •Another variation Another variation is lowering its priority when it suspends its execution is lowering its priority when it suspends its execution before the budget is exhaustedbefore the budget is exhausted. . •When aperiodic task is ready to use its budget, When aperiodic task is ready to use its budget, it exchanges its priority it exchanges its priority with a lower priority taskwith a lower priority task. In that case, the priority of the server is . In that case, the priority of the server is lowered but maintains its remaining budget. lowered but maintains its remaining budget. •This algorithm is called priority exchange algorithmThis algorithm is called priority exchange algorithm. .

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VariationsVariations … …•So far we have addressed the scheduling issues among the tasks with So far we have addressed the scheduling issues among the tasks with different priorities. different priorities. •The immediate question relates to the tasks of same priority. The immediate question relates to the tasks of same priority. •For such cases, most real-time systems use either the round robin For such cases, most real-time systems use either the round robin (RR) scheduling or the FIFO scheduling strategy(RR) scheduling or the FIFO scheduling strategy. . •The main objective of the above scheduling algorithms is meeting The main objective of the above scheduling algorithms is meeting deadlines. deadlines. •As embedded devices are becoming increasingly common, As embedded devices are becoming increasingly common, battery life battery life is considered a crucial factor and task scheduling indeed plays is considered a crucial factor and task scheduling indeed plays important role in battery lifeimportant role in battery life. . •Next, we will briefly look at energy saving aspects of CPU scheduling. Next, we will briefly look at energy saving aspects of CPU scheduling.

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•>> >> •Real-time POSIX compliant operating systems must support fixed Real-time POSIX compliant operating systems must support fixed priority scheduling with at least 32 priority levels. priority scheduling with at least 32 priority levels. •It can choose either RR or FIFO for scheduling within the same It can choose either RR or FIFO for scheduling within the same priority level. priority level. •In addition, some tasks may be scheduled according to FIFO while In addition, some tasks may be scheduled according to FIFO while others are scheduled using RR. others are scheduled using RR. •In principle, it can support EDF and other dynamic priority algorithms. In principle, it can support EDF and other dynamic priority algorithms.

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– Scheduling:Scheduling:• Periodic, Periodic, • Aperiodic Aperiodic

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– Scheduling:Scheduling:• Periodic, Periodic, • Aperiodic Aperiodic and and • Sporadic Tasks, Sporadic Tasks,

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– Scheduling:Scheduling:• Periodic, Periodic, • Aperiodic Aperiodic and and • Sporadic Tasks, Sporadic Tasks,

– Introduction to Energy Aware CPU Scheduling.Introduction to Energy Aware CPU Scheduling.287

ENERGY AWARE CPU SCHEDULINGENERGY AWARE CPU SCHEDULINGEnergy Aware CPU SchedulingEnergy Aware CPU Scheduling•With the extensive use of portable, battery-powered devices such as With the extensive use of portable, battery-powered devices such as PDAs, mobile phones, camcorders, PDAs everywhere (that is, in PDAs, mobile phones, camcorders, PDAs everywhere (that is, in homes, offices, cars, factories, hospitals, aeroplanes, etc.), minimizing homes, offices, cars, factories, hospitals, aeroplanes, etc.), minimizing power/energy consumption in these devices is becoming increasingly power/energy consumption in these devices is becoming increasingly important. important. •Power consumption is broadly classified into Power consumption is broadly classified into staticstatic and and dynamicdynamic consumption types. consumption types. •Static power consumption Static power consumption occurs due to standby- and leakage occurs due to standby- and leakage currents, and currents, and dynamic power consumption dynamic power consumption due to switching- or due to switching- or operational activities in the device. operational activities in the device. •Since static power consumption increases when the device is Since static power consumption increases when the device is operated below a critical power level, such increases can be avoided operated below a critical power level, such increases can be avoided by always operating the device above the critical power level. by always operating the device above the critical power level.

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•Hence, at the operating level, power reduction strategies mainly refer Hence, at the operating level, power reduction strategies mainly refer to reduction in dynamic power consumption to reduction in dynamic power consumption by using suitable by using suitable processor scheduling algorithms.processor scheduling algorithms. •Recent technologies allow the CPU to operate in a range of voltage Recent technologies allow the CPU to operate in a range of voltage supply. supply. •In these systems, processor energy consumption can be reduced by In these systems, processor energy consumption can be reduced by reducing CPU voltage. reducing CPU voltage. •However, such reduction in power necessitates the processor to run However, such reduction in power necessitates the processor to run at a slower speed. at a slower speed. •The techniques The techniques mainly employed by task-scheduling algorithms to mainly employed by task-scheduling algorithms to reduce dynamic power consumption are reduce dynamic power consumption are processor processor shutshutdown down and and processor processor slowslowdowndown. .

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•Thus, Thus, the crux of designing an energy-efficient scheduling strategy the crux of designing an energy-efficient scheduling strategy is is to decide when to apply shutdown and slowdown and for how long. to decide when to apply shutdown and slowdown and for how long. •Shutting down the system and later waking up the processor Shutting down the system and later waking up the processor consumes considerable power. consumes considerable power. •Therefore, shutdown is applied only when the processor is idle for a Therefore, shutdown is applied only when the processor is idle for a period longer than a threshold value, which varies from system to period longer than a threshold value, which varies from system to system. system. •Slowdown involves many factorsSlowdown involves many factors and, therefore, depends on the and, therefore, depends on the effectiveness of the estimation of slowdown based on these factors. effectiveness of the estimation of slowdown based on these factors. •Another way to save energy Another way to save energy is to is to avoid or reduce preemptions avoid or reduce preemptions whenever possible. whenever possible. •Task preemption is an energy expensive activity. Task preemption is an energy expensive activity.

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•Task preemption is an energy expensive activity. Task preemption is an energy expensive activity. •Preemption introduces an immediate context switch and that Preemption introduces an immediate context switch and that consumes energy. consumes energy. •Context switch cost is significantly high if the system uses multiple Context switch cost is significantly high if the system uses multiple cache memories. cache memories. •A scheduling policy has greater influence on the lifetime of tasks in A scheduling policy has greater influence on the lifetime of tasks in the system. the system. •An increased lifetime of a task An increased lifetime of a task has direct impact on the number of has direct impact on the number of preemptions. preemptions. •Also, since all the necessary resources are generally active during the Also, since all the necessary resources are generally active during the lifetime of a task, lifetime of a task, the increased lifetime of the task leads to increased the increased lifetime of the task leads to increased energy consumptionenergy consumption in the overall system. in the overall system.

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•Hence, Hence, reducing the number of preemptions and average lifetime of reducing the number of preemptions and average lifetime of tasks would significantly reduce the energy consumption tasks would significantly reduce the energy consumption in the overall in the overall system. system. •The primary objective in this context is to reduce these two energy-The primary objective in this context is to reduce these two energy-expensive activities considerably to save energy. expensive activities considerably to save energy. •Accelerated-completion and delayed-preemption Accelerated-completion and delayed-preemption are two are two preemption control techniques. preemption control techniques. •The accelerated-completion technique tries to avoid preemptions by The accelerated-completion technique tries to avoid preemptions by adjusting the voltage/clock speed to higher than the lowest possible adjusting the voltage/clock speed to higher than the lowest possible values. values. •The limitation in this algorithm is that it requires knowledge of the The limitation in this algorithm is that it requires knowledge of the task execution profile. task execution profile.

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•The delayed-preemption technique The delayed-preemption technique tries to avoid preemptions tries to avoid preemptions byby delaying higher-priority tasks delaying higher-priority tasks if a lower priority task is currently if a lower priority task is currently running. running. •This requires computing the slack and voltage/clock speed of the This requires computing the slack and voltage/clock speed of the interrupting task at each preemption point, which increases the interrupting task at each preemption point, which increases the scheduler complexity and running time overhead. scheduler complexity and running time overhead.

•>> Although a context switch takes only a few microseconds, the >> Although a context switch takes only a few microseconds, the effective time- and energy overhead of a context switch is generally effective time- and energy overhead of a context switch is generally high due to activities such as cache management, Translation Look-high due to activities such as cache management, Translation Look-aside Buffers management, etc.aside Buffers management, etc.

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•Many energy savings techniques for fixed priority scheduling have Many energy savings techniques for fixed priority scheduling have been studied recently. been studied recently. •They all essentially involve dynamically changing the speed of the They all essentially involve dynamically changing the speed of the processor by varying the clock frequency with the supply voltage. processor by varying the clock frequency with the supply voltage. •This is called dynamic voltage scaling techniqueThis is called dynamic voltage scaling technique. . •By changing the speed of the processorBy changing the speed of the processor, the execution times of the , the execution times of the tasks can be increased or decreased. tasks can be increased or decreased. •Decreasing speed has the danger of missing deadlines. Decreasing speed has the danger of missing deadlines. •Therefore, dynamic voltage scaling has to be incorporated Therefore, dynamic voltage scaling has to be incorporated into the into the scheduling algorithm carefully without violating the timing constraints scheduling algorithm carefully without violating the timing constraints of the applications. of the applications. •The aim is to adjust the voltage or to perform a shutdown based on The aim is to adjust the voltage or to perform a shutdown based on the current state. the current state.

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•The simplest algorithm for the static priority is as follows. The simplest algorithm for the static priority is as follows. •If the ready queue is emptyIf the ready queue is empty and and the upcoming idle time is greater the upcoming idle time is greater than the threshold valuethan the threshold value, then enter the processor into the shutdown , then enter the processor into the shutdown mode. mode. •A higher level description of an algorithm called A higher level description of an algorithm called low-energylow-energy earliest earliest deadline first deadline first (LEDF) for EDF, which uses the basic voltage scaling (LEDF) for EDF, which uses the basic voltage scaling technique, is given next. technique, is given next.

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…LEDF() LEDF() { { while (ready queue is not empty) while (ready queue is not empty) { Sort deadlines in ascending order; { Sort deadlines in ascending order; Schedule task with earliest deadline; Schedule task with earliest deadline; If deadline can be met with lower speed, schedule at that speed; If deadline can be met with lower speed, schedule at that speed; If deadline can be met only with higher speed, schedule at that speed;If deadline can be met only with higher speed, schedule at that speed; } } } }

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Energy Aware CPU Scheduling…Energy Aware CPU Scheduling…•In summary, the following techniques are used to design energy-In summary, the following techniques are used to design energy-efficient scheduling algorithms: efficient scheduling algorithms:

1.1. operate the processor above critical speed; operate the processor above critical speed; 2.2. slow down processor speed whenever idle time is expected slow down processor speed whenever idle time is expected

due to early completion of the task; due to early completion of the task; 3.3. shutdown the processor for a sufficient period; shutdown the processor for a sufficient period; 4.4. avoid preemption whenever possible. avoid preemption whenever possible.

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STRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMSSTRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMS• >> Suppose a task A is responsible for updating the values of wheel- and wind >> Suppose a task A is responsible for updating the values of wheel- and wind

• 15.7 Task Synchronization We have seen that the CPU is a resource shared by many tasks, but one 1 1 time. Like the CPU, there are many other resources in the system that ha‘-e D1 15.7 Task Synchronization We have seen that the CPU is a resource shared by many tasks, but one 1 1 time. Like the CPU, there are many other resources in the system that ha‘-e D1 be shared over time. However, unlike the CPU, some of these resotrzzs cannot be taken away from a task at any arbitrary time. In real-time systems, any actions based on be shared over time. However, unlike the CPU, some of these resotrzzs cannot be taken away from a task at any arbitrary time. In real-time systems, any actions based on inconsistent values are if unacceptable. In this example, F is a shared resource that has to be accev P-429 In real-time systems, any actions based on inconsistent values are often inconsistent values are if unacceptable. In this example, F is a shared resource that has to be accev P-429 In real-time systems, any actions based on inconsistent values are often unacceptable. In this example, F is a shared resource that has to be accessed exclusively. How to share such exclusive resources among many competing tasks is a task unacceptable. In this example, F is a shared resource that has to be accessed exclusively. How to share such exclusive resources among many competing tasks is a task synchronization problem. Many synchronization problems and their solutions for general systems are discussed in Chapter 7. In this section, we focus on only one synchronization synchronization problem. Many synchronization problems and their solutions for general systems are discussed in Chapter 7. In this section, we focus on only one synchronization problem called the mutual exclusion problem and its related issues in real-time systems. Given a set of tasks and a resource, the mutual exclusion problem is that, at any given time, problem called the mutual exclusion problem and its related issues in real-time systems. Given a set of tasks and a resource, the mutual exclusion problem is that, at any given time, at the most one task can use the resource. The problem may be viewed as a kind of resource allocation problem, but its solutions differ from CPU scheduling algorithms due to the at the most one task can use the resource. The problem may be viewed as a kind of resource allocation problem, but its solutions differ from CPU scheduling algorithms due to the requirement of exclusive access to the resource. Since RE systems are highly concurrent, tasks often compete for shared resources and, therefore, mutual exclusion is an important requirement of exclusive access to the resource. Since RE systems are highly concurrent, tasks often compete for shared resources and, therefore, mutual exclusion is an important issue. Again, we will not repeat solutions to the mutual exclusion problem discussed in Chapter 7. Instead, we focus on the compositional effect of the solutions for two important issue. Again, we will not repeat solutions to the mutual exclusion problem discussed in Chapter 7. Instead, we focus on the compositional effect of the solutions for two important problems in the real-time context: CPU scheduling and mutual exclusion. Consider a simple case where three periodic tasks T1, T2, and T3 with respective priorities pl, p2, and p3 (pl problems in the real-time context: CPU scheduling and mutual exclusion. Consider a simple case where three periodic tasks T1, T2, and T3 with respective priorities pl, p2, and p3 (pl < p2 < p3) need exclusive access to a shared resource R. Now we have two problems to be solved for Tl, T2, and T3: (1) CPU scheduling and (2) mutual exclusion of R. We know that < p2 < p3) need exclusive access to a shared resource R. Now we have two problems to be solved for Tl, T2, and T3: (1) CPU scheduling and (2) mutual exclusion of R. We know that many solutions are available for these two problems separately. Assume that the problems are solved separately using suitable algorithms. In priority scheduling, the ready task many solutions are available for these two problems separately. Assume that the problems are solved separately using suitable algorithms. In priority scheduling, the ready task with the highest priority uses the CPU at any time. For mutual exclusion, tasks compete for R. The solution will let one task succeed in the competition and use R. The other tasks with the highest priority uses the CPU at any time. For mutual exclusion, tasks compete for R. The solution will let one task succeed in the competition and use R. The other tasks have to wait until the holder task releases R. When we analyse these two solutions independently, they seem to work well. However, the techniques are not compositional. That is, have to wait until the holder task releases R. When we analyse these two solutions independently, they seem to work well. However, the techniques are not compositional. That is, they need not work well when both are combined, as explained next. Task Tl is using the shared resource R. The mutual exclusion algorithm will not allow T2 and T3 to use R until Tl they need not work well when both are combined, as explained next. Task Tl is using the shared resource R. The mutual exclusion algorithm will not allow T2 and T3 to use R until Tl releases it. Now, T3 becomes ready for execution, the scheduling algorithm preempts Tl and allows T3 to run. Now, T3 wants to use R. Since Tl has exclusive access to R, T3 has to releases it. Now, T3 becomes ready for execution, the scheduling algorithm preempts Tl and allows T3 to run. Now, T3 wants to use R. Since Tl has exclusive access to R, T3 has to wait until Tl releases R. Two cases are possible now: l. If the mutual exclusion algorithm involves busy-waiting, then T3 holds the CPU (by busy-waiting for R) and Tl is waiting for the wait until Tl releases R. Two cases are possible now: l. If the mutual exclusion algorithm involves busy-waiting, then T3 holds the CPU (by busy-waiting for R) and Tl is waiting for the CPU to use R. This is a deadlock situation between Tl and T3. 2. If the mutual exclusion algorithm does not involve busy-waiting, then T3 must release the CPU and wait for Tl to CPU to use R. This is a deadlock situation between Tl and T3. 2. If the mutual exclusion algorithm does not involve busy-waiting, then T3 must release the CPU and wait for Tl to release R. Now, T2 becomes ready, and gets the CPU by priority scheduling algorithm. Now, the waiting time of T3 depends not only on the execution time of Tl but also on the release R. Now, T2 becomes ready, and gets the CPU by priority scheduling algorithm. Now, the waiting time of T3 depends not only on the execution time of Tl but also on the execution times of tasks with priorities between pl and p3. In either case, this scenario violates the spirit of priority scheduling and may lead to deadline misses and their execution times of tasks with priorities between pl and p3. In either case, this scenario violates the spirit of priority scheduling and may lead to deadline misses and their consequences. P-430 consequences. P-430

• >> Efficient implementation of accesses to shared resources is extremely imponant in real- time context to alleviate priority inversion problems. Problems arise when a low priority >> Efficient implementation of accesses to shared resources is extremely imponant in real- time context to alleviate priority inversion problems. Problems arise when a low priority task prevents a high priority I85: from executing. These problems are called priority iziiwsion problems. The cost of such problems is enormous in real-time systems and it is best task prevents a high priority I85: from executing. These problems are called priority iziiwsion problems. The cost of such problems is enormous in real-time systems and it is best illustrated by the following real-world example. Priority Inversion in Mars Probe Pathfinder: Pathfinder used at “information bus” as a shared resource to pass information among illustrated by the following real-world example. Priority Inversion in Mars Probe Pathfinder: Pathfinder used at “information bus” as a shared resource to pass information among differeri components of the spacecraft. A high-priority bus-management task (BMT ran frequently to move data in and out of the bus. A meteorological data- gathering task (MDT), differeri components of the spacecraft. A high-priority bus-management task (BMT ran frequently to move data in and out of the bus. A meteorological data- gathering task (MDT), with low priority, ran infrequently to publish its data cf the bus. The system used priority-based CPU scheduling and semaphore-base; non-busy-wait mutual exclusion algorithm to with low priority, ran infrequently to publish its data cf the bus. The system used priority-based CPU scheduling and semaphore-base; non-busy-wait mutual exclusion algorithm to ensure mutually exclusive acces~ to the information bus. As a corrective measure. a watchdog timer was used ta reset the entire system, if BMT could not execute for some reason. ensure mutually exclusive acces~ to the information bus. As a corrective measure. a watchdog timer was used ta reset the entire system, if BMT could not execute for some reason. On 4 July 1997, after a seven-month voyage, the spacecraft landed or Mars. A few days into the mission. the spacecraft began experiencing systerr resets. The following is what On 4 July 1997, after a seven-month voyage, the spacecraft landed or Mars. A few days into the mission. the spacecraft began experiencing systerr resets. The following is what caused the resets. The low-priority MDT acquire; exclusive access to the information bus for writing its data onto it, and the high- priority BMT. started later, noticed that MDT has caused the resets. The low-priority MDT acquire; exclusive access to the information bus for writing its data onto it, and the high- priority BMT. started later, noticed that MDT has the control of the bus an; hence blocked itself. At that time. a medium-priority long-running comm1.- nication task started its execution and preempted MDT to acquire the CPL' the control of the bus an; hence blocked itself. At that time. a medium-priority long-running comm1.- nication task started its execution and preempted MDT to acquire the CPL' Now, MDT was waiting for the CPU and BMT was waiting for MDT. After _ time interval, the watchdog timer went off initiating total system reset. The combination worked fine for Now, MDT was waiting for the CPU and BMT was waiting for MDT. After _ time interval, the watchdog timer went off initiating total system reset. The combination worked fine for most of the time and rarely encountere; any problem during ground testing as. in the design. the possibility for ; medium-priority task to start its execution in the short interval most of the time and rarely encountere; any problem during ground testing as. in the design. the possibility for ; medium-priority task to start its execution in the short interval where BMT ts waiting for MDT was very low. After noticing the problem in Pathfinder of. Mars. the original simulator in the NASA lab was run to reproduce the failure It did so within where BMT ts waiting for MDT was very low. After noticing the problem in Pathfinder of. Mars. the original simulator in the NASA lab was run to reproduce the failure It did so within 18 hours. Once they noticed the failure in the simulator, the} analyzed the execution trace and identified the priority-inversion pX'Obl6lT. Fortunately. the system was implemented 18 hours. Once they noticed the failure in the simulator, the} analyzed the execution trace and identified the priority-inversion pX'Obl6lT. Fortunately. the system was implemented with a solution to priority-inversior. problems. However. they had an option to enable or disable it. Initially it had been disabled by setting a condition flag to FALSE. Once they with a solution to priority-inversior. problems. However. they had an option to enable or disable it. Initially it had been disabled by setting a condition flag to FALSE. Once they noticed the priority-inversion problem. it was enabled by setting the condition flag tr TRUE. After that the problem was solved. no further resets occurred. Next we discuss the noticed the priority-inversion problem. it was enabled by setting the condition flag tr TRUE. After that the problem was solved. no further resets occurred. Next we discuss the solutions to priority-inversion problem. solutions to priority-inversion problem.

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• 15.7.1 Resource Sharing and Priority Inversion Problem The solution to priority inversion problems is to collectively deal with CPL‘ scheduling and resource scheduling. The simplest solution to the priorit§ inversion problem is to disable interrupts during the access to a shared resource. That is, CPU scheduling is disabled when a shared resource is allocated. This solution has not been generally supported for obvious reasons. The next simplest solution is by Mok (proposed in his PhD thesis in 1983) called non-preenzprive critical section (NPCS) protocol. The idea is P-431

• >> Although several people claimed the invention of priority inversion problem, the problem was clearly defined by Lampson and Redell in 1980. that when a task gets a shared resource its priority is raised to the highest level (highest priority of all tasks in the system). The advantage of NPCS protocol is its simplicity, as it does not require the knowledge of the number of resources and requirements of resources of the tasks. The obvious dis- advantage is that it blocks all other tasks even if they do not compete for a resource. If the resource requirements of all tasks are known, then the problem can be solved by a simple modification: the resource holding task executes at the highest priority of all tasks requiring that resource. This is referred as ceiling-priority (CP) protocol. Another solution proposed by Lampson and Redell in 1980 was similar to the CP protocol, but this one is based on the monitor. A monitor can be designed to synchronize access to one or more shared resources. Each monitor is assigned with the priority of the highest priority task that enters the monitor. When a task enters the monitor, its priority is temporarily increased to that of the monitor. We refer it as MB-CP protocol. Sha et al. proposed a protocol called priority inheritance (PI) protocol, which works as follows: A resource is assigned to a task only when the resource is free. Requests to a resource are denied when it is not free, and the requesting tasks are blocked. Assume that a task A is currently using a resource R. Another task B requests R and is blocked. If the priority of B is higher than the current priority of A, then A “inherits” the priority of B and continues to use R. When R is released, the priority of A is reset to its original priority. PI protocol does not prevent deadlocks. Consider that a task A1 holds a shared resource RI and requests another shared resource R2 that another task A2 holds. Consequently. A1 is blocked. Now A2 requests R1 that A1 already holds. Hence there is a deadlock. To prevent deadlocks, Sha et al. proposed another protocol called priority ceiling (PC). It is a variation of CP. The priority ceiling of a resource is defined as the highest priority of tasks that may use that resource. That is, the priority ceiling of each resource is known in advance. A task is allowed to access a new resource only if the task priority is higher than or equal to the priority ceilings of all the resources currently in use. Otherwise, the task is blocked. When a task A gets access to a resource R, it inherits the priority ceiling of R until it releases R. When R is released, priority of A is reset to its original priority. To see how this protocol prevents deadlocks in the above example, assume that A2 has higher priority than AI . By PC protocol, R] and R2 have priority ceiling equal to the priority of A2. Assume that Al first acquires R I . Then, if AI is trying to acquire R2, the request will be denied because its priority is lower than the priority ceiling of R2. The deadlock is prevented. In summary. all these protocols involve increasing the priority of tasks during their accesses to shared resources. The variation lies in when to increase priority and to what value. Assume that a task A gets a shared resource R. Except for PI, A‘s priority is increased to the priority ceiling when A acquires R. The difference lies in the Away the priority ceiling is computed for R. O For NPCS, the priority ceiling is equal to highest priority of all tasks in the system. _ P-432 0 For CP and PC, the priority ceiling is equal to the highest priority of ;-L tasks requiring R. The difference is in allowing- or denying access to P‘ O For MB-CP, the priority ceiling is equal to the priority ceiling of the monitor, which contains the critical section of R. I Assume that a task A holds R. In PI, whenever a higher priority task E‘ requests R, A inherits the priority of B and B is blocked.

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SYLLABUS Section B Real Time and Embedded Operating Systems: Real Time and Embedded Operating Systems: – Introduction, – Hardware Elements, – Structure.

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