Switching Electronics - Betz

ELEC3230 Notes - Switching Electronics

R.E. BetzSchool of Electrical Engineering and Computer Science

University of Newcastle, Australia.email: [email protected]

c©1999, 2000, 2001, 2002, 2003, 2004

Created: May 24, 1999Revised: July 19, 2004

ii

Preface

The notes in this document are for a course in the School of Electrical Engi-neering and Computer Science at the University of Newcastle, Australia. Thiscourse covers a number of topics that can be broadly grouped under the title of“switching electronics”. Electronic switching is the unifying factor that providesthe theme for the course. The notes were written because the subject materialcovers such diverse areas as digital logic switching families, switched transmis-sion lines and printed circuit boards, switch mode power supplies (SMPSs), and(to a lesser degree) converters. No single text book covers such material.

The general approach of the course is to emphasise the practical aspects ofswitching and how design has to be changed to account for its effects. Thetheory behind many of these ideas is presented in detail in the appendices. Thisis particularly true in relation to switching in digital systems with transmissionlines.

The structure of the course is as follows. The first part will consider a varietyof issues related to switching in digital systems. This will include a review oflogic families and interfacing of different logic families. Then issues related tointerfacing logic components on a printed circuit board will be considered. Thiswill include noise issues, transmission line effects, terminations, cross coupling,printed circuit board layout, decoupling issues.

The second section of the course will look at switch mode power supplies intheir various forms. The main structures for switch mode power supplies will beconsidered. Again practical issues will be emphasised. Design of the magneticsfor switching supplies will be considered, as well as some control issues. Thecontrol issues are only briefly considered due to the lack of background of somestudents doing the course.

The final part of the course considers high powered converter and invertertopologies. At this stage there is only an introduction to high power switch-ing devices, and a brief look at naturally commutate converters, mostly singlephase. Eventually there will be a reasonable treatment of three phase naturallyconverters and forced commutated inverters (using thyristors as well as transis-tors).

Robert E. Betz – Newcastle, Australia, July 19, 2004.

iv

Revision History

1999 First version of the notes created for the 5 credit point subject ELEC322.Only included the digital switching and transmission line material.

2000 A major upgrade of the material to include switch mode power supplies,and some material on higher powered converters. This upgrade was nec-essary because the subject changed from ELEC322 to ELEC323, and dou-bled in credit points to 10.

2001 Prior to the issue of the notes, corrections were made to the notes from2000. Added a chapter on the practical design of switch mode powersupplies. Minor corrections and additions made to the notes through thecourse of 2001.

March 2002 Minor corrections and additions made.

July 2002 Made further minor typographical corrections.

July 2003 Further typographical corrections, added section on capacitivelycoupled load terminations, fixed the equivalent circuit of the home brewprobe. Added a new chapter to briefly introduce other power electroniccircuits not already considered in the notes. Added the course outline,schedule, and Saber introductory exercise to the appendix.

August 19, 2003 Made a few typo corrections as well as a change to an in-correct diagram.

July 19, 2004 Made typo corrections and added extra remarks in relation tomagnetic utilisation with push-pull converters. Also added an extra re-mark in relation to the derivation of the fact that harmonics do not con-tribute to real power. Corrected a few minor diagram errors. Added theassignments to the appendices.

vi

Contents

List of Figures xi

List of Tables xix

I Digital Systems 1

1 Logic Families 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Review of Logic Family Properties . . . . . . . . . . . . . . . . . 2

1.2.1 A Brief History . . . . . . . . . . . . . . . . . . . . . . . . 21.2.2 The CMOS Logic Family . . . . . . . . . . . . . . . . . . 3

1.2.2.1 Logic Levels and Noise Margins . . . . . . . . . 61.2.2.2 Fanout . . . . . . . . . . . . . . . . . . . . . . . 91.2.2.3 Specific CMOS Logic Families . . . . . . . . . . 9

1.2.3 Bipolar Logic Families . . . . . . . . . . . . . . . . . . . . 101.2.3.1 Bipolar Logic Noise Margins . . . . . . . . . . . 121.2.3.2 Fanout . . . . . . . . . . . . . . . . . . . . . . . 121.2.3.3 Specific TTL Logic Families . . . . . . . . . . . 13

1.3 Issues in TTL–CMOS Interfacing . . . . . . . . . . . . . . . . . . 13

2 Introduction to Digital Switching 162.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2 Relevant Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 162.3 Propagation, Time and Distance . . . . . . . . . . . . . . . . . . 182.4 Lumped Versus Distributed Systems . . . . . . . . . . . . . . . . 182.5 Four Kinds of Reactance . . . . . . . . . . . . . . . . . . . . . . . 20

2.5.1 Ordinary Capacitance . . . . . . . . . . . . . . . . . . . . 202.5.2 Ordinary Inductance . . . . . . . . . . . . . . . . . . . . . 222.5.3 Mutual Capacitance . . . . . . . . . . . . . . . . . . . . . 28

2.5.3.1 Relationship between Mutual Capacitance andCrosstalk . . . . . . . . . . . . . . . . . . . . . . 28

2.5.4 Mutual Inductance . . . . . . . . . . . . . . . . . . . . . . 332.5.4.1 Relationship Between Mutual Inductance and

Crosstalk . . . . . . . . . . . . . . . . . . . . . . 362.6 Speed of Digital Systems . . . . . . . . . . . . . . . . . . . . . . . 39

2.6.1 dv/dt Effects . . . . . . . . . . . . . . . . . . . . . . . . . 412.6.2 di/dt Effects . . . . . . . . . . . . . . . . . . . . . . . . . 41

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2.6.3 Ground Bounce . . . . . . . . . . . . . . . . . . . . . . . . 442.6.3.1 Why Does Ground Bounce Occur? . . . . . . . . 442.6.3.2 How Does Ground Bounce Affect Circuits? . . . 452.6.3.3 Estimating Ground Bounce Magnitude . . . . . 472.6.3.4 Reducing Ground Bounce . . . . . . . . . . . . . 47

2.6.4 Lead Capacitance . . . . . . . . . . . . . . . . . . . . . . 482.6.5 Measurement Issues . . . . . . . . . . . . . . . . . . . . . 49

2.6.5.1 Rise Time and Bandwidth of CROs . . . . . . . 492.6.5.2 Self-inductance of CRO Probe Ground Clips . . 512.6.5.3 Mutual-inductance of CRO Probe Ground Clips 572.6.5.4 Loading Effect of CRO Probes . . . . . . . . . . 59

2.6.6 Better Probing Techniques . . . . . . . . . . . . . . . . . 622.6.6.1 Home Brew 21:1 Probe . . . . . . . . . . . . . . 622.6.6.2 Low Inductance with Conventional Probes . . . 662.6.6.3 PCB Test Points . . . . . . . . . . . . . . . . . . 662.6.6.4 Shield Currents and Ground Loops . . . . . . . 69

3 Point-to-Point Wiring and Transmission Lines 733.1 Shortcomings of Point-to-Point Wiring . . . . . . . . . . . . . . . 73

3.1.1 EMI Radiation . . . . . . . . . . . . . . . . . . . . . . . . 753.1.2 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.2 Uniform Transmission Lines . . . . . . . . . . . . . . . . . . . . . 773.2.1 Measurement of Distributed Parameters . . . . . . . . . . 773.2.2 Alternative Way of Deriving Characteristic Impedance . . 793.2.3 Physical Explanation of Reflections . . . . . . . . . . . . . 80

3.3 Modelling of Transmission Lines . . . . . . . . . . . . . . . . . . 823.4 Some Practical Effects in Transmission Lines . . . . . . . . . . . 83

3.4.1 Skin Effect . . . . . . . . . . . . . . . . . . . . . . . . . . 833.4.2 Proximity Effect . . . . . . . . . . . . . . . . . . . . . . . 863.4.3 Dielectric Losses . . . . . . . . . . . . . . . . . . . . . . . 87

3.5 Termination of Transmission Lines . . . . . . . . . . . . . . . . . 873.5.1 General Effects of Source and Load Impedance . . . . . . 89

3.5.1.1 Load termination . . . . . . . . . . . . . . . . . 933.5.1.2 Source Termination . . . . . . . . . . . . . . . . 933.5.1.3 Very Short Line . . . . . . . . . . . . . . . . . . 95

3.5.2 Capacitive Terminations . . . . . . . . . . . . . . . . . . . 963.5.2.1 Equally Spaced Capacitive Loads . . . . . . . . 97

3.5.3 Multi-point Terminations . . . . . . . . . . . . . . . . . . 100

4 Ground Planes and other Printed Circuit Board Issues 1084.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1.1 Decoupling Capacitors and Power Planes . . . . . . . . . 1104.2 Crosstalk Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.1 Path of Least Inductance . . . . . . . . . . . . . . . . . . 1114.2.1.1 Crosstalk in Ground Planes . . . . . . . . . . . . 1134.2.1.2 Crosstalk in Slotted Ground Planes . . . . . . . 1144.2.1.3 Crosstalk in Two Layer PCBs . . . . . . . . . . 1164.2.1.4 Crosstalk in with Power and Ground Finger PCBs1184.2.1.5 A Note on Guard Traces . . . . . . . . . . . . . 1194.2.1.6 Distributed Cross Coupling . . . . . . . . . . . . 119

CONTENTS ix

II Switched Mode Power Supplies 125

5 Fundamental Topologies 1265.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265.3 Taxonomy of Switch Mode Converters . . . . . . . . . . . . . . . 127

5.3.1 Step-down or Buck Converters . . . . . . . . . . . . . . . 1275.3.2 Step-up or Boost Converters . . . . . . . . . . . . . . . . 1295.3.3 Buck–Boost Converters . . . . . . . . . . . . . . . . . . . 1305.3.4 Cuk Converters . . . . . . . . . . . . . . . . . . . . . . . . 1325.3.5 Full Bridge Converters . . . . . . . . . . . . . . . . . . . . 134

5.4 Basic Analysis of Switch Mode Converters . . . . . . . . . . . . . 1365.4.1 Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 1365.4.2 Basic PWM Generator . . . . . . . . . . . . . . . . . . . . 1375.4.3 Simplified Analysis of the Buck Converter . . . . . . . . . 139

5.4.3.1 Continuous Conduction Mode . . . . . . . . . . 1395.4.3.2 Boundary between Continuous and Discontinu-

ous Conduction . . . . . . . . . . . . . . . . . . 1415.4.3.2.1 Discontinuous Current with Constant

Vd. . . . . . . . . . . . . . . . . . . . . 1425.4.3.2.2 Discontinuous Current with Constant Vo.145

5.4.3.3 Output Ripple . . . . . . . . . . . . . . . . . . . 1475.4.3.4 Simulation . . . . . . . . . . . . . . . . . . . . . 149

5.4.4 Simplified Analysis of the Boost Converter . . . . . . . . 1515.4.4.1 Continuous Conduction Mode . . . . . . . . . . 1525.4.4.2 Boundary between Continuous and Discontinu-

ous Conduction . . . . . . . . . . . . . . . . . . 1535.4.4.2.1 Discontinuous Current with Constant

Vd. . . . . . . . . . . . . . . . . . . . . 1565.4.4.3 Simulation . . . . . . . . . . . . . . . . . . . . . 159

5.4.5 A Brief Look at the Buck-Boost Converter . . . . . . . . 1595.4.6 A Brief Analysis of the Cuk Converter . . . . . . . . . . . 1615.4.7 Full Bridge dc-dc Converter . . . . . . . . . . . . . . . . . 162

5.4.7.1 Bipolar Switching . . . . . . . . . . . . . . . . . 1635.4.7.2 Unipolar Switching . . . . . . . . . . . . . . . . 166

5.4.8 Comparison of Basic Converter Topologies . . . . . . . . . 1685.4.8.1 Switch Utilisation . . . . . . . . . . . . . . . . . 168

5.4.8.1.1 Buck Converter . . . . . . . . . . . . . 1695.4.8.1.2 Boost Converter . . . . . . . . . . . . . 1695.4.8.1.3 Buck-Boost Converter . . . . . . . . . . 1705.4.8.1.4 Full Bridge Converter . . . . . . . . . . 171

5.4.9 Synchronous Rectifiers . . . . . . . . . . . . . . . . . . . . 1735.4.10 Resonant and Soft-Switching Converters . . . . . . . . . . 173

5.4.10.1 Why One Should Not Use Resonant Converters 1765.4.10.2 Why One Should Use Quasi-Resonant Converters 176

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6 Switch Mode Power Supplies 1786.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786.2 Isolated Converter Topologies . . . . . . . . . . . . . . . . . . . . 178

6.2.1 The Forward Converter . . . . . . . . . . . . . . . . . . . 1786.2.1.1 Other Forward Converter Topologies . . . . . . . 183

6.2.1.1.1 Two Switch Converter . . . . . . . . . . 1846.2.1.1.2 Push-Pull Converter . . . . . . . . . . . 184

6.2.2 The Flyback Converter . . . . . . . . . . . . . . . . . . . 1896.2.3 Utilisation of Magnetics . . . . . . . . . . . . . . . . . . . 194

6.3 Introduction to Control Techniques for Switching Power Supplies 1996.3.1 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016.3.2 Protection Issues . . . . . . . . . . . . . . . . . . . . . . . 204

6.3.2.1 Soft Start . . . . . . . . . . . . . . . . . . . . . . 2046.3.2.2 Voltage Protection . . . . . . . . . . . . . . . . . 2046.3.2.3 Current Limiting . . . . . . . . . . . . . . . . . . 205

6.3.3 Control Architecture of a Switch Mode Power Supply Sys-tem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076.3.3.1 Voltage Mode Control . . . . . . . . . . . . . . . 2076.3.3.2 Voltage Feed-forward PWM Control . . . . . . . 2096.3.3.3 Current Mode Control . . . . . . . . . . . . . . . 209

6.3.3.3.1 Slope Compensation . . . . . . . . . . . 212

7 Introduction to Practical Design of Switch Mode Power Sup-plies 2187.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2187.2 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . 218

7.2.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 2197.2.1.1 Values . . . . . . . . . . . . . . . . . . . . . . . . 2197.2.1.2 Resistor Types . . . . . . . . . . . . . . . . . . . 2197.2.1.3 Tolerance . . . . . . . . . . . . . . . . . . . . . . 2207.2.1.4 Selecting Values . . . . . . . . . . . . . . . . . . 2207.2.1.5 Maximum Voltage . . . . . . . . . . . . . . . . . 2207.2.1.6 Temperature Coefficient . . . . . . . . . . . . . . 2217.2.1.7 Power Rating . . . . . . . . . . . . . . . . . . . . 2217.2.1.8 Shunts . . . . . . . . . . . . . . . . . . . . . . . 2227.2.1.9 PCB Track Resistors . . . . . . . . . . . . . . . 223

7.2.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 2237.2.2.1 Types of Capacitors . . . . . . . . . . . . . . . . 2247.2.2.2 Standard Values . . . . . . . . . . . . . . . . . . 2247.2.2.3 Tolerance . . . . . . . . . . . . . . . . . . . . . . 2257.2.2.4 ESR and Power Dissipation . . . . . . . . . . . . 2257.2.2.5 Aging . . . . . . . . . . . . . . . . . . . . . . . . 2257.2.2.6 dv/dt Rating . . . . . . . . . . . . . . . . . . . . 2267.2.2.7 Series Connection of Capacitors . . . . . . . . . 226

7.2.3 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2267.2.3.1 Schottky Diodes . . . . . . . . . . . . . . . . . . 2267.2.3.2 PN diodes . . . . . . . . . . . . . . . . . . . . . 227

7.2.4 The BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297.2.5 The MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 229

7.2.5.1 Bi-directional Conduction . . . . . . . . . . . . . 230

CONTENTS xi

7.2.5.2 Power Losses . . . . . . . . . . . . . . . . . . . . 2307.2.5.3 MOSFET Gate Resistors . . . . . . . . . . . . . 2317.2.5.4 Maximum Gate Voltage . . . . . . . . . . . . . . 231

7.2.6 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . 2317.2.6.1 Offsets . . . . . . . . . . . . . . . . . . . . . . . 232

7.2.6.1.1 Input Offset Voltage . . . . . . . . . . . 2327.2.6.1.2 Input Offset Current . . . . . . . . . . . 2337.2.6.1.3 Input Bias Current . . . . . . . . . . . 233

7.2.6.2 Limits on Resistor Values . . . . . . . . . . . . . 2347.2.6.3 Gain-Bandwidth Product . . . . . . . . . . . . . 2367.2.6.4 Phase Shift . . . . . . . . . . . . . . . . . . . . . 2367.2.6.5 Slew Rate Limits . . . . . . . . . . . . . . . . . . 237

7.2.7 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . 2377.2.7.1 Hysteresis . . . . . . . . . . . . . . . . . . . . . . 2377.2.7.2 Comparator Interfacing . . . . . . . . . . . . . . 239

7.3 Introduction to Magnetics Design . . . . . . . . . . . . . . . . . . 2397.3.1 Review of the Fundamentals . . . . . . . . . . . . . . . . 240

7.3.1.1 Ampere’s Law . . . . . . . . . . . . . . . . . . . 2407.3.1.2 Faraday’s Law . . . . . . . . . . . . . . . . . . . 2417.3.1.3 Inductance . . . . . . . . . . . . . . . . . . . . . 2417.3.1.4 A Note on Units . . . . . . . . . . . . . . . . . . 2427.3.1.5 The Three R’s . . . . . . . . . . . . . . . . . . . 243

7.3.1.5.1 Reactance . . . . . . . . . . . . . . . . 2437.3.1.5.2 Remanence . . . . . . . . . . . . . . . . 2437.3.1.5.3 Reluctance . . . . . . . . . . . . . . . . 244

7.3.2 The Ideal Transformer . . . . . . . . . . . . . . . . . . . . 2447.3.3 Real Transformers . . . . . . . . . . . . . . . . . . . . . . 246

7.3.3.1 Core Materials . . . . . . . . . . . . . . . . . . . 2477.3.3.2 Saturation . . . . . . . . . . . . . . . . . . . . . 2477.3.3.3 Other Core Limitations . . . . . . . . . . . . . . 249

7.3.3.3.1 Curie Temperature . . . . . . . . . . . 2497.3.3.3.2 Core Losses . . . . . . . . . . . . . . . . 249

7.3.4 Optimal Design Issues . . . . . . . . . . . . . . . . . . . . 2507.3.5 Design of an Inductor . . . . . . . . . . . . . . . . . . . . 252

7.3.5.1 Key Magnetic Parameters . . . . . . . . . . . . . 2557.3.5.1.1 Initial Permeability . . . . . . . . . . . 2557.3.5.1.2 Effective Permeability . . . . . . . . . . 2557.3.5.1.3 Amplitude Permeability . . . . . . . . . 2557.3.5.1.4 Incremental Permeability . . . . . . . . 2557.3.5.1.5 Effective Core Dimensions . . . . . . . 2567.3.5.1.6 Inductance Factor . . . . . . . . . . . . 256

7.3.5.2 Details of Inductor Design . . . . . . . . . . . . 2577.3.5.3 Issues in Forward Converter Transformer Design 263

7.3.5.3.1 Turns Ratio = 1:1 . . . . . . . . . . . . 2647.3.5.3.2 Turns Ratio = 2:1 . . . . . . . . . . . . 2647.3.5.3.3 Turns Ratio = 3:1 . . . . . . . . . . . . 2647.3.5.3.4 Turns Ratio = 4:1 . . . . . . . . . . . . 264

7.3.6 Design of Manufacturable Magnetics . . . . . . . . . . . . 2657.3.6.1 Wire Gauge . . . . . . . . . . . . . . . . . . . . 2657.3.6.2 Wire Gauge Ratio . . . . . . . . . . . . . . . . . 265

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7.3.6.3 Toroidal Core Winding Limits . . . . . . . . . . 2657.3.6.4 Tape versus Wire Insulation . . . . . . . . . . . 2667.3.6.5 Layering of Windings . . . . . . . . . . . . . . . 2667.3.6.6 Number of Windings . . . . . . . . . . . . . . . 2667.3.6.7 Potting . . . . . . . . . . . . . . . . . . . . . . . 2677.3.6.8 Safety Requirements . . . . . . . . . . . . . . . . 267

III Line Commutated Converters and High Power In-verters 269

8 Introduction to High Power Converter Technology 2708.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

8.1.1 Applications of Power Converter Technology . . . . . . . 2718.2 Review of Power Semiconductor Devices . . . . . . . . . . . . . . 272

8.2.1 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2728.2.2 Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

8.2.2.1 Turn-on Transient . . . . . . . . . . . . . . . . . 2798.2.2.2 Turn-off Transient . . . . . . . . . . . . . . . . . 281

8.2.3 Gate Turn-off Thyristors . . . . . . . . . . . . . . . . . . . 2828.2.3.1 Snubbers and GTO Thyristors . . . . . . . . . . 2838.2.3.2 GTO Turn-on . . . . . . . . . . . . . . . . . . . 2858.2.3.3 GTO Turn-off . . . . . . . . . . . . . . . . . . . 286

8.2.4 Insulated Gate Bipolar Transistors (IGBTs) . . . . . . . . 2898.2.4.1 IGBT Operation . . . . . . . . . . . . . . . . . . 2898.2.4.2 IGBT Turn-on . . . . . . . . . . . . . . . . . . . 2928.2.4.3 IGBT Turn-off . . . . . . . . . . . . . . . . . . . 292

8.2.5 Other Devices and Developments . . . . . . . . . . . . . . 2938.2.5.1 Power Junction Field Effect Transistors . . . . . 2938.2.5.2 Field Controlled Thyristor . . . . . . . . . . . . 2938.2.5.3 MOS-Controlled Thyristors . . . . . . . . . . . . 2948.2.5.4 New Semiconductor Materials . . . . . . . . . . 294

9 Line Frequency Uncontrolled Rectifiers 2999.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2999.2 Some Mathematical Preliminaries . . . . . . . . . . . . . . . . . . 299

9.2.1 Fourier Analysis of Repetitive Waveforms . . . . . . . . . 3009.2.1.1 Measures of Waveform Distortion . . . . . . . . 3019.2.1.2 Power and Power Factor . . . . . . . . . . . . . 303

9.3 The Half Wave Rectifier Circuit . . . . . . . . . . . . . . . . . . . 3089.3.1 Pure Resistive Load . . . . . . . . . . . . . . . . . . . . . 3089.3.2 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . 3099.3.3 Inductive Load with Back EMF . . . . . . . . . . . . . . . 311

9.4 The Concept of Current Commutation . . . . . . . . . . . . . . . 3129.5 Practical Uncontrolled Single Phase Rectifiers . . . . . . . . . . . 317

9.5.1 Unity Power Factor Single Phase Rectifier . . . . . . . . . 3239.5.2 Effect of Current Harmonics on Line Voltages . . . . . . . 3289.5.3 Voltage Doubler Single Phase Rectifiers . . . . . . . . . . 3299.5.4 The Effect of Single Phase Rectifiers on Three Phase, Four

Wire Systems . . . . . . . . . . . . . . . . . . . . . . . . . 330

CONTENTS xiii

9.6 Three Phase, Full Bridge Rectifiers . . . . . . . . . . . . . . . . . 332

10 Introduction to Other Power Electronic Devices and Applica-tions 33510.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33510.2 Inverters and Applications . . . . . . . . . . . . . . . . . . . . . . 335

10.2.1 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . 33810.2.1.1 Space Vectors and PWM . . . . . . . . . . . . . 342

10.2.2 Dead-time Issues . . . . . . . . . . . . . . . . . . . . . . . 34710.2.3 Some Inverter Applications . . . . . . . . . . . . . . . . . 349

10.2.3.1 Variable Speed Drives . . . . . . . . . . . . . . . 34910.2.3.2 Grid Connected Applications . . . . . . . . . . . 350

10.3 Multilevel Converters and Applications . . . . . . . . . . . . . . . 35210.4 Matrix Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 352

IV Appendices 353

A List of Course Materials 354

B Course Outline 355B.1 Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355B.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355B.3 Course Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . 356B.4 Plagiarism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357B.5 Special Consideration . . . . . . . . . . . . . . . . . . . . . . . . 357B.6 Changing Your Enrolment . . . . . . . . . . . . . . . . . . . . . . 357B.7 Support Services . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

C Course Schedule 359

D Introductory Exercise using Saber Simulator 361D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361D.2 Circuit Schematic Capture . . . . . . . . . . . . . . . . . . . . . . 362D.3 Executing the Transient Analysis . . . . . . . . . . . . . . . . . . 366D.4 Plotting and Processing Results . . . . . . . . . . . . . . . . . . . 367

D.4.1 Manipulating Results . . . . . . . . . . . . . . . . . . . . 368D.4.2 Fourier Analysis . . . . . . . . . . . . . . . . . . . . . . . 371

D.5 A Practice Exercise . . . . . . . . . . . . . . . . . . . . . . . . . . 372

E Assignment 1 375E.1 How to Answer the Questions . . . . . . . . . . . . . . . . . . . . 376E.2 Software Tools to Aid Report Production . . . . . . . . . . . . . 376

F Assignment 2 383F.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383F.2 Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . 385F.3 The Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

F.3.1 The Buck Converter . . . . . . . . . . . . . . . . . . . . . 385F.3.2 Boost converter . . . . . . . . . . . . . . . . . . . . . . . . 386F.3.3 Forward converter . . . . . . . . . . . . . . . . . . . . . . 388

xiv CONTENTS

G Review of Second Order Circuits 390G.1 Series RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 390

G.1.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . 393G.1.2 Time Domain Response . . . . . . . . . . . . . . . . . . . 394

G.2 Parallel RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . 395G.2.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . 397

H Review of Transmission Lines 399H.1 Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402H.2 Solution of Transmission Line Equations for the Lossless Case . . 403

H.2.1 Semi-infinite Transmission Line . . . . . . . . . . . . . . . 408H.2.2 Finite Transmission Line and Reflection Coefficient . . . . 409

H.3 Reflection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 412H.4 Time Harmonic Solutions for Lossy Lines . . . . . . . . . . . . . 415

H.4.1 Solutions for Voltage and Currents . . . . . . . . . . . . . 417H.4.2 Semi-infinite Transmission Line . . . . . . . . . . . . . . . 418H.4.3 Finite Length Transmission Lines . . . . . . . . . . . . . . 421H.4.4 Line Input Impedance . . . . . . . . . . . . . . . . . . . . 422

H.4.4.1 Lossless Line Input Impedance . . . . . . . . . . 424H.4.5 Transfer Function of a Lossless Transmission Line . . . . 424H.4.6 Thevenin Equivalent Circuit . . . . . . . . . . . . . . . . . 425

I Useful Formulae 427I.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427I.2 Useful Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . 427I.3 Formulae . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

I.3.1 AWG Related Conversions . . . . . . . . . . . . . . . . . . 427I.3.2 Copper Plate Weight Formulae . . . . . . . . . . . . . . . 428I.3.3 Parallel Plate Capacitance . . . . . . . . . . . . . . . . . . 429I.3.4 Inductance of Circular Wire Loops . . . . . . . . . . . . . 429I.3.5 Inductance of Rectangular Loops . . . . . . . . . . . . . . 430I.3.6 Mutual Inductance of Two Loops . . . . . . . . . . . . . . 430I.3.7 Mutual Inductance of Parallel Transmission Lines . . . . 430I.3.8 General Transmission Line Expressions . . . . . . . . . . 431I.3.9 Coaxial Transmission Line . . . . . . . . . . . . . . . . . . 431I.3.10 Single Wire Above a Ground Plane . . . . . . . . . . . . . 432I.3.11 Twisted Pair Transmission Line . . . . . . . . . . . . . . . 433I.3.12 Microstrip Transmission Line . . . . . . . . . . . . . . . . 434I.3.13 Symmetric Stripline Transmission Line . . . . . . . . . . . 435I.3.14 Offset Stripline Transmission Line . . . . . . . . . . . . . 435

Bibliography 437

List of Figures

1.1 Block diagram of an enhancement mode n-channel MOSFET. . . 41.2 Common circuit symbols for enhancement mode MOSFETs. . . . 51.3 CMOS inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4 Typical transfer characteristic for a CMOS inverter. . . . . . . . 71.5 Noise margin and generic logic level definitions. . . . . . . . . . . 81.6 Typical circuit for a TTL NAND gate. . . . . . . . . . . . . . . . 111.7 Worst case logic levels with TTL loadings. . . . . . . . . . . . . . 14

2.1 Approximate transmission line. . . . . . . . . . . . . . . . . . . . 192.2 Time domain plots of voltages along a transmission line. . . . . . 212.3 Voltage versus distance along a transmission line. . . . . . . . . . 212.4 Examples of capacitive circuit waveforms. . . . . . . . . . . . . . 232.5 Examples of inductance circuit waveforms. . . . . . . . . . . . . . 242.6 Field reinforcement and cancellation with parallel conductors. . . 272.7 Mutual coupling example between resistors. . . . . . . . . . . . . 302.8 Equivalent circuit for mutual capacitive coupling example. . . . . 312.9 Simulation plots for capacitor cross coupling. . . . . . . . . . . . 312.10 Relevant capacitive coupling waveforms with resistors grounded. 332.11 Example of mutual inductance in a digital system. . . . . . . . . 352.12 Measurement setup for mutual inductance experiment. . . . . . . 382.13 Physical configuration of resistors in inductive coupling experiment. 382.14 Equivalent circuit for simulation of inductive mutual coupling. . 392.15 Results of the inductive cross coupling simulation. . . . . . . . . 402.16 Logic gate with a capacitive load. . . . . . . . . . . . . . . . . . . 422.17 Inductive coupling waveforms with a 10pf load capacitance. . . . 432.18 Schematic of an integrated circuit showing the lead inductance. . 442.19 Example waveforms for an octal latch driving a capacitive load. . 462.20 Logic package showing the capacitance between pins. . . . . . . . 502.21 Composite rise time of an oscilloscope. . . . . . . . . . . . . . . . 502.22 Equivalent circuit of CRO input probe. . . . . . . . . . . . . . . 522.23 Bode plot of the transfer function of a CRO probe. . . . . . . . . 542.24 Response of the CRO probe equivalent circuit with the input rise

time of 1.8nsec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552.25 Response of the CRO probe equivalent circuit with the input rise

time of 5.5nsec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562.26 General configuration for probe lead pick up. . . . . . . . . . . . 582.27 CRO probe equivalent circuit with no lead inductance. . . . . . . 602.28 Source to probe input transfer function for a CRO probe. . . . . 61

xvi LIST OF FIGURES

2.29 CRO probe input impedance. . . . . . . . . . . . . . . . . . . . . 612.30 A home brew 21:1 high speed probe. . . . . . . . . . . . . . . . . 632.31 Equivalent circuit for the home brew probe. . . . . . . . . . . . . 632.32 Speed-up circuit as applied to a CRO probe input. . . . . . . . . 672.33 Ideal frequency response for a correctly compensate speed-up cir-

cuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672.34 Use of wire connection to lower sense loop inductance. . . . . . . 682.35 Low inductance probe connection. . . . . . . . . . . . . . . . . . 682.36 Layout of a PCB embedded high frequency test point . . . . . . 692.37 Noise pick-up due to shield currents. . . . . . . . . . . . . . . . . 702.38 Differential probing to eliminate shield current effects. . . . . . . 72

3.1 Physical configuration of different types of common transmissionlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.2 Experimental set-up to measure transmission line distributed pa-rameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.3 Voltage pulse in an ideal transmission line. . . . . . . . . . . . . . 803.4 Typical dimensions of PCB traces to produce 50Ω and 75Ω char-

acteristic impedances. . . . . . . . . . . . . . . . . . . . . . . . . 813.5 Model of the transmission line using coupled LC sections. . . . . 833.6 Lenz’s Law explanation of the skin effect. . . . . . . . . . . . . . 843.7 Resistance of AWG 24 round wire (diameter = 0.02in) with fre-

quency (reproduced from [1] page 158). . . . . . . . . . . . . . . 853.8 Example of the proximity effect in round conductors. . . . . . . . 863.9 Diagrammatic representation of the various reflected signals in a

transmission line showing the acceptance, propagation and trans-mission transfer functions. . . . . . . . . . . . . . . . . . . . . . . 92

3.10 Load terminations: (a) Conventional termination, (b) Capacitivetermination 1, (c) Capacitive termination 2. . . . . . . . . . . . . 94

3.11 Transmission line with a capacitive load in the middle. . . . . . . 963.12 Right angle track showing origin of additional capacitance. . . . 983.13 Chamfered track to match impedance around a right angle corner. 983.14 Transmission line with equally spaced capacitive loads. . . . . . . 993.15 Some possible multi-point configurations. . . . . . . . . . . . . . 1003.16 Voltage just prior to line connection with mid line multi-point

connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013.17 Termination voltage with a mid line multi-point connection. . . . 1023.18 Waveform plots for a multi-point line with a single series termi-

nation and mid point line connection. . . . . . . . . . . . . . . . 1023.19 Two multi-point lines branching from a Z0/2 source terminator

– the lines are of the same length. . . . . . . . . . . . . . . . . . 1033.20 Two multi-point lines branching from a Z0/2 source terminator

– the lines are of different lengths. . . . . . . . . . . . . . . . . . 1043.21 Multi-point splitter using resistive network. . . . . . . . . . . . . 1053.22 Multi-point waveforms using the resistive “splitter” network. . . 1053.23 Poorly designed gate daisy chain with end termination. . . . . . 1063.24 Better design for a gate daisy chain. . . . . . . . . . . . . . . . . 107

4.1 Dimensions of two power planes. . . . . . . . . . . . . . . . . . . 109

LIST OF FIGURES xvii

4.2 Approximate current flows with low and high frequency spectralcontent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

4.3 Distribution of current in the ground plane when the currentshave high frequency components. . . . . . . . . . . . . . . . . . . 113

4.4 Two traces above a ground plane and the resultant current dis-tribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.5 Current paths with a slot cut in the ground plane of a PCB. . . . 1154.6 Current flow through connect hole grids. . . . . . . . . . . . . . . 1154.7 Layout of a two layer power plane. . . . . . . . . . . . . . . . . . 1174.8 Layout of a finger power and ground plane system. . . . . . . . . 1184.9 Guard trace configuration. . . . . . . . . . . . . . . . . . . . . . . 1204.10 Model for the coupling of a distributed transmission line. . . . . 1204.11 Mutual inductively coupled transmission lines with Tr = 210psec 1224.12 Waveforms for capacitively coupled transmission lines and Tr =

210psec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234.13 Mutual coupling waveforms with both inductive and capacitive

coupling and Tr = 210psec. . . . . . . . . . . . . . . . . . . . . . 124

5.1 Block diagram of the structure of a typical DC-DC converter. . . 1275.2 A basic buck or step-down converter. . . . . . . . . . . . . . . . . 1295.3 A basic boost or step-up converter. . . . . . . . . . . . . . . . . . 1295.4 Two switch buck–boost converter. . . . . . . . . . . . . . . . . . 1315.5 Single switch Buck–boost converter circuit. . . . . . . . . . . . . 1325.6 The Cuk converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 1335.7 Cuk converter with the switch open. . . . . . . . . . . . . . . . . 1335.8 Cuk converter with the switch closed. . . . . . . . . . . . . . . . 1345.9 Full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . 1355.10 Definition of the terms related to duty cycle. . . . . . . . . . . . 1365.11 Waveforms in a sawtooth based PWM modulator. . . . . . . . . 1385.12 Simple PWM generator circuit. . . . . . . . . . . . . . . . . . . . 1385.13 Currents and circuit configurations for a buck converter. . . . . . 1405.14 Current waveform at the point of discontinuous current in the

inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425.15 Current waveform for a buck converter with discontinuous current.1435.16 Voltage ratio of the buck converter for continuous and discontin-

uous operation modes and constant Vd. NB. ILBmax = TsVd

8L . . . 1445.17 Characteristics of the buck converter with constant Vo. NB.

ILBmax = TsVo

2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465.18 Output voltage ripple for a buck converter. . . . . . . . . . . . . 1485.19 Circuit used in simulation of the buck converter. . . . . . . . . . 1505.20 Waveforms for a buck converter with D = 0.5, RL = 100, and

continuous inductor current. . . . . . . . . . . . . . . . . . . . . . 1505.21 Initial startup waveforms for a buck converter with D = 0.5,

RL = 40kΩ, and discontinuous inductor current. . . . . . . . . . 1515.22 Currents and circuit configurations for a boost converter. . . . . 1525.23 Voltage ratio of a boost converter versus duty cycle. . . . . . . . 1535.24 Current waveform on the edge of continuous current. . . . . . . . 1545.25 Plot of the normalised continuous current boundary for the boost

converter (Vo constant). . . . . . . . . . . . . . . . . . . . . . . . 155

xviii LIST OF FIGURES

5.26 Current waveforms for the boost converter with discontinuouscurrent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.27 Duty cycle versus normalised output current for the boost con-verter with constant Vo. . . . . . . . . . . . . . . . . . . . . . . . 158

5.28 Boost converter simulated using Saber. . . . . . . . . . . . . . . 1595.29 Simulated waveforms for a boost converter with D = 0.5 and

continuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . 1605.30 Output of a boost converter in continuous current mode with

several different duty cycles. . . . . . . . . . . . . . . . . . . . . . 1605.31 Steady state currents and voltages in a Cuk converter. . . . . . . 1615.32 Waveforms for a full bridge converter with a bipolar switching

strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645.33 Waveforms for a full bridge converter with a unipolar switching

strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675.34 The input current into a buck-boost converter with a large input

inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705.35 Plot of switch utilisation for the common converter types. . . . . 1725.36 (a) Conventional non-synchronous rectifier based boost converter.

(b) Synchronous rectifier based boost converter. . . . . . . . . . . 1745.37 A zero current switching (ZCS) resonant buck converter. . . . . . 1755.38 A zero voltage switching (ZVS) resonant buck converter. . . . . . 1755.39 A quasi-resonant forward converter. . . . . . . . . . . . . . . . . 177

6.1 Basic circuit of the forward converter. . . . . . . . . . . . . . . . 1796.2 A practical forward converter. . . . . . . . . . . . . . . . . . . . . 1806.3 Equivalent circuit for a practical forward converter. . . . . . . . . 1806.4 Current waveforms for a practical forward converter. . . . . . . . 1826.5 Circuit diagram of a two switch forward converter. . . . . . . . . 1846.6 Push-pull forward converter. . . . . . . . . . . . . . . . . . . . . . 1856.7 Currents flowing in the push-pull forward converter with SW1

closed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866.8 Currents flowing in the push-pull forward converter with SW1

and SW2 open. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876.9 Flux imbalance in the push-pull circuit. . . . . . . . . . . . . . . 1896.10 Connection between the Buck-Boost and Flyback converter. . . . 1906.11 Flyback converter with the switch closed. . . . . . . . . . . . . . 1916.12 Flyback converter with the switch open. . . . . . . . . . . . . . . 1916.13 The voltage, current and flux in the ideal Flyback Converter. . . 1936.14 Typical BH loop for a magnetic material. . . . . . . . . . . . . . 1956.15 Core excitation waveforms. (a) forward converter. (b) full bridge

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1966.16 Block diagram of a typical switch mode power supply. . . . . . . 2006.17 Feedback circuit using a small forward converter. . . . . . . . . . 2026.18 Example of a simple bootstrap power circuit for a PWM genera-

tor chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2036.19 Bootstrap circuitry modified for increased hysteresis range. . . . 2046.20 Block diagram of the Unitrode high speed PWM generator. . . 2056.21 Operation of a constant current limit. . . . . . . . . . . . . . . . 2066.22 Operation of a foldback current limit. . . . . . . . . . . . . . . . 206

LIST OF FIGURES xix

6.23 Conceptual diagram of a control system for a switch mode powersupply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.24 Linearised model of a switch mode power supply. . . . . . . . . . 2086.25 Block diagram of a nested loop control system for a switch mode

power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2096.26 Waveforms for tolerance band current control. . . . . . . . . . . . 2116.27 Waveforms for constant “off” time control. . . . . . . . . . . . . 2126.28 Waveforms for constant frequency with turn-on at clock time con-

trol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136.29 Open loop instability of current mode control. (a) stability with

duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stabil-ity with duty cycle > 0.5 and slope compensation. . . . . . . . . 214

6.30 Geometrical relationship of the current waveform slopes whenthere is a current perturbation. . . . . . . . . . . . . . . . . . . . 216

6.31 Inductor current response of current mode converter. . . . . . . . 2166.32 Optimal slope compensation to eliminate RLC type oscillations. . 217

7.1 Equivalent circuit model of a current shunt . . . . . . . . . . . . 2227.2 Method of voltage sharing for series capacitors. . . . . . . . . . . 2277.3 Reverse recovery in a converter secondary circuit. . . . . . . . . . 2277.4 Reverse recovery in a boost converter circuit. . . . . . . . . . . . 2287.5 Operational amplifier circuit for discussion of offsets. . . . . . . . 2327.6 Conventional inverting Op Amp circuit with a gain of 1000. . . . 2347.7 Inverting Op Amp circuit with alternative feedback network. . . 2357.8 Gain-bandwidth product of an Op Amp. . . . . . . . . . . . . . . 2367.9 Comparator with hysteresis. . . . . . . . . . . . . . . . . . . . . . 2387.10 Interfacing a comparator to an NPN transistor. . . . . . . . . . . 2397.11 A loop of wire enclosing an area of time varying flux density. . . 2417.12 A BH loop for a magnetic material. . . . . . . . . . . . . . . . . 2437.13 Circuit symbol for a transformer. . . . . . . . . . . . . . . . . . . 2457.14 Simplified model of a real transformer. . . . . . . . . . . . . . . . 2477.15 Ferrite choice (from [2]). . . . . . . . . . . . . . . . . . . . . . . . 2537.16 Initial permeability with respect to frequency for 2P iron powder

Ferroxcube material (from [3]). . . . . . . . . . . . . . . . . . . . 2537.17 Incremental permeability as a function of magnetic field strength

for 2P iron powder Ferroxcube material (from [3]). . . . . . . . . 2547.18 Core type selection table (from [3]). . . . . . . . . . . . . . . . . 2577.19 Core data for toroidal cores using powdered iron (from [3]). . . . 2597.20 Typical BH characeristic for 2P magnetic material (from [3]). . . 2607.21 Losses in 2P material with respect to flux density and frequency

(from [3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2617.22 Winding interleaving for high-dielectric isolation and good pri-

mary to secondary coupling. . . . . . . . . . . . . . . . . . . . . . 2677.23 A transformer design to satisfy safety requirements. . . . . . . . 268

8.1 The current-voltage characteristic of a diode. . . . . . . . . . . . 2738.2 Conceptual structure of a conventional diode. . . . . . . . . . . . 2748.3 Conceptual structure of a power diode. . . . . . . . . . . . . . . . 2748.4 Typical reverse recovery characteristic for a diode. . . . . . . . . 2768.5 Conceptual diagram of a thyristor. . . . . . . . . . . . . . . . . . 277

xx LIST OF FIGURES

8.6 Transistor model of the thyristor. . . . . . . . . . . . . . . . . . . 2778.7 Typical characteristic of a thyristor. . . . . . . . . . . . . . . . . 2798.8 Typical turn-on waveforms for a thyristor. . . . . . . . . . . . . . 2808.9 Typical thyristor turn-off waveforms. . . . . . . . . . . . . . . . . 2818.10 An example of a dc chopper circuit using a GTO thyristor . . . . 2848.11 Turn on waveforms for a GTO thyristor. . . . . . . . . . . . . . . 2858.12 Turn-off waveforms for a GTO thyristor. . . . . . . . . . . . . . . 2878.13 GTO thyristor circuit with additional “crowbar” SCR . . . . . . 2888.14 A schematic diagram of the basic structure of the IGBT. . . . . . 2908.15 The IGBT voltage and current transfer characteristics and circuit

symbol: (a) output characteristic; (b) transfer characteristic; (c)and (d) n-channel IGBT circuit symbols. . . . . . . . . . . . . . . 291

8.16 Current flows in the IGBT. . . . . . . . . . . . . . . . . . . . . . 2958.17 Equivalent circuits for the IGBT: (a) approximate equivalent cir-

cuit for normal operating conditions; (b) more complete equiva-lent circuit showing the parasitic thyristor. . . . . . . . . . . . . . 296

8.18 Typical turn-on waveforms for an IGBT. . . . . . . . . . . . . . . 2978.19 Turn-off waveforms for an IGBT. . . . . . . . . . . . . . . . . . . 2988.20 Schematic and circuit symbol for the P-MCT. . . . . . . . . . . . 298

9.1 Line current waveform distortion. . . . . . . . . . . . . . . . . . . 3019.2 Phasor relationship for complex power. . . . . . . . . . . . . . . . 3049.3 Diagram of the normalised single phase power components with a

30 phase angle – the power is normalised by dividing by VrmsIrms.3059.4 Half wave rectifier with a resistive load. . . . . . . . . . . . . . . 3099.5 Half wave rectifier with an LR load. . . . . . . . . . . . . . . . . 3099.6 Plots for a half wave rectifier with an LR load – L = 200mH and

R = 50Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3109.7 Half wave rectifier circuit with an inductor and back emf. . . . . 3119.8 Plots for a half wave rectifier with an inductor and back emf as

a load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3129.9 Test circuit used for current commutation discussion. . . . . . . . 3139.10 Circuit configurations during current commutation of the circuit

in Figure 9.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3149.11 Plots of the currents in the test circuit of Figure 9.9 – vs =

50 sin ωt, Ls = 5mH, Id = 1 Amp. . . . . . . . . . . . . . . . . . . 3169.12 A practical single phase rectifier. . . . . . . . . . . . . . . . . . . 3179.13 Equivalent circuit of the single phase rectifier when the diodes

are conducting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3189.14 Waveforms for the practical single phase rectifier circuit of Fig-

ure 9.12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3199.15 Input current and output voltage harmonics in a single phase

rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3209.16 Real and imaginary components of the harmonic phasors for the

harmonics single phase rectifier harmonics plotted in Figure 9.14. 3219.17 Single phase rectifier with input and dc link filters. . . . . . . . . 3249.18 Circuit for the a single phase rectifier with current wave shaping

boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

LIST OF FIGURES xxi

9.19 Waveforms for a single phase rectifier with active current wave-shaping – (a) the input current and voltage; (b) the boost con-verter input voltage and inductor current. . . . . . . . . . . . . . 326

9.20 Block diagram of the control system for a single phase rectifierwith active current waveshaping. . . . . . . . . . . . . . . . . . . 328

9.21 Single phase rectifier showing the point of common coupling. . . 3299.22 Single phase rectifier voltage doubler. . . . . . . . . . . . . . . . . 3309.23 Single phase rectifiers loads in a three phase, four wire distribu-

tion system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3319.24 Basic three phase, six pulse, full wave rectifier circuit. . . . . . . 3339.25 Waveforms of a three phase rectifier with a constant current

source load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

10.1 Definition of rectifier and inverter modes of operation [4]. . . . . 33610.2 Generic power processing block [4]. . . . . . . . . . . . . . . . . . 33610.3 Block diagram of a generic AC drive system. . . . . . . . . . . . 33710.4 Specific implementation of an inverter. . . . . . . . . . . . . . . . 33810.5 Single leg of inverter and the PWM waveforms. . . . . . . . . . . 33910.6 Switch positions and the resultant voltage space vectors. . . . . . 34210.7 Switching waveforms for double edge pulse width modulation. . . 34310.8 Switching time determination. . . . . . . . . . . . . . . . . . . . . 34410.9 Voltage limit hexagon. . . . . . . . . . . . . . . . . . . . . . . . . 34610.10Inverter showing the initial and final current flow after a leg is

fired. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34710.11Example of dead-time induced switching error in an inverter. . . 34810.12Generic non-battery based photo-voltaic supply system. . . . . . 35110.13Some grid connected FACTS units offered by Siemens. . . . . . . 351

D.1 Simple single phase, half wave rectifier, with an LR load. . . . . . 362D.2 Initial screen upon invoking SaberSketch. . . . . . . . . . . . . . 363D.3 An example of a parts gallery screen. . . . . . . . . . . . . . . . . 364D.4 The wire attributes window. . . . . . . . . . . . . . . . . . . . . . 367D.5 An example of SaberSketch with the Saber guide toolbar activated.368D.6 An example dc/transient simulation set-up window. . . . . . . . 369D.7 The input-output table of the dc/transient analysis window. . . . 370D.8 The initial SaberScope window. . . . . . . . . . . . . . . . . . . . 371D.9 A signal plotted in SaberScope. . . . . . . . . . . . . . . . . . . . 372D.10 An example of a waveform calculation in SaberScope. . . . . . . 373D.11 Fourier analysis dialogues in Saber. . . . . . . . . . . . . . . . . . 373

E.1 Test Printed Circuit Board. . . . . . . . . . . . . . . . . . . . . . 380

F.1 Power circuit of switch experimental box. . . . . . . . . . . . . . 384F.2 PWM control circuit for laboratory module. . . . . . . . . . . . . 384F.3 Buck converter – Saber circuit. . . . . . . . . . . . . . . . . . . . 386F.4 Conceptual PWM control circuit for the buck converter. . . . . . 387F.5 Saber model of the boost converter. . . . . . . . . . . . . . . . . 387F.6 Practical isolated forward converter circuit. . . . . . . . . . . . . 389

G.1 Series RLC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 391

xxii LIST OF FIGURES

G.2 Series RLC circuit pole positions. . . . . . . . . . . . . . . . . . . 392G.3 Time response of a series RLC circuit with Q = 6.3. . . . . . . . 396G.4 Parallel RLC circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 396

H.1 Two wire transmission line and a single element model. . . . . . 401H.2 Semi-infinite transmission line with source . . . . . . . . . . . . . 410H.3 Plot of pulse in the time and distance domains . . . . . . . . . . 410H.4 DC voltage transient on a transmission line . . . . . . . . . . . . 412H.5 Voltage reflection diagram . . . . . . . . . . . . . . . . . . . . . . 414H.6 Terminated transmission line and the equivalent circuit . . . . . 423H.7 Thevenin equivalent circuit of a transmission line . . . . . . . . . 425

I.1 Parallel plate capacitor. . . . . . . . . . . . . . . . . . . . . . . . 429I.2 Coaxial cable cross-section. . . . . . . . . . . . . . . . . . . . . . 431I.3 Round wire suspended above a ground plane. . . . . . . . . . . . 432I.4 Configuration of twisted pair transmission line. . . . . . . . . . . 433I.5 Dimensions of a microstrip transmission line. . . . . . . . . . . . 434I.6 Dimensions of a symmetric stripline. . . . . . . . . . . . . . . . . 435I.7 Dimensions of the offset transmission line. . . . . . . . . . . . . . 436

List of Tables

2.1 Propagation delays for electromagnetic fields in various media. . 182.2 Typical switching characteristics of common logic families. . . . . 472.3 Lead inductances of various logic packages. . . . . . . . . . . . . 492.4 Inter-pin capacitance of common logic packages. . . . . . . . . . 492.5 Rise time and Q for 10pF and 2pF capacitance probes for various

inductances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.6 Inductance and rise time of male coax connectors. . . . . . . . . 642.7 Rise time of some coaxial cables. . . . . . . . . . . . . . . . . . . 652.8 Rise time of home brew probe sense loop. . . . . . . . . . . . . . 65

3.1 Statistics for point-to-point wire wrap board . . . . . . . . . . . . 73

7.1 Resistor application selection guide . . . . . . . . . . . . . . . . . 2207.2 Capacitor application guide . . . . . . . . . . . . . . . . . . . . . 2247.3 Core materials and their uses. . . . . . . . . . . . . . . . . . . . . 2487.4 Inductor specifications. . . . . . . . . . . . . . . . . . . . . . . . . 252

9.1 Fourier coefficient formulae with symmetry. . . . . . . . . . . . . 3019.2 Current harmonic amplitudes. . . . . . . . . . . . . . . . . . . . . 323

10.1 Switching combinations and associated phase and line-to-line volt-ages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

10.2 Switching combinations and associated phase and phase-to-neutralvoltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

10.3 PWM firing times for various sectors . . . . . . . . . . . . . . . . 34510.4 Voltage limit γ’s . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

D.1 Number magnitude specifiers in Saber . . . . . . . . . . . . . . . 366

I.1 Useful constants . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

xxiv LIST OF TABLES

Part I

Digital Systems

Chapter 1

Logic Families

1.1 Introduction

This chapter will consider various issues related to the switching aspects of themain digital logic families. Some consideration will be given to the internal op-eration of the main logic families, with particular emphasis on how the internaloperation manifests itself in the terminal characteristics of logic devices.

An understanding of logic families is important in order to reliably interfacecomponents coming from different types. In addition the switching character-istics of the different families have implications on the design of printed circuitboards and the noise induced on them.

1.2 Review of Logic Family Properties

1.2.1 A Brief History

Much of the material presented in this section is based on the presentation in [5].Electrically controlled digital logic circuits were first developed at Bell Labora-tories in the 1930s, and were based on using relays. The relays were replacedin the 1940s with vacuum tubes, resulting in the worlds first electronic digitalcomputer (known as Eniac). This machine had 18,000 vacuum tubes (and asimilar number of logic gates) and consumed 140,000 Watts of power. The in-vention of the semiconductor diode and bipolar junction transistor allowed thedevelopment of smaller, faster, and more capable computers in the late 1950s.The basic concepts used in these machines were further refined and integratedinto a more compact form in the 1960s with the invention of the integrated cir-cuit. The development of the integrated circuit was very important in loweringthe cost of computers, and at the same time increasing their capabilities.

The 1960s saw the introduction of the first integrated-circuit logic families.A logic family is a collection of different integrated circuit chips that have similar logic familiesinput, output and internal circuit characteristics. This allows all the chips inthe family to be easily interfaced with each other. The converse of this is thatthere may be incompatibility with integrated circuits from other families.

The most successful bipolar logic family (i.e. based on the use of bipolarjunction transistors(BJTs)) is transistor-transistor logic (TTL). This was first TTL

4 Logic Families

introduced in the 1960s, and has now developed into several related logic familiesthat are compatible with each other but differ in speed, power consumption andcost.

The other major logic family is based on metal-oxide semiconductor fieldeffect transistors (MOSFETs), more commonly known as the MOS transistor.MOSFETsThese devices were actually invented 10 years prior to BJTs, but did not initiallybecome popular due to fabrication difficulties. Many of these initial problemswere solved by the 1960s and number of products become available based onthis technology, although the performance lagged behind BJT based devices atthis time.

MOS transistor development continued through the early 1970s, and accel-erated at the end of the 1970s and early 1980s with the development of largescale integrated (LSI) circuits, and particularly the microprocessor. The MOStransistor is also used in a closely associated technology known as CMOS (com-plementary MOS). The advantage of this configuration of MOS transistors isthe low power dissipation that can be achieved. This is becoming increasinglyimportant as integration densities escalate, since removing the internally gener-ated heat from ICs is a problem when there are millions of transistors on a chip.By far the majority of electronic devices now produced use MOS transistors ina CMOS configuration.

There is an equivalent set of SSI (small scale integrated) circuit devicesusing CMOS technology. These devices have similar capabilities to their TTLcounterparts, and in many cases are designed to be input and output compatiblewith TTL. In fact most VLSI (Very Large Scale Integrated Circuits) are alsodesigned to have TTL compatible inputs and outputs.

1.2.2 The CMOS Logic Family

Before considering CMOS itself, let us firstly briefly review the operation of thebasic switching element in CMOS, NMOS and PMOS logic (the latter two ofthese will become obvious in the following discussion).

Consider Figure 1.1, which shows a cross section of a MOS transistor. Thisdiagram shows the basic structure of a n-channel enhancement mode MOSFETenhancement mode(known as an NMOS transistor). This is called an enhancement mode devicebecause the application of the gate voltage enhances (or creates) a channel forthe current to flow from the drain to the source. Unlike BJTs the current carriersin a MOSFET are the majority carriers (compared to minority carriers beingthe dominant current carrier in the BJT). This is achieved in the enhancementmode MOSFET by the gate voltage causing an “inversion” of the material underthe gate so that a channel is formed which allows the majority carriers in thesource well to flow to the drain well. This channel is shown schematically inFigure 1.1. Notice that the channel becomes wider towards the source where theeffect of the voltage appearing across the gate insulation is larger and thereforeis able to attract more carriers.

The terms “source” and “drain” refer to the movement of the majoritysource and draincarriers in the device. In the case of the n-channel MOSFET shown in Figure 1.1the source connection is where the electrons are generated in the device, andthe drain is where they leave the device. In this particular device, if the voltagebetween the gate and source terminals (VGS) is zero then the device will notconduct current. Under this condition there is a reverse bias diode between the

1.2 Review of Logic Family Properties 5

p

n+

Drain SourceGate++

DepletionRegion

Inducedn Channel

n+

SiliconDioxide

Insulation

VDD

VSS

VGS

Substrate

Figure 1.1: Block diagram of an enhancement mode n-channel MOSFET.

drain and the substrate. If sufficient positive voltage is applied between theseterminals then electrons are attracted under the gate area, and conversely holesare repelled. If a large enough voltage is applied then the material under thegate will change from p material to n material. Therefore there is an n-channelfrom the two n+ wells and electrons can then flow between the two.

The MOSFET of Figure 1.1 has a p substrate. An alternative is to have an substrate and p+ wells. These are known as PMOS transistors . In this case PMOS transistora p channel has to be enhanced with the application of the gate voltage, whichimplies that the gate voltage has to be negative compared to the substrate. Ifthe substrate is connected to the source then if VGS is zero then no currentcan flow (due to a reverse biased diode being formed as in the case of the n-channel device), and if VGS < Vt, where Vt is a threshold voltage then current threshold voltagewill flow. The circuit symbols commonly used for the n-channel and p-channelMOSFETs are shown in Figure 1.2. Notice that the inverted input to the p-channel MOSFET is signified in one of the symbols by an inversion circle.

The MOSFETs discussed thus far are enhancement mode devices, and theyrequire a voltage to be applied in order to turn the devices on. There areMOSFET devices that are “normally-on” devices – that is they conduct cur-rent without any applied voltage, and a voltage has to be applied to turn thedevice off. These are known as depletion mode MOSFETs as the applied volt- depletion modeage depletes an existing channel. Depletion mode devices found widespread usein early LSI technologies where they were used for providing pull-up resistors.However, all VLSI chip technology today is based on the CMOS circuit topol-ogy, which does not involve the use of depletion mode devices. Therefore thedevices will not be considered any further. The main problem with the NMOSbased technology was the power dissipation due to the voltage drop across thedepletion mode MOS transistor based resistors in these designs.

6 Logic Families

n-channel p-channel

Drain

Drain DrainSource

Source Source

Gate Gate Gate

Figure 1.2: Common circuit symbols for enhancement mode MOSFETs.

The concept of the threshold voltage (Vt) was mentioned above. This isthe voltage which causes the MOSFET to conduct a significant current. From adigital logic viewpoint the voltage which “turns on” the device is very important.Fortunately the MOSFET designer has a number of techniques of controllingVt [6]. In general the threshold voltage is a function of a number of parametersincluding the following:

• gate material

• gate insulation material

• channel doping

• impurities at the silicon-insulator interface

• voltage between the source and substrate

Two common techniques used for adjusting the threshold voltage entail vary-ing the doping concentration at the silicon-insulator interface through ion im-plantation, or using different insulator material for the gate. An example of thelast approach is to use a layer of silicon nitride (Si3N4), which has a relativepermittivity of 7.5 compared to that of silicon dioxide (SiO2) which is 3.9. Useof this is equivalent to using a much thinner gate insulator, and hence the gatecapacitance is increased meaning that for the same applied voltage more chargeis accumulated under the gate.

After our brief review of MOSFETs we will now return to the CMOS imple-mentation of MOSFETs. The abbreviation CMOS stands for ComplementaryMetal Oxide Semiconductor transistor . It refers to a configuration of MOS-Complementary

Metal OxideSemiconductorTransistor

FET transistors as shown in Figure 1.3. It is a totem pole structure in whichthe top transistor is a p-channel enhancement mode device, and the bottom de-vice is a n-channel enhancement mode device.1 This structure is a basic inverterimplemented in MOSFET technology.

1The supply voltage is denoted as VDD for historical reasons. The first MOS circuits werebased on NMOS devices where the drain was connected via a resistor to the positive supply.The VDD voltage is often called VCC .


VDD

p-channel

n-channel

Vout

Vin

Figure 1.3: CMOS inverter.

1.2.2.1 Logic Levels and Noise Margins

Logic levels and noise margins are one of the most important aspects of any noise marginslogic family in relation to interfacing members of the family together, and thereliability of operation in the presence of noise.

One of the most important characteristics of a CMOS inverter is the transfercharacteristic . A typical characteristic is shown in Figure 1.4. Emphasis should transfer character-

isticbe placed on the word typical, since the exact positioning and shape of this char-acteristic varies depending on the IC fabrication line, width to length ratios ofthe p and n transistors, doping levels, and random variations in the manufac-turing process. However a manufacturer will guarantee certain characteristicsof the circuits they manufacture.

Figure 1.4 illustrates an aspect of digital systems that is not always appre-ciated – a digital inverter is essentially an analogue inverting amplifier, albeit avery high gain amplifier.2 Ideally the transition from the high to the low levelwould be vertical (i.e. infinite amplifier gain) and ViL and ViH would be equal.

The noise margins of a digital device refer to the amount of electrical noisethat can be tolerated on the output of a device before the input of a followingdevice will see a high level as a low level, or vice-versa. The noise margins areclosely related to the transfer characteristic in Figure 1.4.

Noise margins are usually specified by two values – the low noise margin,NML and the high noise margin, NMH . The following discussion is with refer- low noise margin,

high noise marginence to Figure 1.5, which shows the generic definitions of logic levels. We needto define a few of the variables in this figure:

2The analogue amplifier properties of inverters are used when one constructs a crystaloscillator using a string of inverters

8 Logic Families

Supply current

Vout

Vin

VtnV V

DD tp

0 5. VDD

VDD

VDD

Slope=-1

ViL

ViH

Figure 1.4: Typical transfer characteristic for a CMOS inverter.

VIHmin = minimum HIGH input voltageVILmax = maximum LOW input voltageVOHmin = minimum HIGH output voltageVOLmax = maximum LOW output voltage

Given these definitions we can now formally define the noise margins:

NML = |VILmax − VOLmax | (1.1)NMH = |VOHmin − VIHmin | (1.2)

Therefore NML is the difference between the highest low level voltage thatthe CMOS output produces and the highest input voltage that the CMOS inputwill still recognise as a low (i.e, any higher voltage cannot guaranteed to be seenas a low). Similarly NMH is the difference between the lowest output voltagethat can be produced, and the smallest input voltage that is still recognised asa high input.

As an example of typical values let us consider the HC-series CMOS familyoperating with a 5V supply voltage.

VOHmin The minimum output voltage in the HIGH state is 4.9V.

VIHmin The minimum input voltage recognised as a HIGH is 3.5V.

VILmax The maximum input voltage recognised as a low is 1.5V.

VOLmax The maximum output voltage in the LOW state is 0.1V.

Using these values for the various voltage levels together with 1.1 and 1.2one can see that NML = 1.4V and NMH = 1.4V , which is not only symmetric


Indeterminateregion

Logical lowoutputrange

Logical highoutputrange

VSS

or GND

VDD

Logical highinputrange

Logical lowinputrange

NMH

NML

VIHmin

VILmax

VOHmin

VOLmax

Input characteristicsOutput characteristics

Figure 1.5: Noise margin and generic logic level definitions.

but is also an excellent level of noise margin for a component working on a 5Vsupply voltage.

An important point not mentioned in the above paragraph is that the outputvoltages (either min or max values) are specified under certain loading condi-tions, which are specified in the manufacturers data sheet. The load is specified loading conditionsin terms of currents:

IOLmax The maximum current that the output can sink in the the LOW statewhile still maintaining an output voltage no greater than VOLmax .

IOHmax The maximum current that the output can source in the HIGH statewhile still maintaining an output voltage less than VOHmin .

The inputs in CMOS circuits have a very low DC current loading, althoughthe capacitive loading can be very important under transient conditions. Atypical input current value for a HC-series CMOS gate is ±1µA.

Many CMOS data sheets will contain values of IOLmax and IOHmax for bothCMOS loads as well as TTL loads. In the case of TTL loads the noise marginsare significantly degraded relative to CMOS loads. For example, if a TTL loadis connected to HC-series CMOS devices output voltage limits are: VOLmax =0.33V (compared to 0.1V with CMOS load), and VOHmin = 4.3V (compared to4.9V with a CMOS load). The effect of these changes in output voltage levelsis not obvious in quantitative terms until we consider the input performance ofTTL logic.

One can also consider the behaviour of the circuits with non-ideal inputs. non-ideal inputsThis refers to a situation where the inputs are not clamped hard to the VSS orVDD supply rails. Therefore we can have a situation where both the transistorsare both at least partially on, and therefore the outputs are created by a resistivedividing action. If there is a current sink or source load (such as a resistiveload or a TTL input) then the situation is even more complicated in termsof calculating the output voltage level. In addition the output transistors of

10 Logic Families

the CMOS devices will also be consuming power under these conditions. Ifconnected to a CMOS load there is virtually no current flowing when the logiclevels are constant, and therefore there is little power dissipation.

1.2.2.2 Fanout

The term fanout refers to the ability of a logic gate to drive a number of inputsfanoutwithout exceeding its worst case loading specifications. The fanout is clearlydependent on two things – the output drive capability and the loading of theinputs connected to the output.

As an example consider fanout of HC-series CMOS. When driving CMOSinputs the IOLmax value is 20µA giving a VOLmax of 0.1V. The inputs for theseCMOS components have a loading of ±1µA, which implies that 20 inputs canbe connected to a low output without exceeding the maximum output voltagespecification. This is called the low state fanout . Similarly the maximum highlow state fanoutstate output current is −20µA. 3 Therefore the maximum high state fanout ishigh state fanoutalso 20. This symmetry between low state and high state fanout is not usual,and therefore the overall fanout is the minimum of the two fanout numbers.4overall fanout

The fanout properties that we have just discussed is the DC fanout , sinceDC fanoutwe are considering constant output values. However, in some cases the so-calledAC fanout , which is largely determined by the capacitance of the inputs andAC fanoutthe propagation that can be tolerated. This fanout restriction occurs due tothe RC time constant issues associated with the resistance of the output stagesof the CMOS devices and the input capacitance associated with the gate ofthe inputs. Clearly as the capacitance increases then the switching edges slowdown. Therefore skew is introduced into the edges, and hence the propagationdelay of signals is increased. In addition slow edges can cause problems in noisyenvironments.fine

1.2.2.3 Specific CMOS Logic Families

Let us now briefly look at some specific CMOS logic families. We have alreadybriefly looked at the HC-series of components in the previous sections. Howeverthe first successful commercial CMOS family was the 4000-series . This family4000-seriesoffered very low power dissipation compared to the TTL family, but on thedownside it was very slow and was difficult to interface to TTL which was themost popular logic family at the time of its introduction. Consequently the4000-series was supplanted by more advanced CMOS families which will bediscussed in the remainder of this section.

A brief note on the numbering of these components. A generic number fora CMOS IC takes the form “74FAMnn”, where the ‘74’ denotes a commercialcomponent5 and the ‘FAM’ denotes the family of the component, and finally thenn denotes the particular part number. For example, we can have the followingpart numbers for CMOS 8 input NAND gates; 74HC30, 74HCT30, 74AC30,74ACT30.

The HC-series (high speed CMOS) of components were designed to work in aHC-series (highspeed CMOS)

3The sign convention for currents in digital circuits is that current flowing into the deviceis positive

4The fanout can be increased if one is willing to sacrifice noise margin.5‘54’ denotes a military specification component


CMOS only logic system. They offered higher speed and better drive capabilitiescompared to the 4000-series. The input logic levels were different than thosefor TTL, therefore interfacing this logic with TTL was problematic. The HCT-series on the other hand were designed to be compatible with TTL logic levels. HCT-seriesTherefore the inputs would work at the same voltage levels as those for TTLgates.

Introduced in the mid-1980s the AC-series (advanced CMOS) and the ACT- AC-series (ad-vanced CMOS)series (advanced CMOS TTL compatible) were very fast logic families that couldACT-series (ad-vanced CMOS TTLcompatible)

source and sink even larger currents than TTL. As with the HC-series the dif-ference between the two was that the ACT components were TTL input com-patible. The typical AC-series components have a propagation time of 5nsec fora NAND gate, as compared to 18nsec for the HC-series components. The pricepaid for this extra performance is higher power dissipation per logic cell.

In the 1990s another even faster CMOS logic family was introduced – theFCT-series (Fast CMOS, TTL compatible) . There are several different speed FCT-series (Fast

CMOS, TTLcompatible)

grades available. Compared to the AC-series this family had a significantlybetter speed-power product. The other point to note was that there are notindividual gates in this family, but it tends to concentrate on chips with acomplexity equal to a 74x138 decoder or larger.

1.2.3 Bipolar Logic Families

The bipolar logic families have a basic active unit consisting of a bipolar junction bipolar logic fami-liestransistor. There are two broad groups within this family – the TTL group and

the ECL group. We shall concentrate mainly on the former, since ECL (emittercoupled logic) tends to be esoteric and is only used in very high performanceapplications.

Figure 1.6 shows the diagram of a two input low power Schottky (LS) NAND low power Schottkygate.6 Let us briefly discuss its major internal components. The input stageconsists of four Schottky diodes and a resistor. Two of the diodes (D1X, D1Y )together with the resistor R1 form an AND gate (note that in some implemen-tations these are replaced by a multi-emitter Schottky transistor).7 The othertwo diodes (D2X, D2Y ) are there for protection from negative excursions of theinputs under transient conditions.

The output of the input stage then feeds to the phase splitter stage. Thepurpose of this stage is to convert the single signal from the input stage intothe two levels to successfully control the output stage. If any of the inputsare low (0V ) then the base voltage of Q2 is approximately 0.25V (the voltagedrop across the input Schottky diode). Therefore the Q2 transistor is cutoff.Consequently the base of Q3 is connected to VCC via resistor R2 and will beturned on. This is turn will turn on Q4 which makes the output go high.

Let us consider the situation where one of the inputs is 0.8V and the otheris higher than this. Under this condition the voltage on the base of Q2 will be0.8V + 0.25V = 1.05V . Due to the presence of Q6 it takes at least 1.2V toenable Q2 to turn on, therefore this will still be seen as a “low” input situation.

If both input voltages are 2V then the input diodes are effectively cutoff,since the diode drops across the base-emitter junctions of Q2 and Q6 mean

6A TTL inverter is formed by simply eliminating one of the inputs in the NAND gate.7One can have more inputs by simply including more diodes

12 Logic Families

V VCC

5

X

Y

Z

R k1

20 R k2

8

R k3

12

R k4

15 .

R5

120

R k7

3

R k6

4

D1X

D1Y

D2X D2Y

D3

D4Q2

Q3

Q4

Q5

Q6

[ [ [Diode AND gate

and input protectionPhase splitter Output stage

Figure 1.6: Typical circuit for a TTL NAND gate.

that the voltage at the base of Q2 cannot rise much above 1.2V . Under thiscondition Q2 turns on. Depending on how hard it is on, the voltage on thebase of Q3 will drop and that on Q5 will rise. Therefore Q3 will tend to turnoff (and consequently so will Q4 ), and Q5 will be tending to turn on. The Q6transistor is diverting current away from the base of Q5. This ensures that Q2is turned on “hard” before there is enough current to turn Q5. This in turnensures that the inputs really have to be at about 2V before this will happen.Clearly with inputs below 2V and above 0.8V it is difficult to say exactly whatwill happen. This is a grey area in the operation of TTL, and the specificationswill not say what the output will be under these conditions.

The output stage of TTL is a push-pull or totem-pole output. The toppush-pulltotem-pole two transistors are configured as a Darlington Pair to provide sufficient current

output and the dual diode drops across the base emitter junctions help preventsimultaneous turn on of Q4 and Q5. The diodes D3 and D4 are provided todischarge the stored charge in the Q4 transistor and a capacitive load, therebyimproving speed.8

Remark 1.1 A totem-pole output stage is virtually the same as the output stageon the CMOS components. Consequently it also suffers from the problem thatthere is a time during switching transients that both the top and bottom transis-tors are on at the same time. Hence there is a spike of current that flows duringthis period, which results in extra noise in the digital system. The resistor R5

8The Q4 transistor is an ordinary transistor since it cannot go into deep saturation whenconfigured in the Darlington Pair.


helps to control the magnitude of this current.

1.2.3.1 Bipolar Logic Noise Margins

Using the same broad definitions as in Figure 1.5 we can define the TTL logiclevels and noise margins as follows: TTL logic level and

noise marginsVOHmin The minimum output voltage in the HIGH state, 2.7V for most TTL

families.

VIHmin The minimum input voltage guaranteed to be recognised as a HIGH,2.0V for all TTL families.

VILmax The maximum input voltage guaranteed to be recognised as a LOW,0.8V for most TTL families.

VOLmax The maximum output voltage in the LOW state, 0.5V for most TTLfamilies.

Using (1.1) and (1.2) we can define the noise margin for TTL componentsas NMH = 0.7V and NML = 0.3V . Therefore we have non-symmetric noisemargins with this technology, resulting in the logic being more susceptible tonoise in the low state than the high state.

1.2.3.2 Fanout

The fanout restrictions for TTL are more restrictive than those for CMOS dueto the fact that substantial currents flow out of the inputs for TTL.

The amount of current flow for a TTL component is different depending onwhether the input is a high or low value:

IILmax This is the maximum current that an input requires to pull it LOW. Fora LS-TLL component a typical value is −0.4mA. 9

IIHmax This is the maximum input current required in a HIGH state. This isessentially the current that leaks through the reverse biased input diodes.Typical values for LS-TTL is +20µA.

The other aspect to the determination of fanout is the output drive capa-bilities of the circuits. As with the inputs there is an asymmetry in the outputdrive of TTL:

IOLmax The maximum output current that one can sink in the LOW state whilststill maintaining the VOLmax output voltage. Typical value is 8mA for LS-TTL.10

IOHmax The maximum current that can be sourced in the HIGH state whilstmaintaining a minimum output voltage of VOHmin . A typical value is−400µA for LS-TTL.

If one examines the asymmetric input and output behaviour of TTL then itcan be seen that the LOW and HIGH fanout are the same at 20.11 LOW and HIGH

fanout9The current convention is that current flowing into a TTL IC is positive.10Because TTL can sink large amounts of current (as compared to sourcing current) it is

known as current sinking logic.

14 Logic Families

Note 1.1 The asymmetric output of TTL can cause problems in some applica-tions. For example if one wishes to drive a LED or relay then one cannot usecurrent sourced from a TTL component to do this. One would have to arrangethe circuit so that the current sinking capability can be utilised. Clearly therewould be a problem driving high capacitance loads as well, since the switchingedge would be rather slow under these circumstances.

Practical Issue 1.1 Unused inputs in TTL circuits should be tied to an appro-priate logic level (as was the case with CMOS circuits). However, if an inputshould be tied HIGH it is better to tie it via a pull-up resistor . In theory this ispull-up resistornot required, and we could tie the input directly to the VCC supply rail. However,if the input transiently goes above 5.5V then damage to the input may result. Apull-up resistor limits the current that can flow in this situation and preventsdamage. The value of the resistor is also important as well since the inputs takea significant amount of current in the HIGH state. Therefore the resistor mustbe chosen so that the input is well within the range of the logic value required.

One can also have a pull-down resistor. However the same overvoltage issuedoes not apply so a LOW input is often tied to the GND supply. A pull-downcan be used if one wishes to drive the tied input in a testing situation, althoughone is sacrificing some noise margin in order to achieve this. For example a1kΩ pull-down resistor would give a low voltage of approximately 0.4V.

1.2.3.3 Specific TTL Logic Families

As was the case with CMOS there are a number of families or groups of com-patible components within the general TTL family. We shall not go throughthe original TTL family as it is no longer used, but instead briefly mentionthe contemporary families, which all use Schottky transistors, and vary in theinternal resistor values and transistor feature sizes. This results in differentspeeds and speed-power products for the different families. Similarly to theCMOS logic numbering system those for TTL components have the generic form“74FAMnn”, where the “FAM” is one of “AS” – advanced Schottky, “ALS” –advanced low power Schottky, and “F” – fast TTL.12 The “F” components arepositioned in terms of speed-power product between “ALS” and “AS”.

Typical propagation delays for a NAND gate are: AS: 1.7nsec; ALS: 4nsec;propagation delaysF: 3nsec.

1.3 Issues in TTL–CMOS Interfacing

Although most designers attempt to design a circuit using one logic family, thereare occasions when components from other logic families may be used. Underthese circumstances it is important to understand the implications of connectingdifferent logic families.

The logic level specifications for each of the logic families are summarisedin Figure 1.7. Note that these values are worst case values for TTL loading . InTTL loadingthe case of the HC-series CMOS components we are assuming that the supply

11Note that in mixed TTL circuits (i.e. LS, S, AS etc components), one must add up theindividual input loadings to determine the fanout that can be achieved.

12Low power Schottky (LS) components were for many years the technology of choice forTTL designs. However, both in speed and power performance ALS has largely replaced LS.

1.3 Issues in TTL–CMOS Interfacing 15

OUTPUTS INPUTS

5.0

3.843.76

2.7

0.50.370.33

3.85

2.0

0.8

1.35

0

HC, HCTAC, ACT

LS, S, ALS,AS

VOHmin

LS, S, ALS,ASAC, ACTHC, HCT

VOLmax

HC, AC

LS, S, ALS,AS, HCT,

ACT

LS, S, ALS,AS, HCT,

ACT

INDETERMINATE

TTL LEVEL

VIHmin

HC, AC

VILmax

Low Levels

High Levels

Figure 1.7: Worst case logic levels with TTL loadings.

is between 4.5V and 5.5V . By comparing the output max or min logic levelson the left side of this figure with the appropriate max or min value on theright side one can calculate the worst case DC noise margins for the various worst case DC

noise marginslogic families. Furthermore, one can also calculate the noise margins when logicfamilies are mixed.

One interesting case of mixing logic families is TTL and HC-series CMOS.Recall that HC-series CMOS was not designed to be TTL compatible. Theproblems can be seen by looking at the HIGH level performance. HC-seriesCMOS is not guaranteed to see a HIGH until 3.85V is on the input, but TTLoutputs are guaranteed to only produce 2.7V . Even the CMOS TTL compatiblefamilies will not produce enough voltage to trigger the HC-series CMOS inputunder TTL loading conditions. Even if they did there would be virtually no DCnoise margin.

Practical Issue 1.2 If one had to interface a TTL output to a HC-seriesCMOS input then one way of achieving reliable operation would be to use apull-up resistor. The value could be chosen so that the sink current specifica-tions for the TTL would not be exceeded, and at the same time the fastest risetime would be achieved. The Low to HIGH switching edge would have two sec-tions – a fast section when the output is driving it, and a slower stage as thepull-up resistor charges up the output. The success of this would depend on theload capacitance, since a larger capacitance may slow down the second sectionof the edge unacceptably.

Another factor to consider is the fanout . This is especially true in the case fanoutof interfacing CMOS outputs with TTL inputs, since the latter source muchmore current than CMOS inputs when held in the LOW state. Each loadingsituation must be considered individually, and is dependent on the mix of logictypes. For example, the 74HC or HCT output can drive 10 74LS but only two74S loads. Note that we are assuming the VOLmax = 0.5V for this condition,and IOLmax = 0.8mA.

16 Logic Families

The last factor to consider is the capacitive loading of the inputs. This isespecially important when using the HC-series of components, since there isabout a 1nsec increase in rise times for every 5pF of load capacitance.

Note 1.2 With CMOS logic it is possible that poor quality inputs (e.g. a HIGHinput near 2V ) can result in both the top and bottom transistors being on tosome extent. This results in a larger than usual current flowing through theoutput in steady state and therefore the IC may heat up considerably.

Practical Issue 1.3 A price that one pays when mixing TTL with a CMOSdesign is the loss of noise margins. Therefore, if noise immunity is a majorissue in a design then it is better to use a CMOS logic only design, and use theCMOS family that is designed to only work with other CMOS components (HCor AC-series), since these have the highest noise margins.

Of course if one resorts to the HCT, ACT etc. families of CMOS then oneimmediately has the noise margins of TTL. The only benefits gained are in thepower consumption area.

Chapter 2

Introduction to DigitalSwitching

2.1 Introduction

This chapter introduces some of the concepts and background material requiredto understand future chapters. In addition some rules of thumb will be intro-duced, and backed up where appropriate by simulations to demonstrate theparticular effect that the rule relates to.

This chapter essentially covers a variety of issues that tend to be left out ofmost digital systems courses. The chapter considers the effects that the rapidrise times of digital signals have on the operation of digital systems. There-fore the emphasis is on self induced “noise”, rather than externally inducednoise. This noise takes to various forms from transmission line effects throughto ground bounce and crosstalk. The approach when considering these issues isvery practical, and where appropriate suggestions are made as to how a designcan be altered to minimise problems related to high speed switching.

Much of this chapter is based on [1] which is an excellent reference on highspeed digital design.

2.2 Relevant Frequencies

One of the key issues in digital systems design is the relationship between thefrequency content of digital signals and the properties of the lines that they haveto propagate down. We shall look at the first of these issues in this section.

To some people it seems strange that the frequency content of a digital signalis not related to the frequency of the digital signal. The frequency content weare interested in is related to the switching edge rate of rise . It can be shown switching edge rate

of risethat the power spectral content of a random digital waveform being clocked atsome rate Fclock has a knee point at some frequency. If the frequencies abovethis knee point are ignored then this has very little effect on the time domainrepresentation of the digital signal. There is a very simple formula to find outwhat the knee frequency is given the rise time of a digital signal [1]:

18 Introduction to Digital Switching

Fknee =0.5Tr

(2.1)

where:

Fknee frequency below which most of the energy in digital pulsesis concentrated

Tr pulse rise time

The ramifications of equation (2.1) are:1

1. If a circuit has a flat frequency response up to the Fknee then it will passa digital signal practically undistorted.

2. The behaviour above Fknee of a digital circuit will have little effect on howit processes digital signals.

Equation (2.1) can be used as a rule-of-thumb for determining whether onehas to worry about high frequency effects in a digital system.

Another interesting figure of merit that comes from the analogue electronicsworld is the relationship between the -3dB bandwidth and the rise time of asignal:

F3dB ≈ K

Tr(2.2)

where:

F3dB frequency at which the impulse response (i.e. the frequency response)rolls off by 3dB

K depends on the type of pulse shape – 0.338 for gaussian pulsesand 0.35 for single pole exponential decay

Another measure of bandwidth that is used by some manufacturers is theequivalent noise bandwidth, or the RMS bandwidth.2 In this case the relation-ship is:

Tr ≈ K

FRMS(2.3)

where:

FRMS RMS bandwidth

Tr rise time (10%-90%)

K depends on the pulse shape – 0.361 for gaussian pulsesand 0.549 for single pole exponential decay

1The Fknee frequency in (2.1) is only related to the rise time of the digital waveform, andnot the clocked frequency of the waveform

2The noise bandwidth of a frequency response H(f), or the RMS bandwidth, is the cutofffrequency at which a box-shaped frequency response would pass the same amount of whitenoise energy as H(f).

2.3 Propagation, Time and Distance 19

Delay Relative DielectricMedium (ps/cm) constantAir 33.5 1.0Coax cable (75% vel) 44.5 1.8Coax cable (66% vel) 51 2.3FR4 PCB, outer trace 55–71 2.8–4.5FR4 PCB, inner trace 71 4.5Alumina PCB, inner trace 94.5–106 8–10

Table 2.1: Propagation delays for electromagnetic fields in various media.

2.3 Propagation, Time and Distance

Another very important aspect to the propagation of digital signals is the dis-tance that a signal propagates and the time it takes to propagate this distance.As we shall see these quantities are very important in determining whether wecan consider a digital system in terms of lumped parameters, or whether we haveto consider the propagation paths as distributed transmission lines. Table 2.1shows propagation delays for a variety of media encountered in digital systems. propagation delays

Remark 2.1 Propagation delay increases in proportion to the square root ofthe dielectric constant of the surrounding media. Therefore a coaxial cable man-ufacturer will attempt to make the dielectric media have a dielectric constant asclose to that of air as possible in order to minimise the propagation delay.

Notice that the outer trace figure for the printed circuit board track has afaster propagation velocity as compared to the inner track. This is due to thefact that more of the field produced by the outer track is in air, and thereforethe overall dielectric constant is lower (v = c/

√εreff

).

2.4 Lumped Versus Distributed Systems

Now that we have considered the frequencies that are relevant in a digital systemvia (2.1), and we understand that the digital waveforms propagate at differentvelocities depending on the media that the wave is travelling through. This thennaturally leads to the concept of lumped versus distributed representations of apropagation medium.

Whether we can consider a medium to be represented as a lumped circuit or lumped circuitas a distributed circuit depends on how “long” an edge is in the medium. This distributed circuitconcept is best understood via an example. However, before doing this we willwrite down a few of the basic expressions for transmission lines. The expressionfor characteristic impedance is: characteristic

impedance

Z0 =√

L0

C0(2.4)

where:

L0 line inductance per unit length

C0 line capacitance per unit length


The total delay for the transmission line is calculated using the formula: total delay

Td = l√

L0C0 (2.5)

where l length of the transmission line. Clearly this means that the velocityof propagation in the transmission line is:

v =1√

L0C0

(2.6)

Note 2.1 Equation 2.5 is the total line delay. Therefore the delay per unitlength is D =

√L0C0 ⇒

√L0C0 =

√εr/c.

As an input pulse to a transmission line is rising from a low value to a highvalue the pulse is actually travelling down the transmission line. Therefore weend up with the pulse distributed with respect to distance down the transmissionline. The length of the rising edge of a pulse is:length of the rising

edgelr =

Tr

D(2.7)

Example 2.1 Consider a transmission line with the following parameters; L0 =4.6nH/cm and C0 = 1.1pF/cm. This transmission line was approximated usinga series of LC elements as shown in Figure 2.1. Note that there is no induc-tance in the ground. Therefore we are assuming that there is a ground planesufficiently wide so that its inductance can be ignored. The simulations of theline were carried out in the simulation package called Saber.

Let us firstly work out a couple of the parameters for the line before weexamine the simulation plots. Using (2.4) we can determine that Z0 = 64Ω.Using (2.5) the line delay is Td = 782ps, and the delay per cm is 71ps.

v_pulseinitial:0pulse:5

4.6e-9 4.6e-9 4.6e-9 4.6e-9 4.6e-9 4.6e-9 4.6e-9 4.6e-9 4.6e-9 4.6e-9 4.6e-9p1

1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12

p2 p3 p4 p5 p6 p7 p8 p9 p10 p11

64

Length = 11cm

t_r:0.5ns

Figure 2.1: Approximate transmission line.

Figure 2.2 shows a series of voltage versus time plots for the ‘p’ points fromFigure 2.1. The initial input voltage has a rise time of 0.5nsec. Notice thesuccessive delay of the signals further down the transmission line. The totaldelay can be visually seen to be approximately 800psec, which is very near thetheoretical calculation of the delay. The length of the pulse rising edge down thetransmission line is from (2.7) calculated as 7cm.

After some processing of the voltage versus time plots of Figure 2.2 one cangenerate voltage versus transmission line distance plots for various times afterthe application of the voltage signal. Three of these plots are shown Figure 2.3.Notice that the voltage propagates down the transmission line, and at varioustimes before the voltage eventually stabilises at 5V the voltage is not uniform

2.5 Four Kinds of Reactance 21

with distance along the line. Furthermore the length of the voltage edge is ap-proximately 6cm (compared to the theoretical calculation of 7cm for an idealtransmission line). At 410psec the pulse has not risen to 5V because of the500psec rise time of the input voltage (which is typical for a digital logic signal).

As one looks at Figure 2.3 the question of what constitutes a transmissionline comes to mind. In other words when does one have to consider a lineto be behaving as a transmission line, and when can a circuit be consideredas a lumped circuit. The normal rule of thumb used is that a circuit can beconsidered as a lumped circuit if the line length is l/6, where l is the length of lumped circuitthe rising edge defined by (2.7). The meaning of this can be seen in Figure 2.3,where we look at a length of short line which is approximately l/6 in length.Notice that over this length of line that the voltage difference across the line isapproximately 0.9V. Therefore the voltage differences at points along the shortline are not nearly as large as for the longer line. However, the point wherewe say that these differences are small enough to ignore is to a large extentarbitrary.

Remark 2.2 An ideal lumped circuit does not have any propagation delay. Inothe words the input signal is the same at all points in the lumped circuit. Clearlyno circuit behaves in this way, but if the circuit dimensions are small relative tothe length of the rising edge then the circuit can be approximated as a lumpedcircuit.

2.5 Four Kinds of Reactance

Reactive effects are very important in relation to the operation of digital circuits.The reactive effects can be classified into four categories:

• Ordinary capacitance.

• Ordinary inductance.

• Mutual capacitance.

• Mutual inductance.

2.5.1 Ordinary Capacitance

The term ordinary capacitance refers to a capacitance between elements of thesame circuit. This almost always means the capacitance between the positivepart of the circuit and the ground point of the circuit. This capacitance canbe the result of a circuit component (a capacitor) or is can be a parasitic effectbetween wires or wires and a ground plane.

The following is a quick review, since electrical engineers should already befamiliar with most of this material. Consider a circuit of the form shown inFigure 2.4. Capacitive effects can be recognised in a circuit by the following:

1. A step change in voltage across a circuit that is primarily capacitive resultsin an initially high current flow, limited only by the resistance in thecircuit.


Voltage sourcepulse p1 p11

Td ª 800psec

6.0

5.0

4.0

3.0

2.0

1.0

0.0 200p 400p 600p 800p 1n 1.2n 1.4n 1.6n 1.8n 2.0n

t(s)

Figure 2.2: Time domain plots of voltages along a transmission line.

0 2 4 6 8 10 120

1

2

3

4

5

6

Position down the tx line (cm)

Vol

tage

(V)

410psec

602psec

906psec

Short line - 1cm =71psec

Short linevoltagedifferential

Figure 2.3: Voltage versus distance along a transmission line.


2. As t → ∞ the current through the circuit approaches zero – i.e. thecapacitor becomes an open circuit.

3. At t = 0+ the voltage across the capacitor is zero.

4. As t → ∞ the voltage across the capacitor approaches the applied circuitvoltage.

Most of the features in Figure 2.4 can be deduced from the basic equationfor a capacitor:

ic(t) = Cdvc(t)

dt(2.8)

For a circuit such as that of Figure 2.4 one has an exponential rise in thevoltage across the capacitor. Assuming a infinitely fast rise time for the inputwaveform the voltage across the capacitor and the current into the capacitorcan be shown to be:

vc(t) = V (1 − e−t

RC ) (2.9)

ic(t) =V

Re−

tRC (2.10)

Of course the waveforms are more complex when one has a rise time onthe input waveforms. Equation (2.9) can be used to find the approximate ca-pacitance associated with a circuit by considering the time constant of a risingsignal. Of course one must know the resistance in the circuit in order to do this.

Note 2.2 Capacitive circuits at high frequencies contain a mixture of effectsfrom inductance and capacitance. For example, the leads into a capacitor havesome inductance. If a edge with a fast rise time is applied to a capacitive circuit,and if a oscilloscope of sufficient bandwidth is used then one will see a shortinductive voltage “spike” at the beginning of the exponentially rising voltageacross the capacitor.

2.5.2 Ordinary Inductance

The treatment here is similar to that in the previous section on capacitance.The following discussion is with reference to Figure 2.5. As can be seen fromthis diagram the inductor is essentially an open circuit at the switching tran-sient. However, as time proceeds the inductor impedance drops and eventuallythe inductor is a short circuit, with the circuit current being limited by theresistance.

The basic equations for an inductor are:

vL(t) = Ldi

dt(2.11)

With the inductor in the circuit of Figure 2.5 we can write the followingexpressions for the voltage across the inductor and the current through theinductor (assuming the the rise time of the input voltage is zero):


R

+

-

V t( )

V t( )

C V tc( )

V tc( )

+

-

i tc( )

i tc( )

V t

i tc

c

( )

( )

Initiallyshort circuit

Starting tobecome anopen circuit

Current decays to zero

Voltage becomes V t( )

Figure 2.4: Examples of capacitive circuit waveforms.


R

+

-

V t( )

V t( )

V tL( )

V tL( )

+

-

i tL( )

i tL( )

V t

i tL

L

( )

( )

L

V t

R

( )

Output voltage decays to zero

Current approaches

Long-term impedanceis zero

Inductor essentially opencircuit here

Figure 2.5: Examples of inductance circuit waveforms.


vL(t) = V e−tRL (2.12)

iL(t) =V

R(1 − e−

tRL ) (2.13)

In order to evaluate the inductance of a circuit one could again use the timeconstant of the exponential rise of the current, or the exponential fall of thevoltage. These measurements are often difficult to make accurately. A bettertechnique is based on the area under the voltage response of the circuit. Thevalidity of this method is shown via the following analysis.

Consider the expression for the area under the inductor voltage :area under the in-ductor voltage ∫ ∞

0

vL(t)dt = L

∫ ∞

0

diL(t)dt

dt (2.14)

∴∫ ∞

0

vL(t)dt = L(iL(∞) − iL(0)) (2.15)

Therefore one can see that the area under the inductor voltage curve is equalto the total change in current through the inductor multiplied by the inductancevalue. Hence one can write:

L =[area∆iL

](2.16)

where ∆iL = iL(∞) − iL(0).Equation 2.16 can be further refined if we use the fact that the resistance is

known (as this test is usually carried out in a test circuit where we select theresistance). Therefore we can write:3

∆IL =∆VL

R(2.17)

where ∆V = vL(0) − vL(∞). This allows (2.16) to be written as:

L =[(area)R

∆VL

](2.18)

Practical Issue 2.1 Equation 2.18 allows a noise free evaluation of the induc-tance, as the area calculation effectively filters noise from the measurements.

Note 2.3 Equation (2.18) is only valid when the circuit with the inductancehas only a resistive element. If a capacitor, for example, is included then theexpression does not give the correct result.

Practical Issue 2.2 It is often useful to be able to guesstimate the inductanceof a length of wire. The bottom line is that a wire loop has approximately 0.5–1µ-henries of inductance per metre of length, or 5–10 nano-henries of inductanceper centimetre. The variation is due to wire spacing, wire diameter and shape

3Equation (2.17) implicitly depends on the fact that iL(0) = 0 and iL(∞) = V/R andvL(0) = Vin and vL(∞) = 0. Therefore ∆VL = Vin.


of the loop of wire. For loops with a large diameter the inductance is a weakfunction of the wire diameter (as one would intuitively reason).

In order to place this guesstimate on a more sold theoretical footing let usconsider the approximate inductance of a circular loop of wire with a loop radiusof “a” and a wire radius of “R” [7]:

L = µ0a[ln(

8a

R

)− 2] (2.19)

Using this expression the inductance of a 1 metre circumference loop of 14gauge wire is 1.07 µH; for 16 gauge wire it is 1.12µH and for 18 gauge wire it’s1.16µH. Note the weak dependence of inductance on wire diameter. This is dueto the natural log in the expression.

For two parallel wires, spaced d metres apart, each wire with radius R andwith line length l metres the inductance of the loops is [7]:

L =(

µ0l

π

)ln(

d

R− 1

)(2.20)

Applying this formula to the situation of parallel wires with l = 0.5metreand a wire-to-wire spacing d = 1cm, we get L0 = 0.485µH for 14 gauge wire;L0 = 0.53µH for 16 gauge wire; and L0 = 0.58µH for 18 gauge. Therefore theinductance is approximately 0.5µH per metre (or 5nH per cm) for the total wirelength.

When we have closely spaced wires we get partial field cancellation. Forexample if the wires are co-incident then we get total field cancellation (and nonet current of course). This effect can be seen diagrammatically in Figure 2.6where the field is reinforced in between the conductors, but cancels on eitherside of them. The area between the conducts obviously becomes smaller as theconductor spacing decreases, and would be zero if they are co-incident. Becausethe area decreases and more of the field lines are cancelled as the conductors aremoved closer, then the inductance falls (as noted above).

Another useful expression is for the inductance of a rectangular loop withdimensions of length “x” centimetre and width “y” centimetre and the wire hasa diameter of “d” centimetre [1]:

L = 4 × 10−9

x ln

[2y

d

]+ y ln

[2x

d

](2.21)

where L inductance in Henry.The expression for the inductance of a round wire sitting above a ground

plane (this is a good model for a wire wrap on a wire wrap board) is [1]:

L = 2x ln[4h

d

]nH (2.22)

where h the height of the wire above the ground plane; d the diameter ofthe wire; x the length of the wire in centimetres.


Field cancellation

Field reinforcement Conductors

Field lines

Figure 2.6: Field reinforcement and cancellation with parallel conductors.


2.5.3 Mutual Capacitance

Mutual capacitance refers to the inevitable parasitic capacitance that exists parasitic capaci-tancebetween any two elements in a circuit. Voltages in one circuit can result in

voltages and currents in the other circuit due to the coupling effect of thiscapacitive element. The physical mechanism of this interaction is the electricfields associated with the mutual capacitance.

The current that flows through the mutual or parasitic capacitance of obeysthe same circuit equation as the ordinary capacitance expression:

im = CmdvAB

dt(2.23)

where:

im current flowing through the capacitor.

Cm the parasitic capacitance (Farads).

vAB the voltage across the capacitance.

Equation (2.23) is an exact value of the current flowing through the ca-pacitor. However, under certain assumptions one can ignore the difference involtages across the capacitor and assume that the current is due solely to thevoltage change in circuit A or B. If we assume that circuit A is the circuit withthe voltage change then the assumptions are:

1. The coupled current flowing in Cm is much smaller than the primary signalcurrent in circuit A. Therefore the capacitance does not load circuit A.

2. The signal voltage coupled in circuit B is smaller that the signal on A.Therefore the small coupled voltage in B can be ignored and the voltageacross the capacitor can be considered to be vA. Note that this is alsomaking an assumption about the impedance to ground of circuit B.

3. The capacitor is a large impedance compared to the impedance to groundof circuit B. The noise voltage is calculated as the noise current im timesthis impedance. Other interactions with the functioning of the secondarycircuit are ignored in this analysis.

Remark 2.3 When the coupled noise voltage is less than 10% of the signal stepsize these approximations are accurate to about one decimal place. This is goodenough to tell whether one has a problem with coupled noise. If the coupling isgreater than 10% then a digital circuit probably won’t work anyway.

2.5.3.1 Relationship between Mutual Capacitance and Crosstalk

If ones knows the mutual capacitance (Cm), the rise time of the interferingwaveform (Tr), and the impedance of the receiving circuit (RB), then one canestimate the crosstalk as a fraction of the interfering waveform (vA).

Therefore one can write:dvA

dt≈ ∆V

Tr(2.24)

where ∆V the height of the driving waveform.


Therefore the mutual capacitance current is:

im ≈ Cm∆V

Tr(2.25)

The crosstalk expression can now be written by realising that the capacitorcurrent im flows through the circuit B impedance to ground, thereby generatinga voltage equal to imRB. Therefore crosstalk is this voltage relative to thedriving voltage:

Crosstalk =RBim∆V

=RBCm

Tr(2.26)

In situations where there are multiple sources of crosstalk simply algebraicallyadd together the crosstalk from all the sources to get the total crosstalk.

One can develop an expression similar to that of (2.18) for the capacitance.Using (2.23) one can can write an expression for the integral of the currentthrough the capacitor:4∫ ∞

0

im(t)dt = Cm

∫ ∞

0

dvA

dtdt

∴ 1RB

∫ ∞

0

vRB(t) dt = Cm[vA(∞) − vA(0)] = Cm∆V (2.27)

Rearranging (2.27) we can write:

Cm =voltage area across RB

RB∆V(2.28)

One can then substitute (2.28) into (2.26) to get the crosstalk .crosstalk

Example 2.2 This example comes from [1]. Consider the situation in Fig-ure 2.7, which depicts two resistors on a FR-4 printed circuit board (which is a0.063in thick epoxy board). Note that the board has a ground plane on the non-component side. We are interested in the coupling between the two 1/4 wattresistors R2 and R3. R1 is on the board to terminate the driving signal fromthe pulse generator.

Consider that the signal generator drives the a 2.7V signal with a rise timeof 800ps. We can simulate this situation to get some idea of what would happen(in [1] experimental data is presented). An approximate circuit for the situationin Figure 2.7 is shown in Figure 2.8. This circuit has been implemented in theSaber simulation package. If we integrate the area under the voltage across theRB resistor then we should be able to estimate the coupling capacitance.

Figure 2.9 shows the output of the simulation with the resistors in Figure 2.8each being 25Ω and the mutual capacitance 0.4pF. Note the plot of the integral ofthe output voltage – its value is 54pV-sec. To work out the mutual capacitancewe use this value in (2.28):

Cm =54 × 10−12

50 × 2.7= 0.4pF (2.29)

4We will be using the fact that im(t) = vRB(t)/RB .


Therefore the calculation predicts the correct value for the capacitance.The cross coupling can be evaluated using (2.26):

Crosstalk =RBCm

Tr=

(50 × 0.4pF )800ps

= 0.025 (2.30)

One interesting point about Example 2.2 that was not obvious is that it doesnot matter where one imagines the coupling capacitor to be in relation to theresistors. For example, if we imagine that the effective capacitor is connectedas shown by the dashed capacitor in Figure 2.8 and we carry out the samesimulation then for all practical purposes the plots we obtain as exactly the sameas those obtained for the first case. This seems counter intuitive at first since inthis configuration we have halved the amount of resistance in the circuit. Thereis little difference however because it is the effective impedance of the capacitorthat is dominating the circuit. This dominance together with the ramping inputvoltage effectively makes the voltage source capacitor combination behave as ahigh impedance source – i.e. as an effective current source. Therefore thecurrent flowing in the load resistance is not effected by the change in the overallcircuit resistance.

From pulsegenerator

To oscilloscope

R1

50

R2

R2

R3

R3

Cm

Cm

50

RB

50

0.063in

0.1in

Solid ground plane

Figure 2.7: Mutual coupling example between resistors.

The effective impedance of the capacitor to the rise edge of the voltage canbe roughly calculated by evaluating the frequency content of the edge using(2.2). Applying this to the test waveform we find that the frequencies in the


V

50

50

R3

R2

Cm

Other parasitics

Outputvoltage

Figure 2.8: Equivalent circuit for mutual capacitive coupling example.

0.0

20p

40p

60p

(1.1558n, 53.944p)

(A) : t(s)

(V*sec) : t(s)

integ(output_voltage)

-0.002

-0.001

0.0

0.001

0.002i(m)

0.0

0.02

0.04

0.06

0.08(V) : t(s)

output_voltage

Centre tap capacitor (25 Ohm)

0.0

1.0

2.0

3.0

4.0(V) : t(s)

input_voltage

0.0 500p 1n 1.5n 2n

t(s)

Figure 2.9: Simulation plots for capacitor cross coupling.


signal go to 437.5MHz – i.e. the -3db point in the signals frequency content. Ifwe consider a sine wave at this frequency then the impedance magnitude of thecoupling capacitor is (using the standard impedance expression):

Zceff =1

ωCm(2.31)

=1

2π × 437.5 × 106 × 0.4 × 10−12

= 909Ω

which is much greater than the total resistive component of 100Ω. Hence thecurrent flow is governed totally by the rate of change of voltage across thecapacitor. This can be checked by calculating this rate of change and using itin (2.8). Therefore we have:

icm= Cm

dvcm

dt

= 0.4 × 10−12 2.7800 × 10−12

= 0.00135A (2.32)

which is the same number as can be seen in the capacitor current plot of Fig-ure 2.9. We can assume that all the voltage appears across Cm because of itsrelative impedance compared to the resistors.

Note 2.4 The above example is implicitly using the assumptions list in Sec-tion 2.5.3. The low values of the resistors in the circuit compared to the effectiveimpedance of the capacitor means that the current flowing through the parasiticelement is small compared to main current flowing in the pulse generator sectionof the circuit. In other words the mutual capacitance does not load down thecircuit. This is another way of reasoning that we can use the driving voltageas the voltage across the capacitor (instead of having to calculate the voltage).However, if the resistive impedances were significantly larger then we could nolonger use this assumption.

What happens if we ground the floating end of the R2 and R3? Looking atthe situation intuitively, the voltage appearing at the mid point of R2 would behalved by voltage division. The current flowing through Cm capacitor woulddivide in circuit B in two directions. One path is directly to ground via onehalf of the R3 resistor , and the other is into the oscilloscope. Due to the rela-tive magnitudes of the resistors current division results in 3/4 of the capacitorcurrent flowing into the grounded resistor and 1/4 flowing into the oscilloscope.Therefore the voltage in the oscilloscope would be 1/8th of the original voltage.We shall test this reasoning via the simulation.

Modifying the circuit as described we get the results shown in Figure 2.10.As can be seen from this figure the output voltage is approximately 1/8th thatin Figure 2.9 verifying the heuristic discussion in the paragraph above.

Note 2.5 If the coupling capacitance was to be calculated in this case then onehas to halve the circuit A voltage (to account for the grounding in this circuit)


and take into account the current division in circuit B. One cannot blindlyapply the integration of the output voltage technique without accounting for theimpedances in the circuits.

Centre tap cap-resistor to gnd

-200u

0.0

200u

400u

600u

800u

(A) : t(s)

i(m)

0.0

0.002

0.004

0.006

0.008

0.01

(V) : t(s)

output_voltage

0.0

(V) : t(s)

input_voltage

1.0

2.0

3.0

t(s)

0.0 500p 1n 1.5n 2n

Figure 2.10: Relevant capacitive coupling waveforms with resistors grounded.

2.5.4 Mutual Inductance

Whenever we have current flowing in a circuit there is magnetic flux producedaround the conductor. We can influence the magnitude of the flux densityproduced by changing the dimensions of the conductor and arranging the returncurrent path so that we can get some cancellation effects.

When the flux density produced by one conductor-current combination in-duces a voltage and/or current into another conductor that is not part of thesame circuit then we say that we have mutual inductance coupling between themutual inductance

coupling two circuits.The magnitude of the mutual inductance coupling is related to two variables

– a coefficient called the mutual inductance between the circuits, and the timemutual inductancerate of change of current in the originating circuit. The mutual inductancecoefficient measures the flux per unit current linking the coupled circuit, andhas the units of Henries or volt-seconds/amp.


Remark 2.4 Two circuits with mutual inductance between them is analogous toa very small air cored transformer, where the originating circuit is the primary,and the coupled circuit is the secondary. As in the transformer situation, themutual inductance coefficient has the same value regardless of which circuit isthe primary.

A mutual inductance Lm between circuit A and B injects a noise voltage vm

into B proportional to the rate of change of current in circuit A according tothe mathematical relationship:

vm(t) = LmdiA(t)

dt(2.33)

Remark 2.5 Equation 2.33 is exactly the same equation as the standard in-ductance equation.

Remark 2.6 Equation 2.33 demonstrates the fact that rapid changes in thecurrent in circuit A will induce substantial voltages in circuit B, even underconditions of very low Lm. Hence the importance in digital circuits.

Practical Issue 2.3 In digital systems the mutual inductive coupling is usuallylarger than the capacitive mutual coupling.

Figure 2.11 shows a typical situation in a digital circuit where mutual induc-tive coupling may occur. Notice that the voltage induced effectively appears inseries with whatever voltage is being produced at the source end of circuit B.Depending on the direction of the current the induced voltage may add to thesource voltage of circuit B, or it may subtract. Another fact that can be seenfrom the figure is that current in circuit B can influence the current in circuit A(using the same mutual inductance process). However, in the following analysiswe shall make some assumptions so that these effects can be ignored.5

One can use (2.33) to carry out mutual inductance calculations in digitalcircuits under the following assumptions: assumptions

1. The voltage induced due to Lm is much smaller than the primary signalvoltage. Therefore the presence of Lm does not load down circuit A. Thenoise voltage coupled to circuit B is always smaller than the signal voltagein digital products.

2. The coupled signal current in circuit B is smaller that the current in A. Wecan ignore the small coupled current in B and assume that the differencebetween the primary and secondary currents is iA.

3. Assume the secondary impedance is small compared to the impedance toground of circuit B. The coupled voltage is added to the circuit B sourcevoltage, and interactions of the coupled voltage with circuit B are ignored.

Remark 2.7 The above assumptions, if true, mean that we can consider whatis happening in circuit A without having the worry about the reciprocal effectsfrom circuit B back into A. This greatly simplifies thinking about these effects,and gives answers that are accurate enough to allow one to find out if there isa mutual inductance coupling problem. The assumptions made in Section 2.5.3in relation to mutual capacitance also allowed this to be done in that case.

5These are similar to the assumptions made in the capacitive coupling case.


Lm

Circuit A

Circuit B

RA

+ -v tm( )

i tA( )

Source of the changing current

Lowimpedance

Coupled noisevoltage fromcircuit A appearshere

Figure 2.11: Example of mutual inductance in a digital system.

Remark 2.8 Mutual inductance coupling differs from its capacitive counterpartin that voltages of differing polarities can be induced depending on the relativedirection of the current in the primary circuit. The relative direction can bedifferent depending on the physical layout of the circuit. The magnitude of thevoltage is also very susceptible to the orientation of the primary and secondarycircuits.

From Faraday’s Law we know that the voltage induced in a loop of wire dueFaraday’s Lawto a uniform magnetic flux density of B tesla is:

v =d(BA)

dt=

dφ

dt(2.34)

where A the area of the loop through which the magnetic flux density passes.6

Equation (2.34) clearly indicates that for a given flux density that the voltageinduced in a coil is proportional to the area of the coil. Therefore, in order tokeep the mutual inductance low the loop area of the secondary circuit shouldbe kept as small as possible. The sensitivity of the induced voltage to theorientation of the sending a receiving circuits can also be seen. The flux densityin (2.34), as mentioned previous is the component of the flux density that isorthogonal to the surface of the coil area. Therefore, if the flux density has azero orthogonal component then the induced voltage would be zero.

Practical Issue 2.4 An approximate expression for the mutual inductance be-tween two loops can be obtained under the condition that the separation of loopsis far enough to satisfy the following condition:

6Note that we are assuming that the flux density is orthogonal to the surface of the loopin this expression.


d >√

A1 (2.35)

d >√

A2 (2.36)

where A1 the area of loop 1 in cm2, and A2 the area of loop 2 in cm2 andd the distance between the loops in cm. It is assumed that the loops are parallelto each other (i.e. the mutual inductance is maximised).

The expression for the mutual inductance is therefore:

Lm ≈ 2A1A2

d3(2.37)

where Lm the mutual inductance in nano-Henry.The mutual inductance between two parallel wires suspended above a ground

plane is given by:

Lm = L

[1

1 +(

sh

)2]

(2.38)

where:

s separation of the two conductors

h height of wires above the ground plane

L self inductance of one of the wires (2.39)

2.5.4.1 Relationship Between Mutual Inductance and Crosstalk

Given a known mutual inductance, a waveform rise time Tr, and a sourceimpedance in the driving circuit A equal to RA we may estimate the crosstalkrelative to the driving voltage vA.

Following a procedure similar to that in Section 2.5.3.1 we can derive thefollowing expressions for the mutual induced voltage and crosstalk.

We shall assume that circuit A is resistively damped by RA, so the currentin this circuit is essentially given by Ohms Law. This is the normal situation ifthe drive is into a transmission line that is terminated. Therefore using (2.24)and Ohms Law we can write:

diA(t)dt

=∆V

RATr(2.40)

We can now calculate the mutually induced voltage appearing in circuit B:

vm = Lm∆V

RATr(2.41)

The final part of the derivation is the divide by ∆V to get the inductivecrosstalk : inductive crosstalk

Crosstalk =Lm

RATr(2.42)


Practical Issue 2.5 Similarly to the capacitive coupling case there are usuallymultiple sources of coupling in practical situations. To calculate the inductivecoupling in these cases estimate the mutual coupling from each of the individualsources and then add together the individual cross couplings to give the total.

Example 2.3 This is a similar example to Example 2.2 for the capacitive crosscoupling. The approach will be similar, in that we shall consider the couplingbetween two resistors. Figure 2.12 schematically shows the test circuit. Thephysical configuration of the resistors is shown in Figure 2.13. Notice that somelines of flux density emanating from the circuit A resistor link the circuit loopcontaining resistor B, and if these flux density lines change with respect to timethen a voltage will be induced in circuit B (as shown in Figure 2.12).

In this example we assume that the self inductance of the resistors is 10nH,and the mutual inductance between them is 1nH.

The scope connection is assumed to have an impedance of RT , and con-sequently the induced voltage is divided between the RB resistor and the RT

resistor. Usually the scope termination is 50Ω so the voltage across the scopeinput will be halved.

In a manner similar to the estimation of the capacitance in the capacitivecoupling situation we can estimate the inductance using (2.18). We shall setupa simulation of this example in the Saber simulator. The equivalent circuit isshown in Figure 2.14.7

A plot of the important variables in the simulation appear in Figure 2.15.Notice that the area of the voltage appearing across the load is 26.908pV-sec.Therefore substituting this into the area section of (2.18) with the value of theresistor R = 2RB = 100Ω and ∆V = 2.7V then we get Lm = 0.996nH ≈ 1nH.8

The inductive crosstalk can be calculated using (2.42) (remembering to useRB + RT for the resistance):

Crosstalk =1.0 × 10−9

100 × 800 × 10−12= 0.0125 (2.43)

The crosstalk due to the capacitance in this situation is from (2.30) 0.025/8= 0.003 (remember the grounded resistors result in an 8 fold reduction in thecrosstalk). Hence the inductive crosstalk in this situation is four times the ca-pacitive crosstalk.

Note 2.6 If we were physically carrying out this experiment we would not onlyhave the inductive coupling present, but we would also have capacitive coupling.Due to the way the capacitive coupling test was carried out in (2.2) we havevery little inductive coupling (there is no through current in the components).Therefore, the capacitive coupling can effectively be separated from the inductivecoupling.

For this particular situation we could therefore subtract the capacitive area/8(remember the resistors are grounded – see Example 2.2) from the area measuredand then do the inductive calculation.

7Note that one could easily solve this circuit analytically, but the simulation approachallows one to play with the values and ready obtain plots. Furthermore it is analogous todoing an experiment.

8Note that we are using 2RB in the expression since the voltage in the coil is being halveddue to the voltage division effect caused by the presence of the scope impedance.


RA

RB

+ -vm

Lm

Input

Output

To scope

From pulsegenerator

50

50

Figure 2.12: Measurement setup for mutual inductance experiment.

RA

RB0.063in

0.1in

Solid ground planeFlux density lineslinking resistor B.Flux density

field lines

Figure 2.13: Physical configuration of resistors in inductive coupling experiment.


Lm 1nH

50 50

5050RB

RA

RT

(Scope)

Tr 800ps

L 10nH

L 10nH

Figure 2.14: Equivalent circuit for simulation of inductive mutual coupling.

Remark 2.9 We have included the derivative of the current in Figure 2.15.This is shown in order to allow comparison of this simulation with a later onewhere load capacitance has been included in the modelling.

Practical Issue 2.6 In most high speed digital systems the inductive couplingis more significant than the capacitive coupling. The reason for this has not beenanswered in this section, but will be given in Section 2.6.2.

2.6 Speed of Digital Systems

In many discussions of digital systems there is a concentration on the propa-gation delay of the particular logic gates being used. However, many practicalproblems in digital systems are related to the minimum output switching timeminimum output

switching time (i.e. the minimum time to switch from high to low or vice versa). As we haveseen in previous sections of this chapter the problems crosstalk increases con-siderably with increased rate of change of switching edges.

Generally speaking, logic families that have switching times much faster thantheir propagation delay are suffering problems related to fast switching edgeswithout any advantage from a logic design viewpoint – the speed and timing ofthe system is governed by the propagation delay .propagation delay

Practical Issue 2.7 Given two logic families with identical propagation delays,the logic family with the slowest output switching times will be easier and cheaperto use.

In recognition of these facts some more recent logic families now incorpo-

2.6 Speed of Digital Systems 41

Inductive coupling

0.0

2.0

4.0

t(s)

0.0 500p 1n 1.5n 2n 2.5n

-0.04

-0.02

0.0

0.02

-40p

-20p

0.0(2.0486n, -26.908p)

0.0

0.02

0.04

0.06

-20meg0.0

20meg40meg60meg80meg

(880.7p, 65.891meg)

(V) : t(s)

input

(V) : t(s)

output

(V*sec) : t(s)

integ(output)

(A) : t(s)

i(l.l1)

(A/s) : t(s)

deriv(i(l.l1))

Figure 2.15: Results of the inductive cross coupling simulation.


rate circuitry to slow down the switching edges to acceptable levels.9 Prior tothis the switching edges were largely uncontrolled. For example, a technologyin the early 1980s for output drivers on high speed logic circuits was VMOS.These output devices had very fast switching times, but they made it extremelydifficult to build a printed circuit board that would work.10

2.6.1 dv/dt Effects

It was mentioned in (2.1), repeated here for convenience, the spectral contentof a digital signal is directly related to the rise time of the signals in the circuit:

Fknee =0.5Tr

(2.44)

Therefore as the rise time becomes smaller, then the frequencies which thecircuit has to cope with increase. Therefore, all data paths, integrated circuitpackages and physically layout has to be able to function with frequencies upto this value. As noted in (2.26) and (2.42) both the capacitive and inductivecrosstalk are inversely proportional to the rise time of the voltage (Tr). Sincecrosstalk is a relative measure then it is independent of ∆V . Therefore theT10−90 edge time is the really important value and not ∆V .

2.6.2 di/dt Effects

In Sections 2.5.3 and 2.5.4 we were able to relate the dv/dt of the output wave-forms to the di/dt of the currents using the simple approximation that thecircuit was predominantly resistive. However, in practical digital systems theload on a logic element is not only resistive but also it also has a capacitiveloading component.11capacitive loading

component The capacitance present in digital systems has two components – the capac-itive of the printed circuit board tracks themselves, and the capacitance of theinput to the logic gates. Usually the latter of these two will be the dominantone.12 The presence of the load capacitance has an effect on the rate of changeof current. To examine this effect consider a typical circuit shown in Figure 2.16.This shows a gate driving a combination resistor/capacitor load (i.e. a typicalmodel for the input of a gate).

The current i(t) flowing in the output line of the gate can be calculated asfollows:

i(t) =v(t)R︸︷︷︸

Resistive current

+ Cdv(t)dt︸︷︷︸

Capacitive current

(2.45)

In order to calculate the effect that this current has on the inductances inthe circuit we have to differentiate (2.45) with respect to time:

9In fact circuitry of this nature was introduced in the MECL 10K family in 1971, but iswasn’t until 1990 that it was introduced into the more common FCT CMOS family.

10This was especially true in the early 1980s as there were no such things as 4 layer printedcircuit boards that included power supply planes.

11It even has an inductive component if one considers the lead wiring.12This capacitance is due to the input transistor plus the input lead and package capacitance.


CRv t( )

i t( )

Figure 2.16: Logic gate with a capacitive load.

di(t)dt

=1R

dv(t)dt

+ Cd2v(t)dt2

(2.46)

Remark 2.10 Equation (2.46) shows that the rate of change of current whencapacitance is present is a function not only of dv(t)/dt, but also of d2v(t)/dt2.Therefore if dv(t)/dt is increasing by a factor of two the rate of change of current(due to the capacitive component) will increase by a factor of four. Note thata constant ramp (i.e. dv(t)/dt =constant) has d2v(t)/dt2 = 0, and therefore inthis case there is no effect.

Note 2.7 The squared dependence of di(t)/dt on the rate of rise of voltage whenthere is a capacitive load is one of the main reasons that inductive coupling isusually worse than capacitive coupling in digital circuits.

We shall investigate the effect that the presence of capacitance has on theinductive cross coupling in circuit of Figure 2.14. The input waveform still hasa rise time TR of 800p-sec. We shall add a 10pf capacitor to the RA resistorin this figure. For comparison Figure 2.15 shows the results when there is nocapacitive loading in the circuit. The results of simulating the capacitive circuitappear in Figure 2.17.

We can make several observations from Figure 2.17:

• The fact that we have an LC circuit means that the circuit will ring. Thiscan be seen in the oscillatory behaviour in the output voltage and theprimary side inductor current.

• The maximum rate of change of current in the circuit is of the order of1.2 × 108 Amp/sec. Compare this to that in Figure 2.15, where we havea maximum di(t)/dt of 6.5 × 107 Amp/sec.

• Because the di(t)/dt for Figure 2.17 is twice that of Figure 2.15 then themutually coupled voltage into circuit B is approximately twice (as can beseen by comparing the two figures).

These observations therefore confirm the assertions made in Practical Issue 2.6and Note 2.7 that the presence of load capacitance significantly enhances thecross coupling due to mutual inductance.


(V)

0.0

1.0

2.0

3.0

t(s)

0.0 500p 1n 1.5n 2n 2.5n

(V)

-0.08-0.06-0.04-0.02

0.00.020.04

(A)

0.0

0.02

0.04

0.06

0.08

0.1

(A/s

)

-100meg

0.0

100meg

200meg

(V) : t(s)

input

(V) : t(s)

output

(A) : t(s)

i(l.l1)

(A/s) : t(s)

deriv(i(l.l1))

Figure 2.17: Inductive coupling waveforms with a 10pf load capacitance.


2.6.3 Ground Bounce

Ground bounce is an inductive effect caused by the inductance of the leads inthe packages used for integrated circuits. This phenomena causes glitches in the glitcheslogic inputs whenever the device outputs switch from one logic state to another.

2.6.3.1 Why Does Ground Bounce Occur?

The following discussion is with reference to Figure 2.18 which is a schematicof a four pin integrated circuit with bonded wires. One transmit and receivecircuit are shown. Suppose switch B is closed discharging the load capacitor C toground. This results in a load current flowing around this loop. As this currentincreases and decreases there is a voltage induced across the lead inductancecausing a voltage to be induced:

vGND = LGNDdidischarge

dt(2.47)

+-

VCC

Output circuit

Totem pole outputdrivers

Ground pininductance

SW A

SW B

LGND Ci

discharge

vGND

+

-

vin

Ground Plane

Figure 2.18: Schematic of an integrated circuit showing the lead inductance.

This induced voltage shifts the internal ground reference from the boardground plane. It is this phenomena that is called ground bounce. The voltagevGND is usually small compared with the output voltage swing and does notsignificantly impair the transmitted signal. However, it can have dramatic effectson the reception of signals.

Note 2.8 In Figure 2.18 we can see that the input circuit is sensing the inputvoltage relative to its own local ground rail (as emphasised by the differentialamplifier representation of the input circuit). This situation is representative ofthe TTL logic family. Other logic families (e.g. ECL and GaAs) compare the


input to VCC . CMOS circuits tend to compare inputs against a weighted averageof VCC and ground.

The other important issue in relation to the references is the reference forthe outputs. In the case of TTL if the output is high then the output referenceis VCC (since the bottom output transistor is open circuit), and when the outputis low then the reference is the 0V rail. Note that the output reference does notnecessary match the input reference, and this must be carefully considered whenlooking at the effects of noise on the ground and VCC rails.

Consider the situation depicted in Figure 2.18. The input voltage seen onacross the differential input amplifier is:

v′in = vin − vGND (2.48)

In this equation vGND can be either positive or negative depending on thedirection of the current through the ground lead inductance. From the pointof view of the input the noise voltage across the lead inductance is effectivelysuperimposed on the input voltage.

If there is only one output switching then ground bounce should not causea problem. However, in an IC with N outputs switching at the same timethen the problem will get N times worse. Further exacerbation can occur ifthe N outputs are driving capacitive loads, since as noted in Note 2.7 the rateof change of current increases under these conditions. This leads to a doublehumped waveform in the ground bounce voltage, as can be deduced from thecurrent derivative waveform in Figure 2.17 (since v = Ldi/dt).

2.6.3.2 How Does Ground Bounce Affect Circuits?

Consider the situation of a set of octal D flip flops with an edge triggered clockinput. The circuit has a setup time for data of 3nsec and a hold time of 1nsec.The propagation delay is 3nsec. The flip flops are driving a bank of 32 memorychips, each chip with an input capacitance of 5pf. Therefore the total capacitiveloading on each of the flip flop outputs is 160pf.

The following discussion is with respect to Figure 2.19. At time A the inputsto the flip flops are FF Hex. These inputs are clocked into the latches, and afterthe propagation delay they appear at the outputs. At time B the outputshave been changed to 00 hex and the clock then clocks this into the latches.However, due to the simultaneous switching of the outputs coupled with thelarge capacitance of the load there is a significant voltage induced across theground lead inductance. This voltage is delayed by the 3nsec propagation timeof the flip flop. However, if after the 1nsec hold time the inputs to the flip flopshave changed to an arbitrary XX hex value then one could have a problem dueto the glitch that the ground bounce places on the clock line into the flip flops.This glitch will latch the new value on the data lines into the flip flops, andhence an erroneous value is now stored. One would observe the correct valuemomentarily appearing on the outputs, followed by the incorrect value.

Self clocking problems such as this can occur in DIP (dual inline packages)self clockingwhich has very fast output drivers connected to capacitive loads – for examplelarge FCT latches. If these circuits are in surface mount packages then theproblems are significantly reduced due to the lower lead inductance in thesepackages.


FF

FF

00

00

XX

XX

Clock

Q outputs

Data bus

Clock - VGND

VGND

Propagationdelay3nsec

3nsec setup

Time A

1nsec hold

Time B Time CTime D

Glitch at Time Dclocks XX intothe latches

After clock glitchoutputs may switchto another state

Ground bounce noise

Figure 2.19: Example waveforms for an octal latch driving a capacitive load.


74HCT 74AS 10KH 10G NELCMOS TTL ECL GaAs GaAs

∆Vmax(V) 5 3.7 1.1 1.5 1.0T10−90(ns) 4.7 1.7 0.7 0.15 0.05

Table 2.2: Typical switching characteristics of common logic families.

2.6.3.3 Estimating Ground Bounce Magnitude

One needs to know four things to estimate the ground bounce in a circuit:

1. The 10% to 90% switching time of the outputs.

2. The load capacitance or resistance.

3. The lead inductance to ground.

4. The output voltage swing.

For a resistive load the voltage induced in the lead inductance is obviously:

|vGND| =LGND

R

∆V

T10−90(2.49)

If we have a capacitive load, and assuming a gaussian shape for the derivativeof the input step, then it is possible to show that the rate of change of currentis [1]:

dicdt

= Cd2v

dt2= 1.52C

∆V

T 210−90

(2.50)

and hence the voltage induced is:

|vGND| = 1.52LGNDC∆V

T 210−90

(2.51)

Typical values for switching times and voltage swings for common logic fam-ilies appear in Table 2.2.

2.6.3.4 Reducing Ground Bounce

One can deduce from the previous discussion that ground bounce is primarilya function of the switching characteristics and the package which the IC ispackagemounted in. For a given package one way to alleviate ground bounce is to slowdown the output switching speeds. The FCT CMOS and 10K ECL families andnewer bus drivers incorporate circuitry to slow down switching edges.

Another strategy for reducing ground bounce is to lower the lead inductance.This can be achieved by using different package designs. If we consider the moreconventional packaging technology one technique is to put multiple ground wiresmultiple ground

wires on the package. It is best to evenly space these around the package. If thegrounds are all near each other, then going from one to two grounds halves theinductance. However, there is a diminishing return by increasing the number ofgrounds above this.


Some other components attack the problem by bringing out a separate wirefor the internal reference. An example of a family that does this is the 10Kinternal referenceECL family. This separate pin does not carry the large ground currents andtherefore does not suffer ground bounce. Differential inputs are an even moreeffective technique to achieve the same end.

If one is prepared to embrace more radical packaging technologies then thelead inductance can be decreased considerably. The most promising techniquesare wire bond, tape automated wire bond (TAB) and flip-chip. All of thesetechniques involve mounting the chip directly on the printed circuit board – i.e.the lead inductance has been eliminated by eliminating the package.

Wire bonding is a technique akin to the bonding technique used in the current wire bondingintegrated circuit packages. The IC is placed back side down on the printedcircuit board, and one the top side there are a number of small pads on thechip. Very fine wires are then bonded to these pads and then bonded to acorresponding connection on the printed circuit board. The IC and the wiresare covered with a covering material and then the whole lot is hermeticallysealed with a lid. This technique has the capability of hand production forsmall volumes.

Tape bonding is an enhancement of the wire bonding technique. It uses a tape bondingflexible circuit with wire tapes on it. This flexible circuit may have multiplelayers, including a ground to control impedances. This is overlaid on the IC sothat the wire tapes align with the IC pads (which have solder balls on them) andthe printed circuit board connections. The tape wires are then reflow solderedto the IC and the printed circuit board and the whole lot sealed as in thewire bonded case. Therefore this technique improves on the wire bonding byproviding a much faster technique of connecting the wires all at once. The multi-layer capability also improves the signal transmission. The disadvantage of thetechnique is that the flexible circuit must be changed if there is any change toeither the IC or the printed circuit board connection points.

The flip-chip technique places solder balls on each chip attachment pad. The flip-chipchip is then placed face down on the printed circuit board and directly reflowsoldered in place. This technique is often using in ceramic multi-chip structuresthat incorporate advanced cooling techniques. The whole device is hermeticallysealed. From the inductance viewpoint this technique is excellent, as the leadinductances are almost totally eliminated. However, from a mechanical andthermal viewpoint it has some deficiencies. The differing thermal expansionof the IC and the printed circuit board can cause undue stresses on the IC.The only compliance in the set up is the solder balls. Furthermore the IC canbecome hotter because it is held off the printed circuit board by the solder balls.The wire bond and tape bond techniques had the back of the IC contacting theprinted circuit board (usually glued to it), this offering a heat sink.

Table 2.3 shows typical values of the lead inductance for a variety of packagetypes.13

2.6.4 Lead Capacitance

Stray capacitance between adjacent pins of logic packages can couple noise volt-ages into sensitive inputs. Consider the situation shown in Figure 2.20, where

13Data from [8].


14-pin plastic dual-in-line package (DIP) 8nH68-pin plastic DIP 35nH68-pin surface mount plastic leaded chip carrier (PLCC) 7nHWire bonded to hybrid substrate 1nHSolder bump to hybrid substrate 0.1nH

Table 2.3: Lead inductances of various logic packages.

14-pin plastic dual-in-line package (DIP) 4pF68-pin surface mount plastic leaded chip carrier (PLCC) 7pFWire bonded to hybrid substrate 1pFSolder bump to hybrid substrate 0.5pF

Table 2.4: Inter-pin capacitance of common logic packages.

CM is the mutual capacitance between the pins. One may compute the crosstalkmutual capacitancein circuit 2 from the rising edge in circuit 1 by using the expression (2.26) andrealising the RB value is 75/2Ω, since the transmission line and terminationresistances are in parallel. Therefore we have:

Crosstalk =RCM

Tr=

(37.5Ω)(4pF)5nsec

= 0.03 (2.52)

which is 3% cross coupling. This situation becomes significantly worse if the risetime decreases, or if the impedance of the circuit coupled to increases. One wayof alleviating the problem with higher impedances is to add capacitance to thelines with the high impedance so that the impedance is lowered at high frequen-cies. However, whilst this may solve the capacitance cross coupling problem, itmay exacerbate ground bounce problems in some circumstances.

Table 2.4 shows the typical values for the inter-pin capacitances for commonlogic packages.14

2.6.5 Measurement Issues

This section will consider a few relevant issues related to the measurement ofhigh speed digital signals. Most of these issues will be related to limitations andcaveats associated with the use of cathode ray oscilloscopes (CROs) to observesignals in digital systems.

2.6.5.1 Rise Time and Bandwidth of CROs

The main limitations associated for CROs when used in digital systems arerelated to bandwidth issues. We have seen in previous discussion that bandwidthand rise time are intimately related (see (2.2 and (2.3)). In the case of anoscilloscope we have a cascade of different components – the probe (which has afrequency response), and perhaps several input amplifiers and finally the displaysystem, all of which have a frequency response. As we just noted this also meansthat they have a corresponding rise time. It can be shown [1] that the compositerise time of a system composed of a number of components is (assuming gaussiancomposite rise time

14Data from [8].


CM

4pF

Logic package

VCC

75 termination

Z0

75

Tr 5nsec

1

2 Transmission line

Figure 2.20: Logic package showing the capacitance between pins.

t1

Input

t t1

2

2

2

Response of theprobe to input

CRO Probe

G

t t t1

2

2

2

3

2

Vertical amplifier

Composite responseof probe and verticalamplifier

Figure 2.21: Composite rise time of an oscilloscope.

pulses)15:

Trcomposite = (T 21 + T 2

2 + · · · + T 2N )

12 (2.53)

The concept behind this equation is shown in Figure 2.21.Consider the case of an RC low pass filter. The bandwidth of this circuit is:

F-3dB =1

2πRC(2.54)

Substituting this expression into (2.2) we can write:

15Although this is only exact with gaussian pulses, other pulse shapes give almost the sameresult.


T10−90 =0.35F-3dB

= (0.35)(2πRC)= 2.2RC (2.55)

Similarly we can write the following for the LR filter:

T10−90 = 2.2L

R(2.56)

and for the RLC filter (near critically damped):

T10−90 = 3.4√

LC (2.57)

Example 2.4 This example is taken from [1]. A person buys an oscilloscoperated at 300MHz bandwidth with a probe at 300MHz bandwidth (both are −3dBbandwidths). How does this combination affect signals having a rise time of2nsec?

Assuming the pulses are gaussian in nature then we can compute the risetime of each of the components as:

Trprobe/scope=

0.338300MHz

= 1.1nsec (2.58)

Trsignal= 2nsec (2.59)

therefore the displayed rise time is:

Trdisplayed= (1.12 + 1.12 + 2.02)1/2 = 2.5nsec (2.60)

Therefore this oscilloscope will display the 2nsec input signal as a signal witha rise time of 2.5nsec.

2.6.5.2 Self-inductance of CRO Probe Ground Clips

Once again we have inductance arising in the context of high speed operationof digital systems. However, in this case we are considering the measurement ofthe signals.

One point to note at the outset is that the bandwidth of a CRO probe isbandwidth of aCRO probe defined when the probe is in a test jig with the probe grounded directly on

its case. There is no ground wire employed when probe frequency response ismeasured. However, in practice digital designers usually use a plastic lead withan alligator clip on it to secure the CRO ground to the circuit ground undertest. This ground lead has inductance associated with it, the specific valuedependent on the length and configuration of this lead. Clearly the presenceof this inductance will affect the frequency response of the probe, and we shallinvestigate this effect by considering the equivalent circuit shown in Figure 2.22.For a typical CRO probe the input capacitance Cin = 10pF and the inputresistance is Rin = 10MΩ. The value of the source resistance of course dependson the source – for a TTL and CMOS the source impedance is approximately30Ω and for ECL about 10Ω.


RS

L

Cin

Rin

vS

+

-

Toscope

Sourceresistance Probe input

capacitance andresistance

Figure 2.22: Equivalent circuit of CRO input probe.

The presence of the inductance in the probe lead has several significantaffects on the performance of the CRO. Firstly, the input circuit has a rise timeassociated with it. Recall (2.57) for the RLC rise time. In order to use thisexpression we need a representative value for the probe inductance. In orderto obtain this assume that we have a earth clip loop of width 2.54cm (1in) andlength 7.62cm (3in) with American Wire Gauge (AWG) 24 wire which has adiameter of 0.0508cm. Substituting these values into (2.21) we have:

L ≈ 4

2.54 ln[2 × 7.620.0508

]+ 7.62 ln

[2 × 2.540.0508

]= 198nH ≈ 200nH (2.61)

Therefore the intrinsic rise time of the probe is (assuming critical damp-ing)16, using (2.57):

T10−90 = 3.4√

LC = 3.4√

(200nH)(10pF) = 4.8nsec (2.62)

This rise time spells trouble. We calculated in (2.58) that the rise time of theCRO itself was 1.1nsec. Therefore the presence of the probe inductance hasseverely degraded the rise time (and hence bandwidth) of the measurementsystem.

The other interesting aspect of the circuit shown in Figure 2.22 is that it isa resonant circuit . Therefore it will have a quality factor (given the symbol Q). resonant circuit

16An overdamped circuit rise time is even slower than the critical damped rise time, but anunderdamped rise time is faster at the expense of overshoot.


For a series circuit the expression for Q is (see Appendix G for a summary ofsecond order series and parallel RLC circuits):

Q =1

RS

√L

C(2.63)

It should be noted that Q is the ratio of the total stored energy in the systemto the energy lost per radian. A very high Q circuit for example would havea very low value of resistance, meaning that the losses are very low. Such acircuit would tend to resonant for long periods of time. In the particular caseof the CRO probe it is clear that the Q will be very dependent on the sourceimpedance of the particular logic gate driving the probe.

Let us consider the frequency response of the probe circuit. Using simplecircuit analysis one can deduce that the transfer function is:transfer function

vin

vs=[

Rin

Rs + Rin

] [1

1 + CinRinRs+LRs+Rin

s + CinLRin

Rs+Rins2

](2.64)

If we plot this transfer function over the area of the frequency response of interestwe get Figure 2.23. As one can see the peak of the resonance is very dependenton the value of the source resistance. Clearly if the input signal has energy ata frequency of approximately 700Mrad/sec (or 110MHz) then there is going tobe some oscillations in the output. Therefore this limits the rise time to avoidoscillations to:

Tr >0.5

110MHz= 4.54nsec (2.65)

Note 2.9 This particular rise time limitation is purely a product of the partic-ular lead inductance-input capacitance combination.

Let us consider the time domain response of the CRO probe equivalent cir-time domain re-sponse of the CROprobe

cuit. Whilst one can analytically evaluate the response from the transfer func-tion, a experimental/simulation approach has been opted for.17 A Saber sim-ulation has been set up of the circuit, with the previously mentioned input pa-rameters for the probe (Cin = 10pF, L = 200nH, Rin = 10MΩ) and the sourceresistance of 30Ω (which is equivalent to a TTL output source resistance). Theplot of the input voltage to the CRO appears in Figure 2.24.

As can be seen from Figure 2.24 the response seen by the CRO input isvery oscillatory due to the presence of the LC circuit. Also note that with theresistance of the TTL source the Q in the circuit is quite high. In fact to get toa critically damped circuit the value of the source resistance has to be closer to282Ω. With this value of resistance the rise time of the circuit is very near thatcalculated in (2.62).

Practical Issue 2.8 The response of a CRO probe can have a very importanteffect on the observed waveforms.

Remark 2.11 The scope ground undergo very large voltage excursions in Fig-ure 2.24. It is this “ground bounce” that is the source of the scope displayproblems.

17The simulation approach will be used repeatedly throughout these notes as it simulatescarrying out a real practical experiment.


Frequency (rad/sec)

-40

-30

-20

-10

0

10

20

30

108

109

1010

-150

-100

-50

0

Phas

e:deg

Mag

nit

ude:

dB

5

30

100

Figure 2.23: Bode plot of the transfer function of a CRO probe.


Ground bounce

(V)

0.0

2.0

4.0

6.0

t(s)

0.0 20n 40n

rise: 1.8377n

(V)

-4.0

-2.0

0.0

2.0

4.0

(V)

0.0

2.0

4.0

6.0

8.0

10.0

(V) : t(s)

input

(V) : t(s)

scope_gnd

(V) : t(s)

(output-scope_gnd)

Figure 2.24: Response of the CRO probe equivalent circuit with the input risetime of 1.8nsec.


The other interesting thing to look at with this circuit is what happens whenwe slow down the input edge. We calculated in (2.65) that if the rise time wasgreater than 4.5nsec that the circuit oscillations would become substantiallysmaller. If we redo the same simulation as shown in Figure 2.24 but with therise time of the input equal to a 5.5nsec T10−90 rise time we get the plot ofFigure 2.25. Notice that the oscillations are substantially less in this figure,and one could say that the scope is now producing a much more acceptablewaveform.

Ground bounce

(V)

0.0

2.0

4.0

6.0

t(s)

0.0 20n 40n

rise: 5.5469n

(V)

-2.0

-1.0

0.0

1.0

(V)

0.0

2.0

4.0

6.0

8.0

(V) : t(s)

input

(V) : t(s)

scope_gnd

(V) : t(s)

(output-scope_gnd)

Figure 2.25: Response of the CRO probe equivalent circuit with the input risetime of 5.5nsec.

If we slow the edge even more then the overshoot continues to decrease. Ifthe rise time is about 10nsec then the scope input waveform has virtually noovershoot.

Remark 2.12 In summary, we can see from this section that the presence ofthe CRO probe ground lead and clip has dramatic effects on the effective risetime of the probe, and dramatically effects the observed waveforms – particularlyin relation to the overshoot observed on the edges.

Table 2.5 lists the Q and rise times for TTL logic and ECL logic. It isassumed that the source resistance for these logics are 30Ω and 10Ω respectively.


10pF probe 2pF probe

Ground loopinductance

(nH) T10−90 QTTL QECL T10−90 QTTL QECL

200 2.8 4.7 14.1 1.3 10.5 32.0100 2.0 3.3 9.9 0.89 7.4 22.030 1.1 1.8 5.4 0.49 4.1 12.010 0.6 1.1 3.2 0.28 2.4 7.13 0.3 0.6 1.7 0.15 1.3 3.91 0.2 0.3 1.0 0.09 0.7 2.2

Table 2.5: Rise time and Q for 10pF and 2pF capacitance probes for variousinductances.

2.6.5.3 Mutual-inductance of CRO Probe Ground Clips

Another effect from having a probe lead connected is that it acts as a pick upfor electrical noise . This noise cannot be distinguished from noise on the signalelectrical noisebeing observed. The main mechanism for this noise pick up is magnetic mutualcoupling between the loop of the probe lead and another loop in the circuitmagnetic mutual

coupling being probed. The orientation of the two loops is important in determiningthe magnitude of the observed noise voltage – as noted in Section 2.5.4 if theareas of the loops are such that there is no component of the flux from one looporthogonal to the area of the other loop then the mutually induced voltage iszero.

In a practical situation the loop generating the interfering magnetic field isgenerally a loop consisting of printed circuit board tracks running to and froman integrated circuit that is driving some load (usually with some capacitance).Figure 2.26 illustrates this particular situation. As can be seen from the diagramsome of the magnetic field produced by the signal and ground return current ina nearby integrated circuit is coupled to the loop represented by Loop B. If theorientation of the loops is such that this field is orthogonal to the area of LoopB then there will be a mutual inductance between the two loops and hence,depending on the rate of change of the magnetic flux density, a voltage will beinduced in the CRO lead.

One can get a rough estimate of the magnitude of the induced voltages inthis situation by using (2.37) together with the rate of change of current and(2.11).

Example 2.5 Consider the situation where Loop A in Figure 2.26 is 0.7cm ×0.7cm and Loop B is 2.5cm × 7.5cm. The loops are separated by 5cm. If we


Loop A

Loop B

Magnetic fieldlines from Loop Ato Loop B

Return groundcurrent

Signalcurrent

Figure 2.26: General configuration for probe lead pick up.


apply (2.37) then we can calculate:

LM = 2A1A2

D3

= 20.49 × 18.75

53

= 0.147nH (2.66)

We shall assume that the circuit is feeding a capacitive load of 50pF, and the∆V = 3.7V and the rise time Tr − 2nsec. Substituting this into the expressionfor the rate of rise of current with a capacitive load (2.50) we get di/dt =1.52C ∆V

T 2r

= 7 × 107A/sec. We now all the components to calculate the couplednoise. Using (2.11) we can write:

vnoise = LMdi

dt= 0.147nH × 7 × 107A/s = 12mV (2.67)

The 12mV noise is fairly low. However, if we have a bus with a large numberof lines conducting a similar amount of the current then the coupled noise couldpotentially be the (number of lines) × 12mV. Therefore, if one has a 32 linebus then the figure could be 0.384V, which is starting to become a problem whenmeasuring voltages on TTL systems.

Practical Issue 2.9 If one wishes to get some idea of the degree of magneticpickup on a CRO lead then one can connect the alligator clip to the probe tip.Ideally one should see nothing on the CRO screen since the voltage being mea-sured should ideally be zero. However, if the loop formed by the probe lead isorientated in various directions to a potential interference generating circuit thenone would see voltages which are a consequence of magnetic coupling pick up.This can give one a subjective feel for the potential mutual coupling interferencethat would be present in measurements made on the system.

Summary 2.1 In order to minimise the effects of the probe lead one shouldkeep it as small as possible. If possible the earth shield on the probe should beshorted to the nearest ground point to the signal being measured using somethinglike a knife blade.

2.6.5.4 Loading Effect of CRO Probes

Probing a circuit, like many other measurement techniques, can actually changethe circuit parameter being measured. In fact, sometimes in a circuit that ismisbehaving, probing the circuit can load the circuit so that it will work correctlywhen the probe is there.

The important parameters in determining the effect of probe loading are:important parame-ters

• The knee frequency of the digital signal under test (equation (2.1))

• The source impedance of the circuit under test at the knee frequency

• The input impedance of the scope probe at the knee frequency.

To get some sort of a feel for the effects of various probes we shall considerthe source to input transfer function and the CRO input impedance for thefollowing probe parameters:


1. Standard 10× probe with 10pF and 10MΩ input capacitance and resis-tance respectively.

2. A 10× FET active input probe with 1.7pF and 10MΩ input capacitanceand resistance respectively.

3. A passive probe with 0.5pF and 1000Ω input capacitance and input impedancerespectively.

The equivalent circuit we are using is shown in Figure 2.27. Notice that thereis no inductance in the ground of the circuit. This means that we are assumingthe the ground shield of the probe is connected directly to the ground plane ofthe circuit under test (and the ground inductance is therefore negligible).

RS

Cin

Rin

vS

+

-

Toscope

Sourceresistance Probe input

capacitance andresistance

vin

Figure 2.27: CRO probe equivalent circuit with no lead inductance.

The transfer function for Figure 2.27 can be written as:

vin

vs=(

Rin

Rin + Rs

)(1

1 + sCinRinRs

Rin+Rs

)(2.68)

and similarly the input impedance transfer function can be written as:

Zin(s) =Rin

1 + sCinRin(2.69)

Plotting these transfer functions for the above mentioned probe parametersand Rs = 50Ω we get Figures 2.28 and 2.29.

Remark 2.13 It can be seen from Figure 2.28 that the standard 10MΩ, 10pFprobe causes a substantial roll-off in the source to probe input transfer functionfor rise times smaller then 3nsec.


Frequency (rad/sec)

-10

-8

-6

-4

-2

0

107

108

109

1010

-60

-40

-20

0

Phas

e:deg

sv i

ndB

314ns 31.4ns 3.14ns 0.314ns

10 10M pF,10 17M pF, .1000 0 5, . pF

Rise Time

Figure 2.28: Source to probe input transfer function for a CRO probe.

Frequency (rad/sec)

100,000

107

108

109

1010

1000 0 5, . pF10 17M pF, .10 10M pF,

10,000

1000

100

314ns 31.4ns 3.14ns 0.314ns

Rise time

Imped

ance

Mag

nit

ude

(Ohm

s)

Figure 2.29: CRO probe input impedance.


Remark 2.14 The active FET probe and the very low capacitance passive probehave good frequency response characteristics, and will handle frequencies intothe 500MHz plus range of operation (which corresponds to rise times of approx-imately 1nsec or less).

Remark 2.15 The reason for the poor performance of the standard 10MΩ,10pFf probe can be seen from Figure 2.29. The input impedance of the probefalls to levels of approximately 100Ω when the input signals have a rise timeof approximately 3nsec. Therefore the input impedance is placing a substantialload on the circuit when there is a 50Ω source resistance (which is typical for adigital circuit).

Practical Issue 2.10 For the loading to be small the input impedance magni-tude needs to be approximately 10 times the source impedance.

The most important component of a probes input when it comes to its loadingeffects at high frequencies is its capacitance.

2.6.6 Better Probing Techniques

We have seen in the previous subsections that the presence of lead inductanceand input capacitance has significant effects on the measurement performanceof CROs. The logical question to ask is “What can we do to get more accuratemeasurements in high speed digital systems?” The subsection will attempt tooffer several answers to this question.

2.6.6.1 Home Brew 21:1 Probe

We have actually seen this solution in the previous section. Recall from Fig-ures 2.28 and 2.29 that the 1000Ω, 0.5pF passive probe had very good frequencycharacteristics. The home brew probe that we are to look at has these parame- home brew probeters.

Figure 2.30 shows the general configuration of the home made probe. Ifsimply consists of a resistor in series with a 50Ω coaxial cable. The coax isconnected to the 50Ω input of a high bandwidth CRO.

Remark 2.16 The home brew probe approximates the circuit of Figure 2.31.Notice that in this probe the capacitance is parallel to the 1000Ω resistor, andthis combination is in series with the input impedance of the50Ω coaxial cable. Inaddition there is the source resistance RS which represents the output impedanceof the driving gate.

The frequency response of this probe, instead of having a pole, has a zero andpole produced by 1000Ω in parallel with CS and in series with the gate outputimpedance RS. If CS is very small then the zero will be at a very high frequency.The CS capacitor is the parasitic capacitance across the 1000Ω resistor, and isusually ≤ 0.5pf.

The fact that the frequency response contains a zero, is itself, a better char-acteristic. This will mean that the higher frequencies are emphasised, ratherthan attenuated.

The total input impedance into this probe is 1000Ω + 50Ω = 1050Ω. Thecoax looks resistive, therefore the only capacitance is associated with the shunt


I

50

To 50

termination at

scope

1000

Sense groundloop

Figure 2.30: A home brew 21:1 high speed probe.

50

CS

1000

RS

Transmission lineimpedance

Figure 2.31: Equivalent circuit for the home brew probe.


Type Lconnector(nH) T10−90%(nsec)RG-58 BNC twist-on 1.0 0.022RG-58 BNC double-crimp 0.5 0.011RG-174 BNC double-crimp 0.5 0.011RG-8 N-type 0.2 0.004

Table 2.6: Inductance and rise time of male coax connectors.

capacitor between the ends of the resistor, which is typically about 0.5pF fora 1/4 watt resistor (this can be lowered by using a 1/8Watt resistor, but onemust be careful about power dissipation with this).

The input voltage is undergoing voltage division, and the ratio is:

vscope =50

50 + 1000vs = 0.048vs (2.70)

Therefore with the scope set to 50mV/div the vertical sensitivity is 0.05/0.048= 1.04V/div. One can use the vertical sensitivity to tweak the vertical scalingto 1V/div if necessary.

The advantages of this probe are: advantages of thisprobe

• The DC input impedance is 1050Ω with makes the loading on a 25-75Ωsource small.

• The shunt capacitance is very small meaning that the loading does notchange dramatically until very high frequencies.

• The rise time of the probe is very fast.

Remark 2.17 The price one pays with this probe is that the voltage range isseverely limited due to the high attenuation of the probe. This may be a prob-lem with many analogue signals, but the most common digital signals have highenough voltage values that this is not a problem.

The rise time of this probe is dominated by three factors:

1. The rise time of the BNC connector

2. The rise time of the coaxial cable

3. The rise time of the sense loop.

One would not normally think of a connector having a rise time. For slowsignals it effectively hasn’t a rise time, but at the frequencies being dealt with inhigh speed digital systems the rise time can be significant. The rise time arisesfrom the series inductance introduced in the 50Ω at the point where the shieldspreads out away from the centre conductor to connect to the BNC fitting.Table 2.6 shows the series inductance associated with several types of coaxconnectors and the T10−90% time constant that goes with these inductances. Ifthe coax cable has to be terminated at the scope then one should ensure that agood quality termination is used, else there will be further rise time degradation.

The next part of the propagation path of the signal in the probe is the coaxcable itself. A coax cable has a frequency response – i.e. there is a frequency at


which the attenuation in the cable is 3.3dB, this corresponding to the frequencyknee point. Therefore we can apply (2.1) to find the rise time. However, inthe case of coax cables this expression only works for short lengths of cable.Note that at high frequencies the attenuation is proportional to the square rootof the frequency, and this fact can be used to interpolate between attenuationpoints in the cable manufacturers catalogues. Table 2.7 shows the rise timecharacteristics for some common cables.18

Feet TRG-174(nsec) TRG-58(nsec) TTG-8(nsec)1 0.004 0.002 0.00022 0.014 0.006 0.0013 0.032 0.014 0.0024 0.056 0.024 0.0045 0.088 0.038 0.00610 0.35 0.15 0.02520 1.4 0.61 0.1050 8.8 3.8 0.64

Table 2.7: Rise time of some coaxial cables.

The final section of the signal propagation path that we are interested inis the probe sense loop. This loop introduces inductance to the signal path,in a manner similar to that introduced by the probe lead in Section 2.6.5.2.However in this case the 1000Ω resistance dominates the impedance of thispath and this decreases the influence of the inductance substantially. This canbe seen quantitatively by considering the time constant of the loop, L/R. For agiven L then the time constant is reduced for a large R. This effect can be seenin Table 2.8.

Loop diameter (mm) Lsense(nH) Trnsec2.54 3.9 0.015.08 11.4 0.0212.7 31.0 0.0625.4 80.0 0.1750.8 200.0 0.42127.0 500.0 1.1254.0 1220.0 2.6

Table 2.8: Rise time of home brew probe sense loop.

We are now in a position to calculate the rise time of our home brew probe.rise time of ourhome brew probe Assume that we have built a probe with 5 feet of RG-174 double-crimped BNC

connector and a probe loop of 12mm. Considering Tables 2.6, 2.7 and 2.8 wecan develop the expression for the rise time of the probe as:

Trcomposite =√

(TBNC)2 + T 2cable + T 2

loop

=√

(0.011)2 + (0.088)2 + (0.06)2

= 0.107nsec (2.71)

18These figures are taken from [1], where the lengths are quoted in imperial measurements.


The home brew probe has a very fast rise time.The rise time can be further improved by the use of a “speed-up capaci-

tor”. This involves intentionally putting a capacitor in parallel with the input “speed-up capaci-tor”impedance of the coaxial cable. Therefore we have an equivalent circuit of the

form shown in Figure 2.32. If we write the transfer function for this circuit weget:

vin(s)vs(s)

=Rin

Rin + Rs

[(1 + sCsRs)

1 + s(Cs + Cin) RinRs

Rin+Rs

](2.72)

Therefore there is a zero at an angular frequency of CsRs and a pole at (Cs +Cin)RinRs/(Rs + Rin). The Cs capacitance is defined by the capacitance ofthe resistor Rs (which is the 1kΩ resistor for the home brew probe). The Cin

capacitor is a capacitor that the user can introduce. Therefore by choosing thecapacitor appropriately one can make the zero and the pole coincide, resultingin a pole zero cancellation. Theoretically the frequency response then becomesflat (which implies that the rise time is zero). Of course in reality the modelof Figure 2.32 is not correct at all frequencies, and this cannot be achieved.However, a significant improvement can be obtained with the correct choice ofcapacitor.

The capacitor value is chosen so that:

(Cs + Cin)RinRs

Rs + Rin= CsRs (2.73)

which after manipulation results in the Cin capacitor being:

Cin = Cs

(Rin + Rs

Rin− 1

)(2.74)

If pole-zero cancellation is achieved then the frequency response of the speed- pole-zero cancella-tionup circuit would look like Figure 2.33.

2.6.6.2 Low Inductance with Conventional Probes

This section will investigate techniques that lower the inductance of the probesense loop whilst using a conventional probe. probe sense loop

One of the simplest techniques is to use a wire loop as shown in Figure 2.34to directly connect the earth shield of the probe to the earth. Alternativelyone can use the blade of a knife to connect the probe ground sheath to a closeground point (assuming that exposed ground points are available at a varietyof convenient locations on the printed circuit board). A third alternative is touse a in-board connector designed for a specific probe as shown in Figure 2.35.Some oscilloscope manufacturers make such connectors. These techniques giveprobe sense loop inductances in the range of 3nH to 30nH depending on typeand the craftmanship employed.

2.6.6.3 PCB Test Points

We have seen in the previous sections that a conventional probe can significantlyinfluence the operation of a circuit being probed. The home brew probe to a


vinv

S

CS

Rin

RS

Cin

Figure 2.32: Speed-up circuit as applied to a CRO probe input.

Magnitude dB

1 sC RS S

1

LNM

OQPs C C

R R

R RS inin S

in S

( )

Resultant response

log10

f

Figure 2.33: Ideal frequency response for a correctly compensate speed-up cir-cuit.


Curly wires

Scopeprobe

Ground

Signal

Figure 2.34: Use of wire connection to lower sense loop inductance.

Printed circuitboard (PCB)

Scope probe

Insert into the PCB

Sleeve

Figure 2.35: Low inductance probe connection.


large extent alleviated this problem, although the loading could still be impor-tant in certain applications. Another approach is to build correctly designedtest points into a circuit a design time. These test points ensure that when thetest pointscircuit is probe the loading does not change, and consequently the signals seenwhen probing will be exactly the same as the signals when the probe is notpresent.

Figure 2.36 shows the general arrangement of an on-board probing set up.Effectively a home brew probe has been built onto the PCB, and the user canuse a link to connect an on-PCB probe load to the signal, or connect the actualprobe cable.

Signal to otherparts of the circuit

1K resistor

50 terminatorGroundvia

Groundvia

Pins shorted when there isno probing

Connect scope to these pinsusing Molex KK connector

50 line

Molex KK Plug

RG-174 50W coaxToscope

Figure 2.36: Layout of a PCB embedded high frequency test point

2.6.6.4 Shield Currents and Ground Loops

When a CRO is connected to a digital system we connect two leads – the senselead and a ground lead. The sense lead is usually the centre conductor of a coaxcable and the ground lead is connected to the shield of the coaxial cable. Letus consider the ground lead – it is usually connected to the CRO ground andto the digital system ground. The CRO ground in turn is usually connected tothe power supply ground via the ground wire in the power cable to the CRO.Figure 2.37 shows this configuration. In this figure the sense wire and shieldconnection are connected together at the digital system. With this configurationthere would be no voltage registered on the scope if no shield current is present.If there is a current, then the voltage that is on the scope is the shield voltage,Vshield.

The shield voltage is induced in the shield due to a shield current causingshield voltagea resistive voltage drop across the resistance of the shield. This current resultsfrom the different ground potentials between the digital system and the scope.These different ground potentials can be caused by a variety of influences –


DigitalSystem

Scope

+-

Vshield

I - Shield current

+

-

Noisevoltage

Green wiresafety ground

Voltage drop across the shield

Sense and groundconnected here

vin

Voltage due to shieldvoltage

Figure 2.37: Noise pick-up due to shield currents.

for example large currents flowing elsewhere in other equipment can cause suchground differences.

Note 2.10 The shield voltages are a result of the shield resistance, and notthe shield inductance. Because of the coaxial nature of the cable the inductanceinduced voltage in the shield and the sense conductor are the same, and thereforeno difference voltage will appear at the CRO amplifier. However, the currentsdue to ground differences only flow in the shield, and this lack of balance betweenthe shield and the sense conductor will result in a voltage at the CRO amplifier.

If you wish to observe the shield voltage in a particular situation do thefollowing:

1. Connect the scope ground and the probe tip together.

2. Move the probe near the circuit without touching anything. Any voltageyou see here is due to magnetic pick-up in the sense loop as described inPractical Issue 2.9.

3. Cover the end of the probe with aluminium foil, shorting the tip directlyto the probe’s metallic ground sheath. This reduces the magnetic pick-upto virtually zero.

4. Now touch the shorted probe to the logic ground. Any voltage you observeis the shield voltage.

There are a number of ways of attempting to tackle the problem of shieldnoise. Of the solutions proposed below, some will work (to varying degrees)and others do not work at all. It should also be realised that the frequencyrange of the noise voltage has a bearing on which techniques will be successfulin alleviating shield voltage problems.

Possible approaches to eliminate shield voltage problems are: eliminate shieldvoltage problems


1. Lower the shield resistance. This is often difficult to do as the probe is acommercial product.

2. Add a parallel impedance between the scope and the logic ground. This isattempting to cause the current to take this path instead of the shield path.Very difficult to get a good low inductance connection for this method.May work if the shunt is significantly shorter than the probe shield.

3. Turn off all parts of the circuit not under test. This will help determine ifthe noise is arising from these parts of the circuit or from somewhere else.Not always practical to do.

4. Put a large inductance in series with the shield. This can be achieved byputting 5 to 10 turns of the probe cable around a good high frequencymagnetic core. If the noise is in the range of 100kHz to 10MHz this workswell. For power supply frequencies the inductance is far too small, and forhigher frequencies the magnetic core is no longer very effective.

5. Redesign the board with ground planes. This will reduce any voltagesdeveloped across the printed circuit board itself. However, will not preventthe shield voltage, just prevents printed circuit board voltage from beingadded to it.

6. Disconnect the scope safety ground. This works as far as the lower fre-quency shield currents are concerned (up to audio frequencies), but in turnresults in a major safety issue. Don’t do this. At higher frequencies cur-rents can flow through capacitors that may be connected from the chassisto the AC input wires, or alternatively across parasitic capacitances in thepower supply

7. Use a triaxial shield on the probe which is connected at one end to thetriaxial shieldscope frame and at the other to the digital system ground. The inner andouter shields are connected together at the scope and digital system. Thisworks on the principle that the skin effect will cause high frequency cur-rents to mostly flow through the outer shield rather than the inner shield.The inner shield has effectively become more inductive (the sense wire issimilarly effected), hence the lower current. The lower shield current inthe inner shield results in a lower voltage drop and therefore less noisevoltage. In a way this is similar to the shunt strap technique, except thatwe are using skin effect to divert the current flow into the alternate path.

8. Use a 1:1 probe instead of a 10:1 probe. This is because the 10:1 probe1:1 probeattenuates the signal we are measuring, but it does not attenuate theshield voltage (since it bypasses the attenuation circuitry in the probe).

9. Use a differential probe arrangement. This is a very good technique butdifferential probeis a little complicated to set up. Differential probing works because it canignore common mode voltages. The shield voltage can be made to appearas a common mode voltage if things are arranged correctly.

Figure 2.38 shows the general arrangement for differential probing. Noticethat the shields are connected together at both ends, but one end of the shieldis not connected to anything. Therefore there cannot be a path for the shield


current. With this configuration the input amplifiers each measure the noisevoltage, but the subtraction of the two signals effectively eliminates this. Mostdual or more channel CROs offer the option of being able to subtract the signalsof two of the input amplifiers. Any differences between the amplifiers can beeliminated by tying the signal wires to a common point and then tweaking thegains until no signal is seen.

DigitalSystem

Scope

+-

+-

+

-

Noisevoltage

Green wiresafety ground

Ground strap

Probe shields tied together

Probe 1

Probe 2

Signal beingmeasured

Probe sense wire todigital ground

Senseloop +

-

Figure 2.38: Differential probing to eliminate shield current effects.

The twisting of the probe cables together is to ensure that any magneticpick-up is the same on both cables, this then being seen as a common modesignal and being eliminated. The ground strap is necessary if the digital systemis floating with respect to the true earth ground. It is to make sure that thevoltage of the digital system does not float above the common mode range ofthe CRO input amplifiers.

The effectiveness of the differential probe technique depends largely on theperformance of the input amplifiers. The common mode rejection ratio of dif-ferential amplifiers is frequency dependent, and sometimes does not go to veryhigh frequencies. However, this technique would be very effective at eliminat-ing shield currents up to several hundred kilohertz without any difficulty formost CROs. High frequency rejection would dependent on the CRO amplifiercommon mode bandwidth.


Chapter 3

Point-to-Point Wiring andTransmission Lines

This chapter is primarily concerned with transmission lines. However, priorto considering them we shall firstly contrast the transmission line approachagainst conventional point to point wiring, as carried out in a wire wrap boardfor example.

3.1 Shortcomings of Point-to-Point Wiring

The following example is taken from reference [1]. Please forgive the imperialunits. The case study tells the story of a now famous Silicon Valley companythat built a wire wrap prototype of its first high speed processor using TTLtechnology. This approach was clearly decided upon because of the flexibilityoffered by the use of wire wrap (it is comparatively easy to make changes), andthe extra speed of getting a prototype built compared to building a printedcircuit board. The basic statistics of the system are shown in Table 3.1.

One of the first steps in deciding to use point-to-point wiring is to figure outwhether one needs to consider transmission line effects. Let us apply (2.7) towork out the length of the rising edge of the input signals:

lr =Rise time (psec)Delay (psec/in)

=2000psec85psec/in

= 23.5in (3.1)

Board size 16in × 20inNumber of gates 600Number of nets 2000Average net length 4inAverage net height above grd 0.2inWire size (AWG 30) 0.01in diameterSignal rise time 2.0nsecKnee frequency 250MHz (=0.5/2.0nsec)

Table 3.1: Statistics for point-to-point wire wrap board

76 Point-to-Point Wiring and Transmission Lines

According to the Section 2.4 states that if line lengths are < lr/6 then we canconsider the lines to behave as lumped circuits and distributed line effects can beignored. In this particular case lr = 3.9in, therefore the designers thought that4in was close enough to regard the line equivalent circuits to be lumped circuits,and transmission like effects would not be significant. The designers thereforemistakenly thought that the circuit would not ring because there would not beany transmission line effects.

The reader of these notes will be aware that a lumped circuit can ring if itcontains capacitive and inductive elements. This is not a sufficient condition forringing though – the Q (known as the Quality Factor) of the circuit is crucial asto whether ringing will occur (see Appendix G for a definition and derivation ofexpressions for Q). If Q < 0.5 then the circuit is over-damped and no ringingwill occur, if Q = 0.5 then the circuit will not ring, but it has the fastest stepresponse without ringing (called critically damped), and if Q > 0.5 then thecircuit will have overshoot and ringing. The larger the value of Q the greaterthe overshoot and the longer it takes for the ringing to die out.

It was shown in Appendix G that the maximum overshoot in a second ordercircuit with Q > 0.5 is:

Vovershoot

Vstep= e

−[

π√4Q2−1

](3.2)

where Vstep the input step (in other words the expected steady state response).One can plug some numbers into this expression and we get for Q = 1 that

the overshoot is 16%, for Q = 2 the overshoot is 44%. It should be noted thatthese are the figures obtained for an ideal step input. We shall see that thedegree of ringing experienced by a circuit is a function of the rise time of theinput signal and the natural ringing frequency of the circuit.

In order to work out the equivalent circuit of the wire wrap wiring we needto know the inductance, capacitance and effective resistance of the wiring andIC drivers. The inductance of the wires can be calculated using (2.22) for aaverage net length:

L = 2x ln[4h

d

]= 2 × 2.54 × 4in × ln

[4 × 0.2in

0.01in

]= 89nH (3.3)

The other relevant parameters for this circuit are R = 30Ω (the typical outputresistance of a TTL or CMOS gate – see Section 2.6.5.2), and a typical inputcapacitive load is C = 15pF. Therefore:

Q =1

Rs

√L

C=

130

√89nH15pF

= 2.6 (3.4)

For an instantaneous step the overshoot can be calculated using (3.2) as:

Vovershoot = Vstepe−[

π√4Q2−1

]= 3.7e−0.616 = 2.0V (3.5)

where Vstep = 3.7, assuming that this is being produced by a lightly loaded TTLoutput.

3.1 Shortcomings of Point-to-Point Wiring 77

The resonant and natural resonant frequency of this particular circuit are(see Appendix G):

Fresonant =1

2π√

LC=

12π

√89nH × 15pF

= 137.7MHz (3.6)

Fnatural resonant =12π

√1

LC−(

R

2L

)2

=12π

√1

89nH−(

302 × 89nH

)= 135MHz (3.7)

We know that for a resonant system to resonate one needs to be supplyingenergy at the frequency that the system wishes to resonant at (just think of atypical resonant system such as a swing – one must push it at the frequency atwhich the swing naturally swings). In this particular circumstance we know thata switching edge contains a wide spectral content up to 250MHz. Therefore therewill be significant energy in the range of 135-138MHz to excite the resonance inthe system.

If one thinks a little further in the frequency domain, we know that:

Fresonant =1

Tperiod(3.8)

and:Fknee =

12Tr

(3.9)

If Tr = Tperiod/2 then:Fknee = Fresonant (3.10)

Therefore if the rise time of the input is greater than half the period of thenatural resonant frequency then the oscillations will be small. If, on the otherhand, the rise time of the input is shorter than the natural resonant period thenthe oscillations in the circuit will be significant.

In conclusion, the wire wrap board built by our Silicon Valley company hadsignificant ringing problems.

3.1.1 EMI Radiation

EMI is an abbreviation for Electromagnetic Interference. It refers to the elec- Electromagnetic In-terferencetromagnetic radiation that emanates from electrical circuitry. It is well known

that circuits that have large loops with rapidly changing currents in them willradiate significant amounts of broadband radiation.

Wire wrap inherently leads to relatively large loops. This is due to thedistance that separates the wires from the ground plane (assuming there isone). It would be even worse if there is no ground plane, and the board isrelying on other wire wrap nets to supply the return paths for currents. Thenet result in either case is that there is a significant loop area that the currentsflow around.

Transmission lines inherently provide very small loops that the currents flowaround. The return currents will automatically tend to flow in the groundplane under the conductor. The conductor itself has a very small separation


from the ground plane, and this also limits the area and provides a degree offield cancellation. For example, if one has a track on a ground planed printedcircuit board, with the track separated from the plane 0.005in, it will radiate32dB less field energy per wire compared to the situation in a typical wire wrapboard, where the wire is 0.2in above the ground plane.

If one is building a wire wrap board it is very important to get the wires asclose to the ground plane as possible. Unfortunately this is not always possible.

3.1.2 Crosstalk

We have previously discussed crosstalk in general (both capacitive and inductive– see Sections 2.5.3 and 2.5.4). The bottom line in relation to inductive mutualcoupling was, that if one has conductors close together with large loop areas,then there will be significant coupling between them. The other main conclusionis that inductive coupling is usually more significant than capacitive coupling.

In this particular case, as discussed in the previous section, the wiring loopsare relatively large. Therefore one would expect significant mutual coupling.Let us now generate some numbers to verify this assertion. Assume that wehave two average length wires on the board running parallel to each other. Ifwe apply (2.38) we can write for the mutual inductance between the wires as:

Lm = L

[1

1 +(

sh

)2]

= 89nH

[1

1 +(

0.20.1

)2]

= 71nH (3.11)

This value of mutual inductance is very high – it is not much different from theself inductance of the wire, which means that a lot of the flux density lines ofone wire loop are linking to the other wire loop.

To work out the crosstalk in this situation we need to use the expression(2.50) for di/dt when there is a capacitive load:

di

dt=

1.52∆V

T 210−90

C =1.52 × 5.7

(3.6 × 10−9)215 × 10−12 = 1 × 107A/s (3.12)

Note that we are using 3.7V as a step TTL input, and then adding the maxi-mum 2.0V overshoot. In addition the rise time of the signal is the rise time ofthis overshooting signal, which we are estimating to be the time to the initialmaximum overshoot, which from (G.35) is 3.6nsec.

The crosstalk is:

vm

Vsteady state=

Lmdidt

Vsteady state=

71 × 10−9 × 1 × 107

3.7= 0.19 = 19% (3.13)

Note that we have used the normal steady state value of the voltage in thedenominator in this expression rather than the overshoot value.

A crosstalk value of 19% is very large. In absolute terms this is 0.7V, whichis almost the switching level of TTL. With this amount of crosstalk this circuitwill not work. It should also be noted that the above calculations are for asingle wire. If one has a bus system on the board then the crosstalk will be

3.2 Uniform Transmission Lines 79

additive from each wire. This fact also leads one to realise that bundling wirestogether in bus structures so that they look nice on a wire wrap board is nota good idea. It is better to wire the wires directly from point to point so thatthere is a randomness to their relative orientation.

With all the problems cited in this section in relation to the performanceof this board it is not a surprise that the company in question never got it towork, and had to abandon this approach and build a prototype printed circuitboard.

Remark 3.1 The wire wrap circuit example above has been presented to showthe pitfalls of point to point wiring. Given the fast rise-time of modern digitaldevices, point to point wire wrap wiring should no be used.

3.2 Uniform Transmission Lines

Appendix H derives in detail the transmission line equations for a lossless trans-mission line. In this section we shall look at the practical implications of trans-mission line phenomena on the performance of digital systems.

Physically the transmission lines that we encounter in digital systems takeone of the forms in Figure 3.1. The twisted pair configuration is called a balancedconfiguration, since the signal flows out on one wire and returns on the other.The other configurations are not balanced, since the return path has a differentphysical configuration than the the other signal path. In the case of groundplane based systems the ground plane is usually shared with a lot of othersignal returns.

In one considers the ideal transmission line as discussed in Appendix H thenwe can say that they have three basic properties:

• They in infinite in extent in the positive and negative directions.

• Signals which propagate along the line are undistorted – this implies thatthe line has an infinite frequency response.

• Signals do not attenuate as they propagate – i.e. ideal lines are lossless.

Remark 3.2 The properties of the ideal transmission line are fascinating. Asshown in Appendix H transmission lines can be modelled as LC circuit elements,which normally form frequency selective networks. However, when they areconnected together in a distributed fashion (as in a transmission line) then thedelicate balance between the inductance and capacitance of the line leads to theeffective impedance of the line appearing to be resistive. Because a resistor is nota frequency selective component then the line has an infinite frequency response.

3.2.1 Measurement of Distributed Parameters

One issue that was not considered in Appendix H was the measurement of thedistributed parameters of an actual transmission line. A simple and reasonablyaccurate approach is shown in Figure 3.2. This diagram shows a 20cm length ofRG-58/U coaxial cable. The capacitance of the cable is measured using a goodcapacitance metre. This value turns out to be 24nF. Note that the cable is opencircuit in order to carry out this measurement. Similarly, in order to measure


Coaxial cable Microstrip

Twisted pair Stripline

Outer jacketOuter shield

Inner dielectric

Inner conductor

Conductor

Dielectric

Ground plane

Ground plane

Ground plane

Jacket (dielectric) Conductors

ConductorDielectric

Figure 3.1: Physical configuration of different types of common transmissionlines.


the inductance of the cable we short circuit one end of the cable, and again usinga good quality measurement bridge we are able to measure the inductance ofthe cable length. In this particular case this turns out to be 50.4nH. We canalso measure the resistance of the cable with this configuration if we have accessto a high sensitivity resistance bridge. To get the per unit length values simplydivide by the length of the cable.

L = 20cm

L = 20cm

Leave end ofline open

Short outend of line

C = 24pFC/cm = 1.2pF

L = 50.4nHL/cm = 2.52nH

Measurecapacitancehere

Measureinductanceand/or seriesresistancehere

Figure 3.2: Experimental set-up to measure transmission line distributed pa-rameters.

3.2.2 Alternative Way of Deriving Characteristic Impedance

The characteristic impedance of a lossless transmission line was formally derivedin Appendix H. However, in this section a more heuristic approach is used toderive the characteristic impedance. The following discussion is with referenceto the situation portrayed in Figure 3.3.

Figure 3.3 shows a pulse that is being transmitted down a transmissionline. It is shown in Appendix H that the velocity of a pulse or waveform in atransmission line is:

v =1√LC

(3.14)

where L the inductance per unit length, and C the capacitance per unitlength.

At some position in the line denoted as X we have a delayed version of theinput, and similarly at position Y . Therefore the time to transverse the distanceY − X is (Y − X)/v = (Y − X)

√LC. As the pulse moves from position X to

position Y the capacitance of the transmission line has to be charged. The totalcapacitance of the line for this distance can be calculated as follows:

CXY = (C)(Y − X) (3.15)

where C the capacitance per centimetre, and therefore the total charge re-quired to charge this capacitance is:

q = CXY V = V C(Y − X) (3.16)


+

-

X

Y

( )X-Y

Input voltage step

Delayed version of input at position X

Delayed version of input at position Y

t0

t1

Time delay = t t Y X LC1 0

( )

Figure 3.3: Voltage pulse in an ideal transmission line.

We can work out the current required to charge this capacitance if we knowthe time that it takes for the waveform to traverse this region. As shown inFigure 3.3 this time is:

td = (Y − X)√

LC (3.17)

therefore:

i =q

td=

V C(Y − X)(Y − X)

√LC

(3.18)

To find the characteristic impedance we form the ratio of V/i giving:

R0 =

√L

C(3.19)

Typical impedances range from 10Ω between the inner and outer shields oftriaxial cable, to 300Ω for balanced cable used for television antennae. Figure 3.4shows typical dimensions for 50Ω and 75Ω characteristic impedances on printedcircuit boards. Refer to Section I.3.12 for the general equations to work out thecharacteristic impedance of microstrip and strip lines.

3.2.3 Physical Explanation of Reflections

As a wave travels down a transmission line Kirchoff’s Laws must apply at everysingle point. When the wave reaches the end of the line, these laws must stillhold. If the line is terminated in its characteristic impedance then, as shownabove, Krichoff’s Laws will hold, since the characteristic impedance is such thatKirchoffs Laws hold all the way along the line. Therefore, as far as the travellingwave is concerned the end of the line looks like an infinite length transmissionline.


H H

H

8H

3

H H

H 2H

Microstrip Microstrip

Stripline Stripline

75 50

All substrates: FR-4; =4.5accuracy = 30%

ER

r

0

Figure 3.4: Typical dimensions of PCB traces to produce 50Ω and 75Ω charac-teristic impedances.

However, if the line is terminated with a short circuit then we know thatthe voltage at this point must be zero. We also know that when the reflectionson the line settle out (assuming that the line has some losses in it, as all realtransmission lines do) then the voltage at any point on the line must be zero.Consequently, since the short circuit forces the zero terminating voltage, thena reflected wave is generated at the termination that has an equal an oppositepolarity to the incident wave. The incident and reflected wave are added (sincethe system is linear and superposition holds) to give the resultant wave. Thereflected wave flows back toward the source.

Eventually the wave reflected from the end termination will reach the source.If the source is voltage source, then the voltage here must be fixed to the sourcevoltage. Consequently then will be another inversion of the incident wave (whichin this case is the reflected wave from the termination) to give a resultant volt-age equal to the source voltage. Therefore, as with the end termination, thereflection is produced such that the end boundary condition is satisfied.

The initial current flow into the transmission line is equal to Vs/R0. The zeroimpedance at the end of the line means that the current is unconstrained – i.e.one can have any current flowing into this termination and still have no voltageappearing across the termination. Therefore it is the voltage constraint thatdetermines what the reflected waveform is, and the current simply follows suit.The negative reflection results in doubling of the resultant current at the endtermination, this eventually reaching the source where its value again increases,and a further reflection occurs. Consequently the current continues to build upin the line, and for an ideal line will go towards infinity as t → ∞.

One can mount similar arguments if the end of the transmission line is ter-minated with an open circuit. In this case when the incident wave reaches the


open circuit the current must be zero, where as the voltage is unconstrained.In order for the current to be zero there must be a current flow in the oppositedirection to the incident current. This means that there must be an equal volt-age pulse, but in the opposite direction, flowing down the line. Therefore thecumulative voltage at the end termination at this incident is twice the incidentvoltage pulse. The reflected voltage will produce an equal, but opposite di-rection current, flowing down the transmission line, and therefore the resultantcurrent is zero. What happens after this is determined by the nature of the load.If the load appears as an AC short circuit, then the open circuit reflection willbe reflected as per the short circuit reflection above so that the source voltageconstraint is satisfied.

3.3 Modelling of Transmission Lines

The most accurate method of modelling a transmission line is to use a specialisedfinite element package designed to model electro-magnetic systems. One simplyinputs the physical configuration of the line, generates a finite element grid, andthen run the FE software to develop the magnetic and electric field patterns.The post-processing software allows one to calculate the inductance, capaci-tance, conductance and resistance per unit length of the line. This approach,however, is very complex and numerically intensive. A more practical method,that delivers good results if the correct parameters are used, is to model thetransmission line as a set of lumped LC sections (or LCRG if one wants a moreaccurate model). Using this modelling approach one can use a circuit simulationpackage (like Spice or Saber) as the simulator.

For digital transmission lines the LC model is usually accurate enough. Thequestion then arises as to how many sections one requires to accurately modelthe line. A rule of thumb is to use that there should be 10 or more segmentsover the length of the rising or falling edge on the line. If we assume that theline as a length of x, v is the propagation velocity, and Tr is the rise or fall timeof the edge, then the above can be stated as [9]:

num of segments ≥ 10(

x

Trv

)(3.20)

where Trv is the length of the rising edge. The term xTrv is the number of rise

edge lengths along the transmission line, and therefore we are ensuring thatthere are more than 10 segments for each of these.

If the C and L parameters for the transmission line are given as the C or Lper metre, then the segment values of these are:

Csegment =(x)(C/metre)

num of segments(3.21)

Lsegment =(x)(L/metre)

num of segments(3.22)

and so on for the R and G values if applicable.Figure 3.5 shows the Saber model of a terminated transmission line using

coupled LC sections. The accuracy of this line is dependent on the rise time ofthe signal on the line.

3.4 Some Practical Effects in Transmission Lines 85

4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH

3.0Vstep

1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF

p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11

Figure 3.5: Model of the transmission line using coupled LC sections.

3.4 Some Practical Effects in Transmission Lines

In all the discussion thus-far we have considered the transmission line to belossless. However, as in all room temperature conductors, those in transmissionlines have resistance. Therefore the transmission is not lossless. Generally theimplications of this loss on the transmission of pulses down the line is that theysuffer attenuation and distortion. The latter point means that the line no longerhas an infinite frequency response.

3.4.1 Skin Effect

As mentioned in the section above a normal transmission line has a distributedresistance. However, the real situation is a little more complicated, especiallyat high frequencies, due to the skin effect.

The skin effect is due to an alteration in the distribution of current in conduc-tors as frequency increases. At DC the current through a conductor is uniformacross the cross-section of the conductor. However, at higher frequencies thecurrent begins to crowd on the outside edge of the conductor, only penetrating asmall distance toward the centre of the conductor. There is virtually no currentflowing in the centre of the conductor.

There are two ways of heuristically explaining this phenomena. One in-volves carrying out the following thought experiment. Imagine the conductorsliced length-wise into concentric cylinders. Because of symmetry arguments nocurrent would flow between the cylinders, and all the current is considered to beflowing longitudinally down the wire. If one considers the inner most cylinder– its inductance will be larger than an outer cylinder due to its small diameter.Therefore the current will flow where the back emf in the wire is less, which istowards the outside of the wire.

Another explanation (which I like because of its more fundamental expla-nation) is to consider the application of Lenz’s law inside the wire. ConsiderFigure 3.6. There is an increasing current flowing into the page, and the fluxdensity lines produced by this current are shown. Because the flux density isincreasing, and these lines are inside a conductive material, there will be Eddycurrents induced in the conductor in such a way as to generate a field whichopposes the one produced by the primary current. Consider the shaded areain the figure. The currents produced around this area to oppose the increasingflux that is orthogonal to it are shown as i1, i2, i3, i4 on the loop. Note the di-rections of the currents. The current i2 along the outside of the conductor is inthe same direction as the current primary initiating current, therefore it tendsto reinforce. However, current i4 is in the opposite direction to the initiatingcurrent in the centre of the conductor. Therefore the current will be less here.


Consequently there will be more current at the outer surface of the conductorcompared to the centre. As the frequency of the current increases then the rateof change of the flux density increases and therefore the voltage induced inter-nally in the wire increases, and consequently the crowding of the current on theouter surface of the wire increases.

This effect can be considered to be happening on an infinitesimally smallelements, therefore the currents i1 and i3 will cancel and there is no net currentin the radial direction.

Area A

Flux densitylines

i

Wire

i1

i2

i3

i4

Figure 3.6: Lenz’s Law explanation of the skin effect.

At high frequencies the average depth of the current penetration, calledthe skin depth, is quite shallow. The current density falls exponentially as weskin depthapproach the centre of the conductor. The expression for the skin depth is:

Skin depth =[

2ρ

ωµ

] 12

(3.23)

where:

ρ the material resistivity

ω the applied frequency in rad/sec

µ the magnetic permeability of the conductor

As one might well imagine the main effect of the skin effect it that the resis-tance of a wire increases with increased frequency. It should also be noted thatthe skin effect is the same for a round conductors as it is for square conductors.

Skin effect begins to become significant for a round conductor when the skindepth becomes less than the radius of the conductor. This is the point wherethe AC resistance of the conductor will begin to rise. The rise is proportional

3.4 Some Practical Effects in Transmission Lines 87

to the square root of the applied frequency. For a flat rectangular conductorthe critical depth is half the conductor thickness.

An approximate expression for the resistance of a conductor at from DC toan arbitrary frequency is:

R(f) = (RDC)2 + [RAC(f)]2 12 (3.24)

where:

RDC the DC resistance

RAC =(5.4864 × 10−7)(fρr)

12

πd(3.25)

where:

d wire diameter in cm

RAC the AC resistance in Ω/cm

ρr relative resistivity compared to copper (Copper = 1.00)

f frequency in Hz (3.26)

One can get a feel for the magnitude of the resistance changes with skineffect from Figure 3.7.

101 103 105 107 109

Frequency (Hz)

101

10 1-

10 3-

10 5-

10 7-

Res

ista

nce

(Ohm

/in)

Figure 3.7: Resistance of AWG 24 round wire (diameter = 0.02in) with fre-quency (reproduced from [1] page 158).

Since skin effect is a surface phenomena then increasing the surface areashould decrease the effect. This is what happens. Litz wire consists of multiplestrands of very fine wire, each strand insulated from the others and woven in aspecific weave pattern. This weave ensures that each individual wire is subject to


similar magnetic forces which ensures equal currents flow in each of the strands.Litz wire is very useful up to frequencies of 1MHz. Beyond this it is very difficultto keep the currents in the strands balanced.

3.4.2 Proximity Effect

Another phenomena that occurs when high frequency currents flow throughwires is the proximity effect. This effect causes the current to tend to crowd inthe sections of each wire that are closest to the other wire – see Figure 3.8 foran illustration of this.

+ -

Current tends to crowd here

Figure 3.8: Example of the proximity effect in round conductors.

When currents flow in the same direction in two parallel wires the wiresexperience a force that tends to pull the wires together. Similarly if the currentsare in the opposite directions the wires tend to repel each other. These forcesoccur for all currents from DC upwards. This is not the proximity effect.1 Theproximity effect only occurs when high frequency currents are present. Thereasons for the effect are similar to those for the skin effect. The currents willtend to distribute themselves in the wire in order to lower the inductance of theloop of current. Clearly this will occur if the currents flow around the inside edgeof the loop as opposed to the outside edge. Under this condition the currentsexperience less back-emf, this effect forcing the current distribution.

The proximity effect at equilibrium is determined by the ratio of wire separa-tion between centres, to the wire diameter. The effect is most pronounced whenwires are nearly touching. The effect will increase the AC resistance above thatfrom just the skin effect alone. Proximity effect, unlike the skin effect, tends toplateau at rather low frequencies.

1Proximity effect does not exert any physical forces on the wires.

3.5 Termination of Transmission Lines 89

3.4.3 Dielectric Losses

If one places fibre glass printed circuit board material into a microwave ovenand turn in on the material will heat up. The same applies to many insulationmaterials. This heat is generated due to losses in the material.

The dielectric materials used in transmission lines similarly are affected bythe fields they are subjected to. The heat in this situation translates to sig-nal attenuation (since it is the signal that is supplying the energy to cause theheating). For most printed circuit board materials the dielectric losses are neg-ligible for digital frequencies below 1GHz. For higher frequencies the dielectriclosses can begin to become appreciable, and other materials based on ceramicsubstrates may have to be used.

For long wires the dielectric properties can be more critical. For example,typical PVC insulation used in telephone wire has measurable dielectric loss at10MHz, and it continues to increase with increased frequency. Dielectric lossesare usually lumped with the skin effect losses in an overall dB loss model of aline.2

3.5 Termination of Transmission Lines

Appendix H develops some of the theory behind transmission lines. This sectionwill not repeat this theory but will consider some of the practical implicationsof it.

One interesting way of looking at transmission lines is in the frequency do-main rather than the time domain. An advantage of this approach is that itdoes not make a distinction between short lines and long lines – in other wordsone does not have to worry about the distinction between lumped circuits anddistributed circuits as much.

Let use consider the transfer function derived in Appendix H, (H.166), whichis for a lossless transmission line. We shall repeat it here for convenience:

−→V L−→V s

=Z0ZL

(ZsZ0 + Z0ZL) cos(βl) + j(Z20 + ZsZL) sin(βl)

(3.27)

where:

l length of the transmission line

β = ω√

LC =ω1√LC

=ω

vrad/m

⇒ βl =ωl

v= ωt

Since the line is lossless then we can simplify the expression for the charac-teristic impedance a little as there is no imaginary component to it. ThereforeZ0 = R0.

Let us consider the situation where we are exciting the line with sinusoidalvoltages under various termination conditions. Firstly let us consider the load

2This is one reason that ADSL connections hace a restriction with respect to the distancethat the subscriber is from the exchange. The transmission lines are conventional twisted pairphone lines.


as a short circuit. Clearly if ZL = 0 in (3.27) then we get:∣∣∣∣∣−→V L−→V s

∣∣∣∣∣ = 0 (3.28)

which is an obvious result. It is comforting that the transfer function expressiongives the correct result.

Now let use consider the load as an open circuit – i.e. ZL = ∞ and thesource impedance Zs = 0. If these values are substituted into (3.27) then weget:

−→V L−→V s

=Z0

Z0 cos(βl)=

1cos(βl)

(3.29)

If l = 0 then clearly−→V L =

−→V s, which makes intuitive sense since one has a zero

length line. Also note that if βl = π/2 then−→V L/

−→V s = ∞.3 This corresponds

to a quarter wavelength transmission line, since λ = 2π/β (see (H.130)). Ifβl = nπ where n = 1, 2, 3 · · · then we get

−→V L/

−→V s = ±1. This corresponds to a

line that is multiples of half a wavelength on the transmission line.Let us consider an open circuit load and a source impedance the same as

the characteristic impedance – i.e. will are considering the case where we haveZL = ∞ and Zs = R0. If we let ZL → ∞ in (3.27) then we get:

−→V L−→V s

=R0

R0 cos(βl) + jR0 sin(βl)(3.30)

therefore: ∣∣∣∣∣−→V L−→V s

∣∣∣∣∣ =R0

R0

√cos2(βl) + sin2(βl)

= 1 (3.31)

Therefore the voltage at the load end of the line is the same as the voltage at thesource. This is known as source or back matching, and intimately relies on thereflection being produced at the open circuited load end of the line. However,it should be realised that the waveform at the source end of the line will bedistorted. Initially when the pulse is applied the voltage at the source end ofthe line will be:

−→V sl =

Zin−→V s

Zin + Zs=

R0−→V s

R0 + R0=

12−→V s (3.32)

This initially launched voltage in the line will reflect totally at the load endof the line, and hence double in value which obviously brings it back to

−→V s.

However, the reflected wave will then propagate back to the source where it willbe absorbed by the source impedance. The voltage at this point will then be−→V s.

Now consider the situation where one has a source termination of Rs and aload termination of R0. Substituting these values into (3.27) one can get:∣∣∣∣∣

−→V L−→V s

∣∣∣∣∣ =R0

Rs + R0(3.33)

3This implies that if−→V s = ε, where ε is a very small value, then

−→V L = ∞. Therefore the

line is resonating.


i.e. the line is acting as a voltage divider.Finally, consider the situation where the load is forward or load matched –

i.e. ZL = R0 and Zs = 0. Substituting these values into (3.27) one gets:∣∣∣∣∣−→V L−→V s

∣∣∣∣∣ = 1 (3.34)

Therefore, as with the back termination one does not get any reflection, andtherefore the transfer function is 1.

If one considers the phasor form of the transfer function:

−→V L−→V s

=1

cos(βl) + j sin(βl)(3.35)

one can see that there is a phase shift of − tan(βl) in the signal. This fact shouldbe clear from a consideration of the physics of a signal propagating at a velocitydown a line.

3.5.1 General Effects of Source and Load Impedance

It was shown in Appendix H that one can construct a relative transfer function(i.e. with unity initial amplitude) for an infinite or semi-infinite a transmissionline of the general form:

H(ω) = e−x√

(R+jωL)(G+jωC) (3.36)

which can be written more succinctly as:

H(ω) = e−x(α+jβ) = e−xγ (3.37)

using the γ definition in (H.112). The H(ω) function describes the amplitudeand phase of a sinusoidal waveform that is propagating down a transmissionline, and an explicit form of the function can be seen in (H.121) (note thatthis equation also contains the initial amplitude whereas (3.37) doesn’t). Thedistance down the line is indicated by x.

Remark 3.3 The correspondence between the H(ω) representation and the ac-tual signals that propagate down the line can be more readily seen by the use ofphasors. From Appendix H one can write:

−→V 1(x) =

−→V 1H(ω) (3.38)

where−→V1(x) denotes the voltage phasor at any point x down the transmission

line, and−→V 1 denotes the input phasor voltage (at x = 0), which can be written

as:−→V 1 = V1e

jθV (3.39)


We can therefore expand the frequency domain expression into its time do-main form as follows:

−→V1(x) = V1e

jθV e−xγ

= V1ejθV e−xαe−jxβ

Using the definition of the phasor to time domain conversion:

⇒ v(t) = R−→V1(x)ejωt= RV1e

−xαej(ωt−xβ)= V1e

−xα cos(ωt − βx) (3.40)

One can see from (3.40) that the voltage along the transmission line is afunction of α and β, and hence γ. Equation (3.40) specifically shows that theamplitude of the voltage decreases as one travels down the line (i.e. decreaseswith x), and at any specific point x along the line the voltage varies with respectto time as a sinusoid.

The above analysis shows that H(ω) captures all the information required toascertain the variation of the voltage with respect to time and distance along thetransmission line.

The acceptance function for a transmission line is the transfer function re-lating the signal amplitude and phase at the beginning of the line to that of thesource itself. Therefore the acceptance function is defined as:

A(ω) =Z0(ω)

ZS(ω) + Z0(ω)(3.41)

At the far end of the line a fraction of the attenuated signal that has propa-gated down the line emerges, and a fraction of the signal is reflected (note thatboth these depend on the load termination). The fraction of the signal thatemerges (i.e. appears at the load) is called the transmission function and isdefined as:

T (ω) =2ZL(ω)

ZL(ω) + Z0(ω)(3.42)

which is derived from 1 + ρ, where ρ is the reflection coefficient.

Remark 3.4 Note that the transmission function states the proportion of thesignal that emerges across the load termination. For example, if ZL(ω) = 0 (i.e.the load termination is a short circuit) then clearly T (ω) = 0, which means thatthere is no signal across the load termination. If on the other hand the loadis an open circuit then there is voltage doubling at the load and therefore thetransmission function is 2.

The reflection coefficient is the ratio of the reflected signal to the incidentsignal and was formally derived in Appendix H and will only be written herewithout proof for the load termination:

ρL =ZL(ω) − Z0(ω)ZL(ω) + Z0(ω)

(3.43)


Similarly the reflection at the source termination is:

ρS =ZS(ω) − Z0(ω)ZS(ω) + Z0(ω)

(3.44)

Let us now consider the situation when a signal is launched down a trans-mission line. Assume a per-unit input signal of 1, therefore the signal at thebeginning of the line is A(ω). At the load end of the line (which is length ldown the line) the signal would be A(ω)Hl(ω). Consequently the signal acrossthe load is A(ω)Hl(ω)T (ω). We shall denote this initial emerging signal as:

S0(ω) = A(ω)Hl(ω)T (ω) (3.45)

The incident signal on the load will in general reflect. This reflected signalis subjected to the attenuation function of the transmission line and a furtherreflection at the source end of the line. This second reflection then continuesback down the transmission line and is again reflected at the load termination,and the process continues. As the reflections continue the reflected signals grad-ually decrease in amplitude (the rate depending on the size of the α parameter),eventually settling out.

If we consider the second reflection, we can write the expression for theincident signal on the source termination as:

[A(ω)Hl(ω)ρL(ω)]Hl(ω) (3.46)

and therefore the reflected signal at the source is:

A(ω)Hl(ω)[ρL(ω)Hl(ω)ρS(ω)] (3.47)

This reflected signal then reaches the load termination again. It is againattenuated by travelling down the line. Considering only the signal emergingfrom the reflected signal we can write:

S1(ω) = A(ω)Hl(ω)[ρL(ω)H2l (ω)ρS(ω)]T (ω) (3.48)

Figure 3.9 shows the series of reflections from the load and source terminationsas the signal propagates up and down the transmission line.

As discussed above this situation continues infinitely. For the nth emergingsignal we can find that the expression is:4

Sn(ω) = A(ω)Hl(ω)[ρL(ω)H2l (ω)ρS(ω)]nT (ω) (3.49)

The total emerging signal is the sum of the all the Sn values for n =0, 1, 2, · · · ,∞. Therefore the final steady state value for the emerging signalis:

S∞(ω) = Σ∞n=0Sn(ω) (3.50)

There is a closed form solution for this infinite sum:

S∞(ω) =A(ω)Hl(ω)T (ω)

1 − ρL(ω)H2l (ω)ρS(ω)

(3.51)

4Note that this expression is only for the component of the incident signal that emergesfrom the line. The total signal at this point is the addition of all the signals present – i.e. theinitial signal plus all the subsequent incident signals resulting from the reflections.


+

ZS

ZL

Z0

A( )H

l( )

Hl( )

Hl( )

Hl( )

Hl( )

T( )

T( )

T( )

A H Tl

( ) ( ) ( )

L( )

L( )

L( )

R( )

R( )

A H H Tl L l S

( ) ( )[ ( ) ( ) ( )] ( ) 2

A H H Tl L l S

( ) ( )[ ( ) ( ) ( )] ( ) 2 2

Some signal reflecting offthe load termination

Signal reflecting offthe source termination

Reflected signal suffersfurther attenuation downthe tx line

Figure 3.9: Diagrammatic representation of the various reflected signals in atransmission line showing the acceptance, propagation and transmission transferfunctions.


Equation (3.51) is the total frequency response function for the transmissionline. The frequency response expressions calculated in Appendix H are for theinitial incident waveform on the termination.

Using (3.51)) we can now revisit the effects of different terminations in amore general setting. Using the expression T (ω) = 1 + ρL(ω) we can write(3.51) as:

S∞(ω) =Hl(ω)A(ω)(ρL(ω) + 1)1 − ρL(ω)ρS(ω)H2

l (ω)(3.52)

If we assume that Hl(ω) is fixed (i.e. the cable parameters are fixed) then wecan alter the ρL(ω) and ρS(ω) functions via the load and source terminationvalues. Note that changing ρS(ω) also modifies A(ω).

Using (3.52) it is possible to ascertain very quickly the effects of the twomain termination types – load or end termination, and source termination.

3.5.1.1 Load termination

In this method of termination involves setting the terminating impedance tothe characteristic impedance of the line. Therefore from (3.43) one can see thatρL(ω) = 0 and T (ω) = 1. Therefore (3.52) can be written as:

Sload term = Hl(ω)A(ω) (3.53)

As can be seen from this expression the input signal simply propagates down theline and none of the signal is reflected back along the line. The magnitude andphase of the signal is totally represented by the propagation characteristic of theline and the acceptance function at the input source to the line. For sensibleterminations there should not be any ringing in the line since there are nodelayed versions of the input signal propagating up and down the transmissionline.

Remark 3.5 Note that load terminations have the undesirable characteristicthat if the driving voltage is high then power is being dissipated in the terminatingresistor. This power can be quite high, since the terminating resistor for mostPCB traces would be to the order of 80-200Ω.

Remark 3.6 The power dissipation problem mentioned in Remark 3.5 can beovercome by using a series combination of a resistor and capacitor in the loadtermination. If the capacitor is chosen appropraitely, then it will be a shortcircuit at the frequencies that approach those in the switching edge. Therefore,these frequencies will see the characteristic impedance terminating resistor asthe load, but the termination will be an open circuit at low frequencies. Con-sequently, there will be no power dissipation under constant output voltage con-ditions. Figure 3.10 shows a conventional load termination and two differenttypes of capacitor based load terminations.

3.5.1.2 Source Termination

This technique sets the source impedance equal to the characteristic impedanceof the transmission line. Therefore the source end reflection coefficient is set tozero – i.e. ρS(ω) = 0. This will prevent the second and subsequent reflectionsfrom occurring, but it will not prevent the initial reflection from the load.


Z0

Transmission lineZ

0C

VCC

20

Z

20

Z

C

2

C

2

(a)

(b)

(c)

vS

vS

vS

Figure 3.10: Load terminations: (a) Conventional termination, (b) Capacitivetermination 1, (c) Capacitive termination 2.


The consequence of setting ρS(ω) = 0 is that A(ω) = 1/2, therefore theinitial signal launched in the line is 1/2 the applied voltage. This can be com-pensated for at the load end by making the transmission function, T (ω) = 2 –this is achieved by making ZL(ω) = ∞. In other words one gets total reflectionat the load, as well as a doubling of the incident wave. This means that thewaveform at the load will be the applied waveform behind the source termi-nation. This reflected waveform then travels back along the transmission linewhere it is totally absorbed at the source.

Remark 3.7 The fact that the signal at the source end is initially 1/2VS canbe a problem if one wishes to use the signal at this end or at points midwayalong the line. The signal is only usable at the load end of the transmissionline using this approach. Note that this contrasts with load terminations, whereoutput signals can be taken anywhere along the length of the line, since there areno reflections along the line.

Remark 3.8 Source terminations do not have the problem mentioned in Re-mark 3.5 of constant power dissipation under high output voltage conditions.

3.5.1.3 Very Short Line

Another way of preventing reflections is to make the line so short that it canbe considered to be a lumped circuit – i.e. the voltage and current distributionalong the line can be considered to be uniform.

If the line is short then this means that Hl(ω) ≈ 1, and hence (3.52) can bewritten as:

Sshort line =A(ω)[ρL(ω) + 1]1 − ρL(ω)ρS(ω)

(3.54)

One can now substitute the expressions for the reflection coefficients intothis short line expression to obtain:

Sshort line =Z0

ZS+Z0

2ZL

ZL+Z0

1 − ZL−Z0ZL+Z0

ZS−Z0ZS+Z0

=ZL

ZL + ZS(3.55)

As can be seen from this expression the line does what we would hope it woulddo it it is short – nothing. The circuit behaves exactly as a lumped circuit.

When can one consider that the transmission line essentially acts as a lumpedcircuit element – i.e. the transmission line must act like a wire which instantlyconducts the voltage from one end to the other. The usual answer is that theline must be much shorter than one-sixth the electrical length of the rising edgeof the signal. We can state this mathematically as follows:

Length 16

Tr√LC

(3.56)

where the parameters are defined as:

Tr rise time of the signal (sec)

L line inductance (H/m)

C capacitance (F/m)

Length maximum line length (m) (3.57)


3.5.2 Capacitive Terminations

Consider the situation shown in Figure 3.11, which shows a capacitor in themiddle of the transmission line. The left hand transmission line effectivelyterminates at the capacitor. Therefore the effective terminating impedance atthis point is the impedance of the capacitor in parallel with the impedance ofthe right hand transmission line.

Z0 Z

0

Reflected signal is a shortbump - negative derivativeof incoming signal

Ongoing signal is degradedin rise time.

Oncoming signal withsharp rise time

Figure 3.11: Transmission line with a capacitive load in the middle.

For simplicity we shall assume that the right hand transmission line is ter-minated with its characteristic impedance, therefore the line impedance seenlooking right from the capacitor is Z0.5 Using this assumption we can calculatethe effect load impedance at the capacitor as follows:

ZL(ω) =1

jωC Z0

Z0 + 1jωC

=Z0

1 + jωCZ0(3.58)

Using this load in the expressions for reflection coefficient we can write:

ρC(ω) =−jωCZ0

2 + jωCZ0(3.59)

Examining the denominator of this expression one can see that the mag-nitude of the frequency component of the denominator is equal to the realcomponent when:

ωCZ0 = 2 ⇒ fC cut-off =1

πCZ0(3.60)

For frequencies at fC cut-off the reflection coefficient magnitude is 1/2, and thereflection is significant. For frequencies fC cut-off the reflection is almost total.

5We could also assume that the line is terminated with an arbitrary termination, but theline is long enough that any reflections will arrive well after the immediate reflections fromthe capacitor.


This can be easily deduced by realising that as ω → ∞ then ρc(ω) → −1. The 2in the denominator becomes irrelevant in relation to the frequency based terms.Therefore one should not use the transmission line with a capacitor attached toit in this fashion under this frequency condition.

If we consider frequencies below fC cut-off then we can write the followingapproximation ρC(ω) = −jωCZ0/2 = −CZ0s/2. The complex frequency do-main operator s is the Laplace transform for the derivative operator. Thereforethe reflection coefficient is acting as a negative derivative operator, with theconstant of differentiation equal to −C(Z0/2). This observation allows us toestimate the amplitude of the reflected pulse as follows:

| V− |= −CZ0

2∆V

Tr(3.61)

where | V− | the amplitude of the reflected pulse in volts, and the othervariables have the normal definitions already established. One can see that therise time of the signal is very important in determining the magnitude of thereflection. If the rise time is slow then the reflected signal may be negligible.

The other aspect of interest in this circuit is the transmitted signal to theright hand section of the line. The normal expression for the transmissioncoefficient is:

T (ω) = 1 + ρC(ω) =1

1 + jωC[

Z02

] (3.62)

This expression shows us that the capacitor acts as a first order low pass filteras far as the signal propagating past the capacitor is concerned. The time con-stant of the filter is C(Z0/2). Therefore the 10%-90% rise time approximately(remembering that the true rise time is Tr =

√T 2

r1+ T 2

r2):

T10-90 = 2.2CZ0

2(3.63)

The net effect is that the rise time of the transmitted edge has been degradedby the presence of the capacitor.

An interesting non-obvious case of single capacitive loading on a line occurswhen tracks go through a 90 angle. This situation is illustrated in Figure 3.12.Ad can be seen from this diagram the effective increase of the line width as itturns the corner causes a discontinuity in the transmission line. It effectivelyadds a small capacitor to this point on the line. One way of overcoming this isto round the corner so that the line width stays the same, but this option maynot be very easy to do depending on the layout software. Another alternative isto chamfer the corner as shown in Figure 3.13, and although it is not obvious,this will achieve the same result and it good for frequencies up to 10Ghz [10].Note that 45 turns require no special treatment.

3.5.2.1 Equally Spaced Capacitive Loads

Consider the situation shown in Figure 3.14. This situation is typical of a bussystem where one has a number of equally spaced integrated circuits sitting onthe same lines (eg. a number of memory chips).

The obvious question to ask in the case of the situation shown in Figure 3.14is: “What is the effect of the capacitive loads on the performance of the transmis-sion line?”. We have leady looked at the case where we have a single capacitor


w

w

w

Effective width larger

Figure 3.12: Right angle track showing origin of additional capacitance.

w

w

0.57w

0.2w

0.2w

Figure 3.13: Chamfered track to match impedance around a right angle corner.


N identical capacitive loads

RL

RS

Z0

CL

CL

+

l cm

Figure 3.14: Transmission line with equally spaced capacitive loads.

on the line, and we saw that it can have a significant effect on the performanceof line depending on the rise time of the signals sent down the line. The effectswhen we have evenly spaced capacitors depends largely on the spacing of thecapacitors relative to the length of the edge of the signals propagating down theline.

If the rising edge length exceeds the spacing of the loads then one can derivea simplified approximation for the behaviour of the circuit. If on the otherhand the rising edge is of the order of or less than the spacing between the loadsthen we get the situation with the single capacitor at end of the nodes where thecapacitors join the transmission line. Therefore there will be multiple reflectionsbouncing between these various nodes resulting in degraded signal quality onthe transmission line.

If we consider the situation where the rising edge is much longer than thespacing between the loads then several capacitors will be involved in determiningthe behaviour of a single edge. Therefore the capacitors are effectively smearedalong the edge. This in effect means that the load capacitors effectively becomepart of the line capacitance. If we doubled the number of capacitors and halvedtheir values and place these along the same length of line the performance ofthe line will not appreciably change. Therefore the capacitors can be thoughtof as continuously distributed capacitance in the form of pF/cm. Therefore thenew distributed capacitance for the transmission line is:

C ′ = Cline +NCL

l(3.64)

This new effective capacitance means that we will now have a new effectivecharacteristic impedance for the line:

Z ′0 =

√L

C ′ (3.65)

One can see from (3.65) that Z ′0 will have a lower value than for an unloaded line.

In fact it is quite easy to end up with very low characteristic impedances for theline, which makes them very difficult to drive effectively with normal bus drivers.The other problem that arises from this increase in effective capacitance is thedelay. We know from (2.5) that the delay per unit length is

√LC ′. Hence for


larger C ′ then longer the delay is for the signals propagating down a line. Thisdelay occurs regardless of whether we can drive the line or not. Depending onthe situation it may be crucially important. For example, if we have a numberof high speed memory chips forming the uniformly distributed load, and thetransmission lines are the address lines, then the delay will cause a skew in theaddress information between the first chip on the transmission lines and the lastchip. This skew effectively lessens the access time of the last chip on the line.For typical values of the SIMM module capacitances and the length of blocksof SIMMs, delays of the order of 5 to 10nsec would not be unusual.

3.5.3 Multi-point Terminations

Up to this point we have been considering a single line and the various ter-mination options for this. However in a practical printed circuit board thereare many instances where a single driver has to drive multiple lines. Obviouslythere are an arbitrary number of configurations that one can have, so we willconsider the very simple case of a single driver driving two lines. Figure 3.15shows several ways that someone may lay the tracks from the single driver.

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z0

Z ?

(a)

(b)

(c)

(d)

Problem with reflectionshere

Problem with reflectionhere

Figure 3.15: Some possible multi-point configurations.


Configuration (a) in this diagram shows an end terminated situation wherethe second line is branched from the middle of the other line. This configurationwill have a problem because of the reflections at the point where the secondline is connected. The results of a simulation of this situation where the lineparameters are L = 4.6nH/cm and C = 1.1pF/cm and each line is terminatedwith 64Ω are shown in Figure 3.16. Note the oscillations in the line. Figure 3.17shows the voltage across the end termination of one of the two lines. Similaroscillations occur on this line due to the reflections from the mid point re-reflecting from the source and re-entering the lines.

Multi-point line

t(s)

0.0 500p 1n 1.5n 2n 2.5n 3n 3.5n 4n

(V)

0.0

2.0

4.0

6.0

(V) : t(s)

Node 5 on line

v(v_pulse.v_pulse1)

Figure 3.16: Voltage just prior to line connection with mid line multi-pointconnection.

If one changes the configuration to that of (b) in Figure 3.15 then we es-sentially have two separate transmission lines, since the voltage source effectivedecouples the lines. The disadvantage of this approach is the we are using endterminations which have high power dissipation properties.

If we adopt the approach shown in Figure 3.15 (c) we get the results shownin Figure 3.18. As can be seen the performance is totally unsatisfactory. Thereare severe oscillations at all points on the lines. The problem is that the returnreflections from the open circuited line ends are not correctly absorbed at theintersection point of the lines. Therefore this leads to further reflections and weend up with the complex waveforms shown. The oscillations are particularlybad in this case due to the magnitude of the reflections that one obtains fromthe open circuits at the ends of the lines.

An alternative for a series termination that we might try is that shownin Figure 3.15 (d), where the line connection has been changed to be at thetermination resistor, and the termination resistor is changed to Z0/2. In thiscase we again get reflections from the open circuit end terminations, and underthe circumstance that the two line lengths are the same these reflections arriveat the source termination together. The initial waveforms launched down thetwo lines will be 1/2V due to the parallel loading of the two lines and the voltage


End termination voltage

t(s)

0.0 1n 2n 3n 4n

(V

)

0.0

2.0

4.0

6.0

(V) : t(s)

End termination voltage

v(v_pulse.v_pulse1)

Figure 3.17: Termination voltage with a mid line multi-point connection.

Graph0

(V

)

0.0

2.0

4.0

6.0

t(s)

0.0 2n 4n 6n 8n 10n

(V

)

0.0

2.0

4.0

6.0

(V

)

0.0

2.0

4.0

6.0

(V

)

0.0

2.0

4.0

6.0

(V) : t(s)

Line 1 end voltage

(V) : t(s)

Mid line voltage

(V) : t(s)

Line 2 end voltage

(V) : t(s)

v(v_pulse.v_pulse1)

Figure 3.18: Waveform plots for a multi-point line with a single series termina-tion and mid point line connection.


division by the presence of the Z0/2 source terminator. The reflected voltagesfrom the open circuit terminations at the end of each of the lines will reachthe junction point at the same time (due to the equal line lengths) and henceone will get 1/2V + 1/2V = V volts at this point. A reflection does not resultfrom this as because the return currents are able to be totally absorbed into thesource terminator (because we have twice the return current and one half thenormal source resistance). The plots for this situation are shown in Figure 3.19

Single source termination R=R0/2, equal line lengths

(V

)

0.0

2.0

4.0

6.0

t(s)

0.0 2n 4n 6n 8n 10n

(V

)

0.0

2.0

4.0

6.0

(V

)

0.0

2.0

4.0

6.0

(V) : t(s)

Line 1 termination

(V) : t(s)

Line 2 termination

(V) : t(s)

v(v_pulse.v_pulse1)

Figure 3.19: Two multi-point lines branching from a Z0/2 source terminator –the lines are of the same length.

If the two lines that split off are of different lengths the situation describedabove no longer applies. The reflections from the open circuit terminations willnot arrive back at the junction at the same time and there will be a numberof oscillations in the system due to this. This effect is shown in Figure 3.20.Here we have the source termination equal to Z0/2 as in the previous case, butone of the lines is half the length of the other. Therefore the reflection fromthis line will arrive back at the junction much sooner from the shorter line, andhence there is a voltage difference at this point some of the return signal fromone line flows into the other. One can see that the termination signals are nolonger satisfactory. Therefore, in general, the technique of using a single sourcetermination for a multi-point system is not going to give good signals.

Note 3.1 It should noted that one cannot daisy chain gates off lines when onehas source terminations, since the signal at intermediate points on the line willhave a two step form. If one uses an end terminator the signal will have thecorrect form as it propagates down the line.

Note 3.2 The use of end terminations of the form shown in Figure 3.15 is notusual in digital systems. The main problem is the drive required to drive the


Single source termination Rs=R0/2 and different length lines

t(s)

0.0 2n 4n 6n 8n 10n

(V

)

0.0

2.0

4.0

6.0

8.0

(V

)

0.0

2.0

4.0

6.0

8.0

(V

)

0.0

2.0

4.0

6.0

(V) : t(s)

Line 1 termination

(V) : t(s)

Line 2 termination

(V) : t(s)

v(v_pulse.v_pulse1)

Figure 3.20: Two multi-point lines branching from a Z0/2 source terminator –the lines are of different lengths.

termination. For example, not many gates would be capable of driving a 65Ωresistive termination to 4 Volts. In addition there is the issue of DC powerdissipation in steady state in these terminations. Generally speaking the seriestermination is much more common. One can also use the split end termination(i.e. two resistors, one connected to +5V and the other to ground, with theparallel combination of the resistors equal to Z0), although these still have manyof the problems of the single termination resistor.

A common way of splitting two lines that is commonly used in communica-tions applications is shown in Figure 3.21. This works on the principle that theimpedance looking from the left hand line (which we will assume is the sourceline) is:

Zin = Z0/3 + (Z0/3 + Z0)‖(Z0/3 + Z0)= Z0/3 + 2Z0/3= Z0 (3.66)

Therefore the impedance looking into the midpoint connection is the charac-teristic impedance of the line. Therefore there should be no reflection at theintersection point. It should be noted that the ends of the two lines at the righthave to be terminated in the characteristic impedance of the line so that thereare no reflections coming back to the junction point. For the reason cited abovethe technique is therefore not useful for digital systems. The other problemis that the signals are attenuated. If the signal on the left line is V, then thesignals propagating down the right lines would be 2/3V. These effects can beseen in Figure 3.22.


Z0

Z0

Z0

Z0

3 Z0

3

Z0

3

Figure 3.21: Multi-point splitter using resistive network.

Waveforms with splitting network

(V

)

0.0

1.0

2.0

3.0

4.0

t(s)

0.0 2n 4n 6n 8n 10n

(V

)

0.0

1.0

2.0

3.0

4.0

(V

)

0.01.02.03.04.05.06.0

(V

)

0.0

2.0

4.0

6.0

(V) : t(s)

Line 1 termination

(V) : t(s)

Line 2 termination

(V) : t(s)

Just before split

(V) : t(s)

v(v_pulse.v_pulse1)

Figure 3.22: Multi-point waveforms using the resistive “splitter” network.


Remark 3.9 The branching technique of Figure 3.21 is used a lot in communi-cations systems to cheaply split signals from antenna. For example, the splitteror diplexer used on home television is often based on this circuit. One needs astrong incoming signal in order to split it in this way.

Remark 3.10 If one has PCB tracks then matching can be achieved by chang-ing the design of the tracks. For example, if the characterisitc impedance of thesource track is Z0 then the impedance of the branches can be made to be 2Z0.This means that the impedance looking into the branch point from the source isZ0. The two branch tracks do not have terminations, and the source is sourceterminated. Because the two branch lines do not have terminations there arereflections at the ends which will double the voltage (which was 1

2V due to thesource termination). These reflected waves then travel back down the branchlines to the line junction point, where they will re-reflect and be partially trans-mitted. If the branch lines are of the same length then the oscillations are nottoo bad, but if the lines are of different lengths then the branch reflections arriveat different times and the resultant waveforms are highly distorted.

Practical Issue 3.1 If one has to branch tracks off each other then attempt tochoose the track sizes to achieve the effect in the previous remark. In additionmake sure that the branch tracks are symmetric as far as possible.

In many practical circuit layouts one has to connect multiple ICs to a signaltrace. An example of this is where there is a global clock line on a circuit board.In this situation it is impractical to run a separate terminated line from theclock source to all the receiving circuits. There are several things that can bedone to make the layout feasible and to maintain the signal integrity.

These trace stubsappear as acapacitor in parallelwith the receiver. End termination

Main transmission line path

Figure 3.23: Poorly designed gate daisy chain with end termination.

Figure 3.23 shows a set of gates daisy chained off a transmission line. Thesmall stub traces to the gate inputs are short enough that they can be consideredas lumped elements. Therefore they appear as extra capacitance in parallel


with the input capacitance of the gate. Consequently the edge of the signal isprogressively degraded as it propagates down the transmission line. The otherpoint to note about this circuit is that it is load terminated, as opposed tosource terminated. Load termination is required in order to ensure that all thegates in the middle sections of the line receive a good quality signal without thetwo stage step that is present when there is a source termination.

Gate pins connecteddirectly to the trace

Fromdriver

Terminatingresistor

Line extends beyondreceiving gate

Figure 3.24: Better design for a gate daisy chain.

Figure 3.24 shows the layout for a better design of a set of daisy chainedgates. The relevant design features shown in this figure are that the gate inputsare connected directly into the track without any stub tracks. This keeps theadded capacitance at the gate points to the input capacitance of the gate, with-out the added capacitance of the stub. Another point about the design is thatthe receiving gates should be positioned the same distance apart (or as near asone can get), the distance being significantly less that the length of an edge onthe trace. This will ensure that the gate input capacitances appear as addedtransmission line capacitance, and will not lead to degraded edges, but just adifferent characteristic impedance. Finally, the last gate should be positionedbefore the end of the line, so that its input capacitance is seen as a part of theline, and not a capacitance across the terminating resistor. This will preventreflections from a capacitance termination.


Chapter 4

Ground Planes and otherPrinted Circuit BoardIssues

This chapter will concentrate on issues related to the lay out of ground planesand tracks on printed circuit boards. These issues are very important if one isto get a printed circuit board that works with the high speed digital technologyprevalent today.

Ground and power planes in high speed digital systems perform three criticalfunctions:

• Provide stable reference voltages for exchanging digital signals.

• Distribute power to all logic devices.

• Control crosstalk between signals.

4.1 Power Planes

A power plane system is used in many modern printed circuit board designs.A power plane system consists of two parallel power planes, one being the pos-itive supply plane and the other being the negative supply (or ground) plane.1

Consider the power planes shown in Figure 4.1.If one considers the two power planes as a lossless TEM mode transmission

line then it is possible to show that the characteristic impedance of the plane isapproximately:

Z0 ≈ η0√εr

(h

w

)(4.1)

where η0 ≈ 377Ω, the characteristic impedance of free space. This transmissionline characterisation of the power planes is complex because of the problems ofcharacterising the line with the terminal ports located anywhere on the plane.

1The presence of two ground planes means that at a minimum one would usually have afour layer PCB – two layers for power distribution and two for signal distribution.

112 Ground Planes and other Printed Circuit Board Issues

h

w

Power planes

l

Figure 4.1: Dimensions of two power planes.

Example 4.1 Consider (4.1) with power planes of dimensions of w = 25cmand h = 0.075cm, the thickness being half the thickness of the typical epoxyfibre glass PCB board (FR-4), which has εr = 4.7. The Z0 is 0.52Ω – thecharacteristic impedance is very low.

Another interesting fact is that the velocity of a wave in the transmissionline depends only on the dielectric for the material:

v =c√εr

=1√

L0C0

(4.2)

where εr the relative dielectric constant, c the speed of light, and L0, C0 arethe inductance and capacitance per unit length. This equation indicates thatthere is a fundamental relationship between the inductance and capacitance perunit length for a transmission line.

Other relevant expressions are those for the capacitance and inductance forthe planes:

C = εrε0A

h= εrε0

wl

h

∴ C0 =C

l= εrε0

w

h(4.3)

Using this expression together with the characteristic impedance expression onecan also calculate the inductance per unit length:

Z0 =√

L0

C0⇒ L0 = Z2

0C0

∴ L0 =

[η20

εr

(h

w

)2] [

εrε0w

h

]

= η20ε0

(h

w

)

= µ

(h

w

)(4.4)

4.1 Power Planes 113

If we consider the line dimensions from the previous example we can calculatethe effective inductance and capacitance per unit length:2

C0 = 4.7 × 8.854 × 10−14 250.075

= 0.138nF/cm (4.5)∴ CT = 25 × C0 = 3.5nF (4.6)

L0 = 4π × 10−9 × 0.07525

= 38pH/cm (4.7)

where l = 25cm.

Remark 4.1 As one can see from the above numbers the power plane has amodest total capacitance and a very low inductance per unit length. Thecombination of the capacitance and the low inductance means that there will bevery low transient voltage drops along the ground plane when a rapidly risingcurrent is drawn from the plane.

4.1.1 Decoupling Capacitors and Power Planes

Of practical interest is where should decoupling capacitors be placed in relationto an electronic component on a power planed PCB. In order to answer thisquestion we shall use the impedance expressions of (H.160), repeated here forconvenience:

Zin = Z0

[ZL cos(βl) + jZ0 sin(βl)jZL sin(βl) + Z0 cos(βl)

](4.8)

If the line is terminated with a capacitor (which is meant to represent a decou-pling capacitor) then ZL = 1/jωC. Let us substitute this into the expressionabove for the input impedance. To enable the expression to be simplified toa meaningful expression we can make a few approximations – we shall assumethat C0l C (which would usually be the case when the C is a decouplingcapacitor), and |βl| 1 (where β = ω

√L0C0) (which again would be the case

for reasonable frequencies – < 500Mhz, and lengths) . Given these assumptionswe can develop the following approximate expression for Zin:

Zin =

√L0C0

[1

jωC cos(βl) + j√

L0C0

sin(βl)]

[√L0C0

cos(βl) + j 1jωC sin(βl)

] (4.9)

Realising the the approximations cited above mean that:

cos(βl) ≈ 1and sin(βl) ≈ βl

then we can simplify the expression to:

Zin ≈1

jωC + jωL0l

1 + C0lC

(4.10)

2ε0 = 8.854 × 10−14 ≈ 136π×109 Farads/cm, µ0 = 4π × 10−9H/cm.


and since C0l/C 1 then 1 + C0l/C ≈ 1 and hence we can write:

Zin =1

jωC+ jωL0l (4.11)

which is simply a series LC circuit.

Remark 4.2 Equation (4.11) shows that an inductance equal to L0l is effec-tively in series with the decoupling capacitor. If one considers a PCB withthe parameters calculated in the previous section (C0 = 0.138nF/cm and L0 =38pH/cm) then the inductance with the capacitor at a distance of 2.5cm fromthe chip it decoupling is 95pH. This is very small compared to the package in-ductances for the capacitor and the chip leads (which are in the nH range). Themain result is that the placement of the capacitor is not critical withrespect to the chip it is decoupling. Therefore there is no need to constrainthe placement and routing too much to get the capacitors close to the ICs.

Remark 4.3 It is interesting to note that the power planes are themselvestransmission lines. Therefore they should be subject to reflections as are thelines we have looked at previously, and this is what happens. If a pulse in in-jected (due to an IC pulling a current from the power planes) then the voltageand current propagate in every direction from the initiating point. When theyreach the edge of the board then there is an open circuit termination and conse-quently a reflection would occur. Fortunately the magnitude of these reflectionsare small due to the small instigating pulse, and the fact that the decouplingcapacitors also have an effect.

4.2 Crosstalk Issues

In the previous chapters we have already considered some of the crosstalk issues,related to the crosstalk between resistors mounted on a ground plane printedcircuit board (PCB), inductive and capacitive coupling between short lines. Itshould be noted that the coupling issue between resistors on a printed circuitboard is very relevant to the line termination of the previous chapter. In thisparticular case one can get significant coupling between the termination resis-tors, especially if they are arranged next to each other on a PCB.

4.2.1 Path of Least Inductance

At low frequency spectral content current flows along the path of least resistancethrough a printed circuit board, including the power planes. However, at highfrequencies the current tends to still take the circuit path that resistors the flowof current least, but in this case the inductance (and not the resistance) is themajor influence on the current path. These concepts are shown diagrammati-cally in Figure 4.2. Notice that the current for high frequency spectral contentcurrents flow through the ground plane under the printed circuit board trace.This path minimises that inductance of the current loop (since the area of theloop is minimised).

4.2 Crosstalk Issues 115

Load

Load

Drivinggate

Drivinggate

Currentflow

Currentflow

Low frequency current flow

High frequency current flow

Figure 4.2: Approximate current flows with low and high frequency spectralcontent.


An approximate relation for the return current density at a point D cm awayfrom a signal trace is:

i(D) =[

I0

πH

] [1

1 + (D/H)2

](4.12)

where:

where I0 total signal current, Amp

H height of the trace above the circuit board, cm

D perpendicular distance from signal trace

i(D) signal current density, A/cm (4.13)

Figure 4.3 shows the form of the distribution of the current under a trace.One may initially think that all the current would bunch up as tightly as possibleunder the trace. However the distribution of the current indicated in (4.12) isactually a balance of two opposing forces. If the current is bunched under theconductor then the inductance would increase as a thin wire carrying the samecurrent has a higher inductance than a fat wire. Therefore, this would meanthat the current would tend to widen. Opposing this is as the current widensacross the ground plane the effective loop area starts to increase, and this tendsto raise the inductance. Therefore this tends to bunch the current. The balanceof these two effects leads to (4.12).

W

H

D

1

12

FH

IK

D

H

Current density at isproportional to:

D

Ground plane

Trace

Figure 4.3: Distribution of current in the ground plane when the currents havehigh frequency components.

4.2.1.1 Crosstalk in Ground Planes

As noted in previous chapters the crosstalk between two conductors dependson their mutual capacitance and inductance. In digital circuits the mutualinductance is usually the larger of the two coupling mechanisms, therefore weshall concentrate on this for the rest of this discussion.

Figure 4.4 shows two traces above a ground planed PCB, and the resultantcurrent distribution under the current carrying trace. The theory behind mutualinductance between the conductors was considered in Section 2.5.4. The equa-tion (2.38) was also postulated for the mutual inductance between two wires.


W

H

D

1

12

FH

IK

D

H

Current density at isproportional to:

D

Ground plane

Trace

Figure 4.4: Two traces above a ground plane and the resultant current distri-bution.

Notice the similarity between this expression and the current density expression(4.12).

Because the returning current density and its associated local magnetic fieldstrength drop off according to (4.12) then we may suspect that the cross-couplingwill also drop off as:

Crosstalk =K

1 + (D/H)2(4.14)

where K is related to the circuit rise time and the length of the interferingtraces.

This relationship can be verified experimentally. The main intuitive resultis that for a fixed trace spacing the cross-coupling falls off with a 1/(1/H2)relationship (remember that the current density has a constant in front of itwith a 1/(1/H2) variable). Therefore it is important that the traces are keptclose to the ground plane. The other important factor is the separation of thetraces. The cross-coupling falls with a 1/D2 relationship. Therefore it onewishes to minimise the coupling then kept the traces a long way apart. Clearly,overall it is the D/H relationship that is the important factor.

4.2.1.2 Crosstalk in Slotted Ground Planes

Slots appearing in the ground plane is a classic layout mistake. These slotsusually occur when a layout person runs out of room on the regular routinglayers and decides to cram in a trace on the ground plane layer. This is achievedby cutting a long slot in the ground plane and laying the trace in the slot. Theeffect of this practice can be seen in Figure 4.5. The return currents have totraverse around the slot thereby dramatically increasing the inductance of thetraces that are generating the return current, and thereby slowing down thesignal rise times. In addition an appreciable amount of current is flowing underan adjacent trace increasing the mutual inductance between the traces.

Slotted ground planes can also occur unintentionally when putting connec-tors onto a PCB. Consider Figure 4.6 which shows the holes for a multi-pinconnector. If the clear-out holes for the connectors pins are made too big thenit is possible to form a virtual slot in the ground plane. One should alwaysensure that there is a path through a connector pin field.


Slot in theground plane

A B

C D

Return currentsfor AB trace

Returncurrent forCD trace

Figure 4.5: Current paths with a slot cut in the ground plane of a PCB.

Cut-out holes for connectoris too big. Reduced cut-out holes

allow current flow throughthe connector area.

Current has to flowaround the connector area.

Figure 4.6: Current flow through connect hole grids.


Remark 4.4 It should be noted that the width of the slot in the ground planedoes not matter. It is the length of the slot perpendicular to the traces that countsas this determines the degree to which the current must divert to go around theslot.

As a trace progressively gets closer to the end of a slot then the extra induc-tance decreases linearly with distance from the slot end. If a trace is close to aslot but does not run over the slot then the slot presence has virtually no effect.

Remark 4.5 One can write down approximate expressions for the inductanceadded by slots. These will not be presented because one should not have slots inthe ground plane at all.

4.2.1.3 Crosstalk in Two Layer PCBs

Sometimes for cost or manufacturing reasons one may wish to use a two layerboard therefore it is relevant to consider how one may lay out the power andground planes on such a board. The technique shown in Figure 4.7 achieves atwo layer power grid system at the expense of more mutual inductance betweentraces, and generally higher trace inductances. It will work alright for lowerspeed designs such as low speed CMOS or LS-TTL designs, but it is unsuit-able for high speed designs – there is no substitute for ground planes for thesesystems.

The important point to note from Figure 4.7 is that the return currenttakes the least inductive return path from the load to the source. This ofteninvolves the current flowing through the positive power plane via the couplingcapacitors. As can be seen from the figure the current will often traverse anumber of capacitors on the way from the load to the source, therefore it isimportant that very low inductance and low impedance capacitors are used.The presence of the capacitors effectively make the power/ground grid a crosshatched ground system.

The inductance of a single trace running across a cross hatched power/groundgrid layout is approximately:

L ≈ 2Y ln(

X

W

)(4.15)

where:

where L inductance, nH

X hatch width, cm

W trace width, cm

Y trace length, cm

Remark 4.6 If two traces run between the same two cross-hatched membersthen the currents for both the traces will take the same path. The mutual induc-tance between the two traces will be L under this situation.

If a second trace is offset by a good distance D, its mutual inductance withthe first trace decreases with a denominator similar to that in (4.12), but withthe cross hatch dimension replacing the term H:

LM ≈ 2Y ln(X/Y )1 + (D/X)2

(4.16)


The ground tracksgo under the positivesupply tracks.

+5VGND

X

XY Trace width W

Current takes the lowest inductancepath back to the source. Notice that thecurrent travels along both the groundand power rails, transferring betweenthen via the capacitors.

Figure 4.7: Layout of a two layer power plane.


4.2.1.4 Crosstalk in with Power and Ground Finger PCBs

An alternative to the power and ground grid design is a layout using the powerand ground fingers. The basic layout of this is shown in Figure 4.8.

GND +5V

Direct signalpath

Return current flowsaround the periphery ofthe board.

Figure 4.8: Layout of a finger power and ground plane system.

This type of layout for two sided boards was prevalent in the early days ofcomputing (e.g. the PDP-8 computer used this, as well as most of the wire wrapboards available 15 years ago). However, this type of layout is not really usablein modern equipment due to the large inductances of the traces and degree ofcrosstalk. The reason for this can be seen in Figure 4.8 – the return currentshave to flow around the periphery of the board. Therefore the loop area of thecurrent from the source driver to the source current return point is potentiallyvery large. This same effect means that there are magnetic fields everywherewith this design, and such boards would not satisfy modern electro-magneticemission standards. This effect also means that the cross coupling betweentraces will be very high.


The approximate loop inductance on a power and ground finger board is:

L ≈ 2Y ln(

X

Y

)(4.17)

where:

where L inductance, nH

X board width, cm

W trace width, cm

Y trace length, cm

Notice that making the trace width twice as large will have little effect on theinductance.

Remark 4.7 One can probably get a board going using old logic families usingthis type of board design, but one would have little hope of getting modern logicto work with it.

4.2.1.5 A Note on Guard Traces

A technique used in analogue design to prevent coupling between signals is toplace what is known as a guard trace between the lines that one wishes tominimise the coupling between.

Figure 4.9 shows the basic configuration of a guard trace. The basic principleis Lenz’s Law. There is a coupling between the signal line an the guard trace.This induces a current in the guard trace that will oppose the field that is causingthe current. Therefore the mutual field will tend to be cancelled. This lessensthe field linking the second signal trace and therefore the mutual inductance isless.

A guard trace is effective at reducing coupling. However, in a digital systemwhere reasonable levels of crosstalk are acceptable, and where all the signaltraces have similar current levels flowing through them, the separation requiredto put in the guard trace gives enough isolation (remember that crosstalk<1/(1 + (D/H)2)), therefore it is to a large degree pointless putting it in. In thecase of analogue circuits very high noise immunity is required, and one can havehigh current conductors near very sensitive circuits. Under these conditionsguard traces are very helpful.

4.2.1.6 Distributed Cross Coupling

The discussion thus far has concentrated on arguments using lumped circuittheory. In many situations this reasoning gives reasonable results, but in the caseof long lines (relative to the switching edges) one must consider the distributednature of the lines.

Figure 4.10 shows a circuit approximation of couples distributed transmissionlines sitting on a ground plane.

What should happen with these lines? The mutual inductive coupling shouldresult in voltages appearing across the inductive elements in line 2 (the line with-out the source). These voltages appear progressively down the line with respect


Guardtrace

Signal trace 1

Signal trace 2

Figure 4.9: Guard trace configuration.

LM

LM

LM

LM

CM

CM

CM

Driving signal

Positive polaritynegative wavefrom transformerk

Negative polaritypositive wavefrom transformerk

A B

C D

k

Figure 4.10: Model for the coupling of a distributed transmission line.


to time as the initial voltage step propagates down the line. Consequently twowaves are injected into the line at each of the mutual inductances, one travel-ling in a positive direction down the line, and the other travelling in a negativedirection down the line. The positive travelling wave (which is actually of neg-ative polarity) is reinforced at every successive tap point since it travels in thesame direction and at the same velocity as the instigating wave. On the otherhand the negative direction travelling wave (which is of positive polarity) is notreinforced since it travels in the opposite direction to the instigating waveform.A new negative travelling wave occurs progressively at each of the taps downthe transmission line. Therefore we end up with a set of waves which arrive atthe source end termination in line 2 in succession, resulting in a long low pulsehere. At the load end termination of line 2 the positive travelling pulses allarrive simultaneously resulting in a single larger pulse.

Note that the simulation is only a discrete model of an completely distributedsystem, therefore the real line would look slightly different.

Remark 4.8 The positive direction travelling pulse is negative because of theassumed polarity of the mutual coupling. We are assuming that the left handside of the line 2 inductors are positive.

Remark 4.9 Because line 1 is correctly terminated the mutual inductance haslittle effect on its performance. The coupling back from line 2 to line 1 due tothe currents and voltage induced in line 2 is small due to the small currents andvoltages present in line 2 relative to those in line 1.

Figure 4.11 shows the effects of mutual inductance only on a transmissionline. The pulse has a rise time of 210psec, the line length is 11cm, and the lineparameters are L0 = 4.5nH/cm and C0 = 1.1pF/cm (i.e. Z0 ≈ 64Ω).

Similarly to the previous section we assume that there is a capacitor con-nected between the various tap points of the transmission lines.

The main difference between the capacitive coupling case and the inductivecase is that both the positive and negative travelling waves created at each tapare of positive polarity. Apart form this the explanation of the waveforms isidentical to the inductive case, and for the sake of brevity will not be repeatedhere. The waveform for the 210psec rise time case is shown in Figure 4.12.

If both capacitive and inductive coupling are present then clearly on getsthe combined effect of both. The load end effects of the mutual and capacitivecoupling will cancel each other to some degree (since they are of opposite polar-ity). At the source end of line 2 the two effects will reinforce making this pulselarger than in only one of the effects is present. These statements are backedup by comparing Figure 4.11 and Figure 4.13.

The source end reflection can often become a far end problem because thesource end pulse is reflected at the source.


Mutual inductance 0.5nH, load terminated, Tr=210psec

t(s)

0.0 500p 1n 1.5n 2n 2.5n 3n

(V

)

−0.2

0.0

0.2

(V

)

0.0

2.0

4.0

(V

)

−0.4

−0.2

0.0

0.2

(V

)

0.0

2.0

4.0

(V

)

−0.2

0.0

0.2

(V) : t(s)

L2.SRC

(V) : t(s)

v(v_pulse.v_pulse1)

(V) : t(s)

L2.END

(V) : t(s)

L1.END

(V) : t(s)

l2.p5

Figure 4.11: Mutual inductively coupled transmission lines with Tr = 210psec


Cap coupling− Tr=210psec

(V

)

−0.2

0.0

0.2

0.4

t(s)

0.0 1n 2n 3n 4n 5n 6n

(V

)

−0.1

0.0

0.1

(V

)

0.0

1.0

2.0

3.0

(V

)

−0.1

0.0

0.1

0.2

(V) : t(s)

L2.END

(V) : t(s)

L2.SRC

(V) : t(s)

v(v_pulse.v_pulse1)

L1.END

(V) : t(s)

l2.p5

Figure 4.12: Waveforms for capacitively coupled transmission lines and Tr =210psec.


Mutual and cap coupling, Tr = 210psec

(V

)

0.0

2.0

4.0

t(s)

0.0 1n 2n 3n 4n 5n

(V

)

−0.1

0.0

0.1

(V

)

0.0

2.0

4.0

(V

)

−0.2−0.10.00.10.2

(V

)

−0.2

0.0

0.2

(V) : t(s)

v(v_pulse.v_pulse1)

(V) : t(s)

L2.END

(V) : t(s)

L1.END

(V) : t(s)

L2.SRC

(V) : t(s)

l2.p5

Figure 4.13: Mutual coupling waveforms with both inductive and capacitivecoupling and Tr = 210psec.


Part II

Switched Mode PowerSupplies

Chapter 5

Fundamental Topologies

5.1 Introduction

This course part will not attempt to cover every issue related to the design andoperation of switch mode power supplies – there is more than enough work inthis area to fill a whole course by itself. Instead, the material shall seek to em-phasise the main types of switch mode converter structures, their fundamentaloperational principles, the various areas where the different structures are useful,and finally aspects of the design and control of the switch mode converters.

Before looking at the different structures for switch mode converters, weshould firstly define what we mean by switch mode converters.

Definition 5.1 Switch Mode Converters (SMCs) are converters which accepta DC input and generate a DC output. Switched mode converters are usuallyonly operating at powers up to 10’s of kilowatts.

The switched mode converter usually finds application as a power supplyregulator in such items as computers, television sets, stereo systems etc., in factalmost all modern electronic consumer devices use some form of switch modeconverter. One of the other areas of application of switch mode converters areaerospace systems, where weight is a very important consideration.

The switch mode inverter, on the other hand accepts a DC input and gener-ates an AC output. These are treated in their own section of this course, sincethese devices tend to find application in the high power industrial systems area,and are most often used for the control of electrical machines (although theyare not exclusively used for this).

5.2 References

References to switch mode power supplies are often contained in texts on elec-tronics and power electronics. There are some specialised book written on thedesign of switching power supplies. Tutorial references that readers may finduseful are [4, 11–13].

One can find a lot of material in the IEEE Transactions on Industrial Elec-tronics, and the IEEE Transactions on Power Electronics. This information

132 Fundamental Topologies

tends to be of a more detailed nature on specific design issues with converters,or new converter topologies.

5.3 Taxonomy of Switch Mode Converters

There are literally hundreds of different circuit configurations for switch modeconverters. However, one can classify most of the them into two basic categories:

• Step-down or buck converters.buck converters

• Step-up or boost converters.boost converters

Many of the other topologies that are in the literature are combinations of thesetwo basic topologies.

The basic layout of a SMC system is shown in Figure 5.1 below. The inputto the converter is usually the mains. Since this is AC the first step is to convertthis to DC via a rectifier. Notice that one can also feed DC, from a battery,directly in at the output point of the rectifier. The unregulated DC is usuallyfiltered with a capacitor, before feeding the DC-DC converter electronics. Theoutput of this stage then feeds the load.

Uncontrolleddiode rectifier

Battery

ACline voltage

DC(unregulated)

DC(unregulated)

DC(regulated)

LoadDC-DC

converterFilter

capacitor

Desired outputvoltage

(1 or 3phase)

Figure 5.1: Block diagram of the structure of a typical DC-DC converter.

In the following diagrams the switches are assumed to be unidirectional. Thedirection of current flow is indicated by the arrow on the switch.

5.3.1 Step-down or Buck Converters

The step-down or buck converter is distinguished by the fact that the outputvoltage is always less than the input voltage. This means, that regardless of theoutput voltage is al-

ways less than inputvoltage

switching strategy, it is impossible to get the output at a higher voltage thanthe input. The distinguishing circuit feature of the buck converter is that onecannot get any current to flow in the circuit when the power device is turnedon, if the output voltage is greater than or equal to the input voltage.

Figure 5.2 shows a basic circuit for a buck converter. Before analysing thecircuit, let us look at it heuristically to determine its basic operation. Whenthe switch SW closes, current will flow to the resistive load via the inductor

5.3 Taxonomy of Switch Mode Converters 133

L. The capacitor C will charge up during this process. Note that there is atransient involved in the inductor current building up and the voltage beingestablished on the capacitor. When the switch is opened the current throughthe inductor cannot stop instantly (if it does then the voltage across the inductorwill become very large and the circuit will most probably be destroyed). Thediode in the circuit will become forward biased, allowing the current in theinductor to continue flowing in the same direction (towards the load). Duringthis phase of operation the energy that was stored in the field of the inductorduring the switch on time is being transferred to the load. If the switch remainsopen for a long time the inductor current gradually decreases to zero, and atthe same time the current drawn from the capacitor increases. If the switch isclosed before the inductor current decreases to zero, then the current begins toincrease again.

Remark 5.1 Note that the maximum current that can flow through the inductorif the switch is left closed is Vd/RL.

Remark 5.2 If the inductor current goes to zero then the converter is said tobe operating in discontinuous mode. If it does not go to zero, then the converteris operating in continuous current mode. Generally speaking, it is desirableto operate the converter in one mode or the other, without a change of mode.Changes in mode can result in difficulties in controlling the output voltage ofthe converter. A change of mode can occur depending on load changes.

Remark 5.3 If the filter were not present in Figure 5.2 then the output voltagewould exactly mirror the input voltage – i.e. if the switch is opened an closedthen the output would be a square wave voltage. The filter has to be designed sothat the cutoff frequency is significantly below the switching frequency. If this isthe case then the filter will reject most of the AC components present at the vod,so that the output voltage will essentially be a DC value equal to the averagevalue of the voltage vod.

Remark 5.4 One of the distinguishing features of this type of circuit is thatwhen the switch is closed the input is connected to the output, but when the buck converter dis-

tinguishing featuresswitch is open the input is disconnected from the output.Another distinguishing feature of the buck converter is that the inductor is

not placed across the input voltage when the switch is closed. The inductor has avoltage imposed across it that is usually somewhat lower than the input voltage.This means that the inductor does not store all the energy being supplied by theinput.

Remark 5.5 If multiple output voltages are required then the buck converter asdepicted here is not the topology to use. Other converters, such as the forwardconverter, that are related to the buck converter can be used.

Remark 5.6 Since the switch is at the input to the converter, then the in-put current is discontinuous. Therefore the input filter to this circuit is morecomplicated compared to other converter types.

Practical Issue 5.1 Driving the gate of a buck converter can be a problem. Ifwe assume that the switching element is a n-channel MOSFET (as it would be


Load

Low pass filter

Vd

Vo

iL

+ -v

LR

Lv

od C

L

SWid

io

Energy storageinductor

Figure 5.2: A basic buck or step-down converter.

for many designs), then the gate voltage often has to be 5V, and in some cases10V above the supply voltage. This complicates the gate drive, since one has tofabricate the higher voltage using a transformer based gate drive circuit.

5.3.2 Step-up or Boost Converters

As the name implies, the boost or step-up converter has an output voltage thatis always greater than the input voltage. The boost converter also has theoutput voltage that

is always greaterthan the input volt-age

added advantage that the output can isolated from the input (using transformerisolation).

Figure 5.3 shows a conceptual diagram of a non-isolated boost converter.The basic operation mechanism is that when the switch is closed the load isisolated from the input by the diode, and current builds up in the inductor. Thiscurrent build is effectively storing energy in the field of the inductor. When theswitch is opened, the current in the inductor wishes to continue to flow in thesame direction and with the same magnitude. Therefore the diode will turn onand the current will immediately flow into the filter capacitor and any connectedload.

SW

L

+ -

Vd

+

-

Vo

io

vL

C

Energy storage

iL

Figure 5.3: A basic boost or step-up converter.


Remark 5.7 If the voltage on the capacitor is larger than the supply voltage,the inductor will produce what ever voltage is required so that Vd + vL = Vo.This is required in order for the current to continue to flow in the inductor.One can see that because the polarity of vL shown in Figure 5.3 always has toreverse for this situation, then the output voltage must always be greater thanthe input voltage (except under initial start-up conditions).

Remark 5.8 The main feature of the boost converter is that current can flowthrough the switch regardless of the relationship between the input and outputvoltages. This usually occurs because the input to the circuit is disconnectedfrom the output when the switch is closed. It is this feature that one must look boost converter dis-

tinguishing featuresfor when one is trying to ascertain what category a particular topology falls into.When the switch is opened, the input is connected to the output because the diodeswitches on.

Another distinguishing feature is that when the switch is closed the inputvoltage is placed across the inductor (so that it stores all the energy being suppliedby the input), and when the switch is opened the inductor is placed in series withthe load. and this stored energy is transferred to the load.

Remark 5.9 In a boost converter the inductor fulfills an energy storage func-tion, whereas in the buck converter the inductor forms a filtering function.Therefore, one can view the boost converter as not having a filter capacitor.This distinction is not very clear for the non-isolated converter, but when welook at isolated converters in the next chapter we shall see that there is a cleardistinction.

Remark 5.10 There is a maximum power that is practical to build for convert-ers that rely on the energy storage principle. This is especially true for low inputvoltages. As we shall see in the next chapter a related converter is the flybackconverter, which operates using the same principle, and hence suffers from thesame power limitations. In order to cater for high power output with an energystorage converter, one needs to have a very small energy storage inductor (sinceE = 1

2Li2, and therefore the current contributes most significantly to the storedenergy). It turns out that for powers much above 50W when the input voltageis low, the inductance becomes very small and is comparable with the parasiticsof the circuit. Therefore, the circuit becomes very difficult to manufacture.

5.3.3 Buck–Boost Converters

The buck–boost converter seeks to combine the properties of the previous twoconverters. This converter type allows the output to be less than or greater thanthe input voltage. Furthermore, this type of converter also allows a negativepolarity output to be generated.

The most obvious way of generating a buck–boost converter is to cascadethe buck and the boost converter. In practice, however, this is not usually done,since one can obtain the same performance from the system using a single switcharrangement. In this case one must really consider the circuit configuration tobe a new one, and not a combination of the previous two.1

1One must consider the buck-boost converter to be a configuration in its own right, sinceit is very difficult to see the separate buck or boost converters in the single switch circuits.


In order to understand the operation of this circuit let us firstly look at a twoswitch implementation. Figure 5.4 shows the conceptual circuit for this. In thiscircuit both switches are either closed at the same time, or they are open at thesame time. If both the switches are closed, then the circuit takes on the classicboost converter configuration. If the output voltage is higher than the inputvoltage, current can still flow through the inductor. When both the switchesare opened, then the inductor is positioned in the circuit as in the classic buckconverter, and the current built up during the switch closed stage circulates viathe diodes through the output capacitor.

Remark 5.11 The key to the circuit of Figure 5.4 is that the switches effectivelychange the circuit configuration, from a boost circuit during the energy storagephase, to a buck circuit when energy is transferred to the load.

RLC

SW1

SW2

iL

+ -vL

Vo

io

Vd

L

Figure 5.4: Two switch buck–boost converter.

Figure 5.5 shows a simplified circuit for a buck-boost converter circuit usingonly one switch. The crucial change in this circuit is the swap of the inductorand the switch and the reversal of the diode as compared to the boost converterof Figure 5.3. The swapping of the inductor and the switch and reversing thediode means that the full input voltage is applied across the inductor when theswitch is closed (as in the boost converter). This means that the inductor isessentially a energy storage element, as in the boost converter. However, whenthe switch is opened the input is no longer connected to the supply (as is thesituation in the buck converter), and therefore the constraint that the outputmust be larger than the input is removed. The resultant voltage across thecapacitor is simply related to the amount of energy stored in the inductor, andthe current required by the load resistor. If one wishes to increase the outputvoltage then the switch is closed for a longer period of time, and it the voltageis to be decreased then the switch is closed for a shorter period of time.

Remark 5.12 One can see from the above explanation that the operation of thiscircuit has characteristics of both the buck and the boost converter. Reiterating,the energy storage in the inductor is from the boost converter (when the switchis closed), and the disconnection of the input from the output when the switchis open is the same as the buck converter.

One can therefore identify a buck–boost topology by looking for the fact thatthe inductor is placed across the supply and disconnected from the load during the


Vd

iL

io

RL

VoCL

+

-

vL

SWid

Figure 5.5: Single switch Buck–boost converter circuit.

energy storage phase when the switch is closed, and the inductor is disconnectedfrom the supply and placed in the output circuit when the switch is opened.

Remark 5.13 One should note that the voltages one can obtain from the buck–boost converter are related to the relationship between the load, the capacitor,and the inductor.

Remark 5.14 The limitations on the performance of the buck-boost converterare very similar to those of the buck and the boost. In addition the presence oftwo diodes in the circulating current path can lead to inefficiency (even whenSchottky diodes are used).

5.3.4 Cuk Converters

This converters peculiar name arises from its inventor (pronounced Ch-ooo-k).It was arrived at by essentially forming a dual of the buck–boost converter.Similarly to the buck–boost converter it is capable of producing voltages thatare larger and smaller than the input voltage, and the output voltage is negativerelative to the same reference as the input voltage. One fundamental differenceis that the primary storage element is a capacitor, as opposed to the inductorin the buck–boost converter.

Figure 5.6 shows a basic Cuk converter. This circuit is slightly more difficultto understand. Therefore we shall consider two situations: one when the switchis closed, and the other when the switch is open.

Consider Figure 5.7, which shows the situation when the switch is open. Forthe sake of the discussion it shall be assumed that the current in the inductorsis continuous. In this case the capacitor is charged by the current iL1 flowingfrom the input. The current iL2 flowing on the load side of the circuit continuesto deliver energy to the load. Note that both iL1 and iL2 would be decreasingunder this circuit condition.


SW

L1

Vd

L2

RL

C

C1

iL1

iL2v

C1

vL1

+ - +-v

L2

+ -

Vo

io

Figure 5.6: The Cuk converter.

The input current, iL1 , would be decreasing because the capacitor voltage isgreater than the input voltage. This can be deduced from the fact that:

vc1 = Vd + Vo (5.1)

Remark 5.15 Equation (5.1) results from the fact that the average voltageacross the inductors in the circuit must ve zero under steady state conditions –the total volt-seconds change across an inductor must be zero over a completeswitching cycle under steady state conditions.

L1

L2

C RL

vL1

+ - vL2

+-

iL1

iL2

Vo

Diode is short circuit

+ -

vC1

io

Vd

Figure 5.7: Cuk converter with the switch open.

Let us consider the situation when the switch is closed. The circuit under thiscondition is shown in Figure 5.8. Clearly the diode is reverse biased under thiscondition, and the input inductor, L1 is storing energy with the input voltageappearing across it. The current, iL2 is also flowing through the switch. Thiscurrent to will be increasing with the capacitor voltage driving it. Therefore,the energy that has been stored in the capacitor is being transferred to the load.

Remark 5.16 The important point to note about the operation of the Cuk con-verter is that the capacitor C1 is the element that is actually transferring the


L1

L2

RL

vL1

+ - vL2

+-

iL1 i

L2

Vo

Switch is closed circuit

+ -

vC1

io

Vd

C2

C1

Figure 5.8: Cuk converter with the switch closed.

energy to the output (and not the inductor as in the other converters that wehave looked at). The inductors in the circuit are essentially performing a filter-ing function on the input currents.

Remark 5.17 Examination of Figures 5.7 and 5.8 indicate that the switch sim-ply transfers the capacitor from the input where it receives energy from the sup-ply, to across the load where it supplies energy to the load.

Remark 5.18 The capacitor in the Cuk converter has to be able to handle highripple currents.

5.3.5 Full Bridge Converters

This is the most complex of the converters, in terms of the number of semicon-ductor components, that we shall look at. It is also the most versatile, in that itcan find application in everything from SMCs to dc-to-ac drives. We shall onlybe considering the former of these two applications.

Figure 5.9 shows a conceptual diagram of the full bridge converter circuit.Notice that it has a total of eight semiconductors, with four of them beingunidirectional switches. The application of a full bridge circuit depends on thecontrol applied to the bridge. One of the most important properties of the fullbridge is that it operates in all four quadrants of the iovo plane. This means thatthe converter can produce positive and negative output voltage and positive andnegative current. The previous converters could only operate in one quadrant(positive or negative voltage, and only positive current). This fact also meansthat the full bridge converter can accept a dc input and produce an ac output(this mode of operation is known as inversion, and will not be discussed furtherat this stage).

One can see from Figure 5.9 that the switches have diodes in parallel withthem. This acknowledges the fact that the switches shown in the diagram areconsidered to be constructed of a technology that only conducts current in onedirection. It also means that if a switch is closed and the current is in thereverse direction then the current will flow through the diode and not throughthe switch.


DC machine load

La

Ra

ea

+

-

SWA

SWA

SWB

SWB

DA

DA

DB

DB

i0

Leg A Leg B

vAN

vBN

v v vAN BN0

N

Vd

Figure 5.9: Full bridge converter.

There are two main switching strategies that can be adopted using the fullbridge inverter:

• Bipolar switching.

• Unipolar switching.

Bipolar switching is the name given to the switching strategy when the A+and B− are switched together, and the B+ and A− are switched together.Therefore the voltage applied to the load is ±Vd. There are no other voltagesthat can be applied. One can deduce that it the switching is such that 50% ofthe time the A+, B− is in force, and the remainder of the time the B+, A−state in in force, then the average voltage across the load is zero. By varyingthe switching around this the voltage can be varied from zero to Vd (when onlyA+, B− are in force) to −Vd (when only B+, A− are in force).

Remark 5.19 The full bridge converter can only produce output voltages thatare in the range of −Vd ≤ vo ≤ Vd.

Unipolar switching, on the other hand, exploits another degree of freedomavailable in the full bridge to gain a lower current ripple in the output. One canalso switch two devices in different legs but on the same rail. For example, onecould switch the A+, B+ devices. This effectively places zero volts on the load,and allows the current to freewheel through one of the switches and the diodeparallelling the other device. The mode of operation clearly changes the rate ofchange the current as compared to the bipolar switching mode.

5.4 Basic Analysis of Switch Mode Converters 141

5.4 Basic Analysis of Switch Mode Converters

In this section we shall do some basic analysis of the converters mentioned inthe previous section. Before carrying out this analysis we shall firstly define theconcept of duty cycle, also known as mark-space ratio. We shall also introducethe concept behind the development of the switching waveforms.

5.4.1 Duty Cycle

Consider Figure 5.10, which shows a switching waveform. The duty cycle of thiswaveform is defined as:

D =ton

Ts(5.2)

Considering the waveform in Figure 5.10 we can work out the average voltage

tont

off

Ts

Vd

v0V

d

SW

t

v0

V0

R

0

ON OFF

Figure 5.10: Definition of the terms related to duty cycle.


produced:

vave =1Ts

∫ Ts

0

vodt

=1Ts

∫ ton

0

Vddt +∫ Ts

ton

0dt

=ton

TsVd

= DVd (5.3)

From (5.3) one can see that the average voltage is directly proportional tothe duty cycle of the switching.

5.4.2 Basic PWM Generator

In the previous section we defined the concept of a duty cycle. The next questionthat arises is: “how does one generate the switched output in a manner thata desired average output voltage is produced?”. The simplest technique, thatactually arose from the days of complete analogue PWM generators is to usea sawtooth or triangular waveform. This concept is shown schematically inFigure 5.11.

One can see from Figure 5.11 that the slope of the sawtooth is:

m =vst

Ts

Therefore one can say that:

ton =Vcontrol

m(5.4)

=Vcontrol

vstTs (5.5)

One can see from (5.5) that:

D =Vcontrol

vst(5.6)

and hence:vave = DVd =

Vcontrol

vstVd (5.7)

orvave ∝ Vcontrol

where the constant of proportionally is Vd/vst.

Remark 5.20 Note that if Vd = vst then the constant of proportionality is one.Therefore the average output voltage is the same as the control voltage. In mostPWM generators this is not the situation.

The circuitry required to perform the PWM generation using the waveformsof Figure 5.11 is very simple. Figure 5.12 shows a conceptual diagram of therequired circuit.

Remark 5.21 The PWM generator circuit shown in Figure 5.12 is usuallyimplemented using analogue circuitry. This can be done at a very low cost. Itcan also be implemented in a digital system.


tontoff

Ts

ON OFF

Vcontrol

vst

Sawtooth waveform

Vd

Figure 5.11: Waveforms in a sawtooth based PWM modulator.

Amplifier

Comparator

+

-

+

-

Vdesired

V0

vcontrol

Switchcontrol

Sawtoothwaveform

Figure 5.12: Simple PWM generator circuit.


5.4.3 Simplified Analysis of the Buck Converter

In this section we shall carry out a simplified analysis of the characteristics ofthe buck converter. The assumptions used are detailed later. However, oneobservation that can be made about the circuit is that the inductor/capacitorcombination in Figure 5.2 effectively form a low pass filter. This filter filters outthe harmonics in the switching waveform, which is of the form of Figure 5.10.For the filtering action to be effective, the -3db roll-off of the LC circuit has to besubstantially lower than the switching frequency of the inverter (i.e. fs = 1/Ts).This means that the effect of the switching on the output current is largelyeliminated, and the switching current is essentially dc. This fact forms the basisof one of the assumptions made later.

As mentioned Section 5.3.1 the buck converter can operate in continuousconduction mode or discontinuous mode. This term refers to the current in theinductor. In continuous mode, the current in the inductor never goes to zero,whereas in discontinuous mode the current will go to zero at some point in theswitching time Ts. Let us now consider each of these modes separately.

5.4.3.1 Continuous Conduction Mode

We shall assume that the circuit is in steady state for the development of theexpressions. If the circuit is in steady state then we immediately know that thesum of the volt-seconds applied across the inductor when the switch is closedplus the volt-seconds when the switch is open must equal zero.2 The waveformsand circuit configurations for the buck converter are shown in Figure 5.13.

Note 5.1 The following analysis assumes that the capacitor voltage essentiallyremains constant over a complete PWM cycle. This in turn implies that thevalue of the capacitor is large enough that it can absorb the charge supplied fromthe inductor current without significant voltage rise.

Remark 5.22 A consequence of the previous note is that over a complete cycleof the PWM the average current supplied by the inductor must be equal to theaverage current supplied to the load. If this were not the case then the capacitorvoltage would continually rise or fall over time as the circuit operated, therebyviolating the steady state assumption.

Notation 5.1 The capitalised currents and voltages in Figure 5.13 and the fol-lowing analysis refer to the average values of the currents, and not the instan-taneous values.

As stated above the average inductor voltage over the complete PWM in-terval has to be zero for steady state operation. Therefore, by inspection of theinductor voltage plot in Figure 5.13 we can say that the volt-seconds appliedmust be zero.3 Therefore:

(Vd − Vo)ton = Vo(Ts − ton) (5.8)

This expression can be rearranged to give:linear voltage gain2This is true because λ =

∫vdt, and the flux in the inductor must not increase over a

complete period for the circuit to be in steady state.3Note the dc output voltage assumption appears in Figure 5.13 as the constant voltages

over each of the switching intervals.


B

vL

t

t

V Vd o

V0

iL

0

0

IL

iL

vL

vL

iL

ton toff

+ - + -Vo VoC C

L L

ioio

Vd

Vd

Ts

Io

A

Figure 5.13: Currents and circuit configurations for a buck converter.

Vo

Vd=

tonTs

= D (duty cycle) (5.9)

Remark 5.23 Keeping in mind the assumptions in the analysis, this (5.9)means that the output voltage varies linearly with the duty cycle, given a fixedinput voltage.

Remark 5.24 One could also obtain the relationship of (5.9) by averaging thevo voltage shown in Figure 5.10, realising that this voltage waveform is the formof the input waveform. The output is then obtained since the average inputvoltage has to be the same as the average output voltage for steady state toexist in the circuit (else the current through the inductor would be increasing ordecreasing over a number of cycles.)

By using conservation of energy one can also calculate the ratio of the inputand output currents. Assuming that the circuit is essentially lossless, then wecan say:

Pd = Po (5.10)

This can be clearly expanded as:

VdId = VoIo (5.11)

orIo

Id=

Vd

Vo=

1D

(5.12)

Remark 5.25 As can be seen from (5.12) the buck converter acts the same asan electronic transformer when in continuous current mode.


Remark 5.26 Even though the current iL is fairly smooth, the input currentid is jumping from some peak value to zero every time the switch is opened.Depending on the source for the converter, the input may have to be filtered tosmooth out these current fluctuations.

5.4.3.2 Boundary between Continuous and Discontinuous Conduc-tion

In this section we shall establish the condition for the converter to move fromcontinuous to discontinuous conduction.

Discontinuous conduction occurs when the current iL goes to zero at orbefore the end of the control period. Consider the current waveform shownin Figure 5.14. One can formally work out that the average value of such awaveform is 1

2 iLpeak , which is also obvious using geometric arguments based onthe fact that the waveform is made up of triangles. Therefore one can derivethe following expression for the minimum average current that must be flowingin the circuit to sustain continuous conduction:

ILB =12iLpeak =

12L

[(Vd − Vo)ton] =DTs

2L(Vd − Vo) = IoB (5.13)

where ILB is the minimum average inductor current, and IoB the minimumoutput current value (remember the two are the same given the steady stateassumption).

Equation (5.13) can be further manipulated using the expression (5.9) toeliminate V0, and assuming that Vd is constant, giving:current required

for continuousinductor current ILB = IoB =

TsVd

2L(D − D2) (5.14)

On can differentiate (5.14) to find the duty cycle for the maximum ILB forgiven Vd, Ts, D, and L:

dILB

dD=

TsVd

2L(1 − 2D) (5.15)

Clearly from (5.15), the maximum value occurs at D = 12 Therefore using (5.14)

that value is:ILBmax =

TsVd

8L(5.16)

Remark 5.27 Equation (5.14) defines the value of the average current requiredin the inductor to just allow continuous conduction. Therefore, the maximumvalue for this average current, which is the value defined in (5.16) occurs whenthe duty cycle is 1/2. This means that the onset of discontinuous current oper-ation occurs first if the duty cycle is around this value (which implies that theoutput voltage is 1

2Vd), as the load current is decreased (i.e. one increases theload resistance value so that less current can flow).

Remark 5.28 The previous remark implies that one can design the converterso that the minimum load current is larger than ILBmax in order to ensure contin-uous conduction (assuming that continuous conduction is the desired operationmode). Note that one of the main design parameters is the inductance value


ton toff

iL

peak

iL

v V VL d o ( )

Vo

0

Current is zero here

Ts

I ILB oB

t

Figure 5.14: Current waveform at the point of discontinuous current in theinductor.

itself. Another point to note is that the input voltage is a parameter in (5.16),so if this voltage varies over a range then this must be taken into considera-tion. Finally, the load of the system will define the load current required, andvia the other considerations mentioned above it will define the parameters of theconverter.

There are two main cases to investigate in relation to discontinuous current– the constant Vd case and the constant Vo case. Let us now consider each ofthese.

5.4.3.2.1 Discontinuous Current with Constant Vd. In many applica-tions the input voltage remains constant, and only the output voltage is varied.We are interested in what the voltage gain of the inverter is under the conditionof discontinuous current. Note that we found that with continuous current thevoltage gain of the converter was D, and hence it operated linearly. However,as we shall see if the converter operates in discontinuous mode then the volt-age gain of the converter becomes non-linear. The following discussion is withreference to Figure 5.15.

In order to calculate the voltage conversion ratio, we firstly start by using voltage conversionratiothe volt-seconds condition – i.e. the total volt-seconds over a control interval

must be zero for steady state operation:

(Vd − Vo)DTs + (−Vo∆1Ts) = 0 (5.17)

which leads to the following relationship for the voltage ratio:

Vo

Vd=

D

D + ∆1(5.18)

The next relationship to establish is the value of the average current in theinductor under this condition depicted in Figure 5.15. We shall use a technique


1Ts

iL

peak

iL

v V VL d o ( )

Vo

0

Ts

I IL o

t

DTs 2Ts

Current iszero here

Figure 5.15: Current waveform for a buck converter with discontinuous current.

similar to that used for (5.13). We must firstly get an expression for the peakinductor current. It can be seen from Figure 5.15 that iLpeak can be written as:

iLpeak =Vo∆1Ts

L

We are now a position to calculate the average inductor current over a period.This is most easily carried out by calculating the area under the iL current inFigure 5.15 for a complete control cycle and dividing by Ts. Therefore we canwrite:

Io =12 iLpeak(DTs + ∆1Ts)

Ts(5.19)

=12iLpeak(D + ∆1) (5.20)

=12

Vo∆1Ts

L(D + ∆1) (5.21)

Substituting for Vo using (5.18) one can manipulate (5.21) to give:average inductorcurrent discontinu-ous mode Io =

12

TsVd

LD∆1 (5.22)

Clearly this can also be expressed in terms of the minimum load current thatresults in discontinuous conduction using (5.16) to give:

Io = 4ILBmaxD∆1 (5.23)

We can now find an expression for ∆1 in (5.18) by rearranging (5.23) to give:

∆1 =Io

4ILBmaxD(5.24)


Substituting (5.24) into (5.18) and rearranging we get the final expression forthe voltage ratio:

Vo

Vd=

D2

D2 + 14

(Io

ILBmax

) (5.25)

Remark 5.29 The most notable feature of (5.25) is that the voltage ratio isnow non-linear. In other words there is a non-linear gain through the converter. voltage ratio is now

non-linearClearly this complicates the design of the control. Furthermore, the onset of non-linearity with the onset of discontinuous current would make the control evenmore difficult if the converter moved from continuous current to discontinuouscurrent operation.

Figure 5.16 is a plot of (5.25) in the discontinuous region, and (5.9) in thecontinuous region.

Remark 5.30 As noted in the previous remark, the voltage ratio to duty cyclerelationship for discontinuous operation can be seen, from Figure 5.16, to bevery non-linear .

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.2

0.4

0.6

0.8

1 Boundary for onset ofdiscontinuous current

D 10.

D 0 9.

D 0 8.

D 0 7.

D 0 6.

D 0 5.

D 0 4.

D 0 3.

D 0 2.

D 01.

D 0 0.

I

Io

LBmax

V

Vo

d CONTINUOUSCURRENTREGION

DISCONTINUOUSCURRENTREGION

Figure 5.16: Voltage ratio of the buck converter for continuous and discontinuousoperation modes and constant Vd. NB. ILBmax = TsVd

8L


5.4.3.2.2 Discontinuous Current with Constant Vo. In many applica-tions the output voltage should be kept constant whilst the input voltage varies.An example of this type of application is a traditional switch mode power supply(SMPS), where the power supply should keep a constant voltage output despiteconstant voltage

output variations of the mains supply voltage.If one uses (5.14) and the linear voltage ratio (5.9), one can calculate the

value of the current at the edge of continuous current conduction in the inductor.Substituting for Vd in (5.14) one gets:

ILB =TsVo

2L(1 − D) (5.26)

which clearly has a maximum at D = 0, giving:

ILBmax =TsVo

2L(5.27)

Remark 5.31 Note that (5.27) is the expression for ILBmax in terms of Vo

whereas the expression (5.14) is in terms of Vd. In (5.27) the assumption isthat Vo is constant (held there by the control of D), and Vd is totally variable.

Remark 5.32 Operation at D = 0 for a constant finite Vo is a mathematicalartifact, since this would imply that Vd = ∞ (given that D = Vo/Vd).

Using (5.26) and (5.27) we can write:

ILB = (1 − D)ILBmax (5.28)

Using (5.18), (5.21), and (5.27) one can write the following expression (notethat both (5.18) and (5.21) are valid regardless of the constraint on Vd or Vo).Now from (5.18) we have:

Vo =DVd

D + ∆1(5.29)

Substituting into (5.21) one can write:

Io =TsVd

2LD∆1 (5.30)

Using (5.27) we can write:

Ts

2L=

ILBmax

Vo(5.31)

Substituting this into (5.30) we get:

Io =ILBmaxVdD∆1

Vo(5.32)

which can be manipulated to give:

∆1 =Io

ILBmax

Vo

DVd(5.33)

which can be substituted back into (5.18) and manipulated to give:

D =Vo

Vd

(Io

ILBmax

1 − Vo

Vd

) 12

(5.34)


Remark 5.33 As can be seen from (5.34) the relationship between D and Vo/Vd

is again highly non-linear. As in the constant Vd case, the control for constantVo would be much simpler if on maintains operation in the continuous currentmode.

0 0.2 0.4 0.6 0.8 1 1.20

0.2

0.4

0.6

0.8

1

V

Vd

o

125.

V

Vd

o

15.

V

Vd

o

2 0.

V

Vd

o

3 0.

V

Vd

o

4 0.

V

Vd

o

5 0.

DISCONTINUOUSCURRENTREGION

CONTINUOUSCURRENTREGIOND

I

Io

LBmax

Figure 5.17: Characteristics of the buck converter with constant Vo. NB.ILBmax = TsVo

2L .

Remark 5.34 The ILBmax in Figure 5.17 is different from that in Figure 5.16.

Figure 5.17 shows the inter-relationship between the duty cycle, load cur-rent and inverse voltage ratio for the buck converter. The non-linearity in thediscontinuous current region of operation is very evident from the figure.

Remark 5.35 Figures 5.16 and 5.17 are actually equivalent. For example, atD = 0.5 in Figure 5.16 Vo

Vd= 0.5 and Io

ILBmax(D=0.5)= 1. The corresponding

point in Figure 5.17 is Vd

Vo= 2 (i.e. Vo

Vd= 0.5), D = 0.5 and Io

ILBmax(D=0)= 0.5.


The latter can be seen from (5.27) and (5.16) as follows. From (5.16):

ILBmax(D=0.5) =TsVd

8L=

TsVo

D8L(using Vd =

Vo

D) (5.35)

=TsVo

4L(for D = 0.5) (5.36)

=12ILBmax(D=0) (5.37)

Correspondence can be found for all the other points.

5.4.3.3 Output Ripple

In the analysis thus-far we have assumed that the capacitor is large enoughthat the voltage at the output does not change substantially. This was anapproximation that made the analysis simpler, but in reality is not true. Inmany applications that ripple at the output is important – for example, inpower supply applications many circuits cannot tolerate significant ripple.

In order to get a feel for the voltage ripple we shall assume that the currentvoltage rippleis continuous. A further simplification is that the impedance of the capacitor isvery much lower than the load resistance, and therefore we can assume that theac component of the current ripple all flows into the capacitor, and the averagecurrent over a switching interval flows into the resistor. The following analysisis with reference to Figure 5.18.

Remark 5.36 One can immediately see from Figure 5.18 that we are assumingthat the ripple is small enough to be insignificant compared to the voltage acrossthe inductor – hence the inductor voltages are drawn as piecewise constant.

Remark 5.37 One could also carry out a complete circuit analysis for the buckconverter and get very precise voltage ripple waveforms. The equations for thisare straight forward, but just a little messy.

The output voltage ripple expression can be developed using a capacitorcharge approach:

∆Vo =∆Q

C=

1C

(12

∆IL

2Ts

2

)(5.38)

The next step is to get an expression for ∆IL. From the definition of the voltageacross an inductor we can say the following:

∆IL =vL∆t

L(5.39)

Considering the off time, we can carry out the following calculations. If ∆t =toff, and we can write toff = Ts − ton, and ton = DTs (from (5.2)) then we get∆t = toff = (1−D)Ts. Using this expression, and the fact that vL = Vo we canwrite:

∆IL =Vo

L(1 − D)Ts (5.40)


vL

V vd o

vo

Ts

0

IL

2

Ts

2

t

t

iL

I IL o

vo

t

0

0

Q

VoVo

Figure 5.18: Output voltage ripple for a buck converter.


Substituting this expression into (5.38) we can write the following expressionfor the voltage ripple:

∆Vo =Ts

8C

Vo

L(1 − D)Ts (5.41)

∴ ∆Vo

Vo=

18

T 2s (1 − D)

LC(5.42)

This expression can be further manipulated into a form that highlights thefiltering requirements of the LC combination. Realising that:

fc =1

2π√

LC(5.43)

then (5.42) can be written as:

∆Vo

Vo=

π2

2(1 − D)

(fc

fs

)2

(5.44)

where fs = 1/Ts.

Remark 5.38 Equation (5.44) emphasises that fact that making the filter poleof the LC filter circuit much smaller than the frequency of the PWM results ina lower output voltage ripple.

Remark 5.39 Note that (5.44) indicates that the ripple is independent of theaverage inductor current (in continuous conduction mode). Therefore, keepingin mind the assumptions made in the analysis, the load on the inverter doesnot influence the amount of ripple. The most relevant of these assumptions inrelation to this issue is that the capacitor impedance is much lower than that ofthe load.

5.4.3.4 Simulation

One can set up a computer simulation of the buck converter circuit. The partic-ular simulator used for this exercise is the Saber by Analogy. The circuit setup in the simulator is shown in Figure 5.19. The switching device is modelledby a switch which has a very high off resistance, and a very low on resistance.The diodes in the circuit are essentially ideal, in that they have a zero turn onvoltage.

If the load is set at 100Ω, the switching duty cycle to 0.5, and the switchingfrequency to 100kHz, then the plot of Figure 5.20 results. Note that this lowvalue of load resistance ensures that the current is continuous in the inductor.The plots shows the initial startup transient (that was missing from the steadystate analysis that we have carried out above). Once the transient has diedaway then the output voltage settles to the 5 Volt level that is predicted fromthe theory. The inductor current settles to the load current, which is Io =5/100 = 0.05 Amp. Notice that the capacitor current is essentially zero. Ifone magnifies the graph it can be seen that the capacitor is absorbing the accurrents resulting from the high frequency switching.


v_oswitch_output_voltage

v_dc 10

BITSTREAM

prbit_l4

pwld

100e-6

50e-3

40000

sw1_l4

pwld sw1_

l4

100

BITSTREAM

prbit_l4

Figure 5.19: Circuit used in simulation of the buck converter.

(V)

0.0

2.0

4.0

6.0

8.0

10.0

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225

(A)

-0.2

0.0

0.2

0.4

(A)

-0.2

0.0

0.2

(V) : t(s)

v_o

(A) : t(s)

Inductor cur

(A) : t(s)

Capacitor cur

Figure 5.20: Waveforms for a buck converter with D = 0.5, RL = 100, andcontinuous inductor current.


Remark 5.40 One can also simulate the performance of the buck converter ifthere is discontinuous current flow in the inductor. However, the simulationtime required for the system to go into steady state is very long due to a problemwith the initial transient. This phenomena can be seen in Figure 5.21 whichshows the currents for a 50% duty cycle and a load resistance of 40kΩ. Noticethat we get an initial LC transient which leaves the capacitor with a charge ofapproximately 9 Volts (i.e. about twice the applied average voltage of 5 Volt).Once this voltage has appeared on the capacitor it can only dissipate via the loadresistor. Therefore the time for the voltage to decay to the steady state value isof the order of 4 to 5 seconds.

Remark 5.41 The slow transient that is evident in Figure 5.21 would not occurin a practical discontinuous mode buck converter. It occurs in the example casebecause the converter control is open loop. In a practical converter the dutycycle is varied depending on the error between the output voltage and the desiredoutput voltage, so as to force the output voltage to the desired.

(V)

0.0

2.0

4.0

6.0

8.0

10.0

(A)

-0.2

0.0

0.2

(A)

-0.2

0.0

0.2

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225

(0.11243, 167.57u)

(0.11243, 70.099u)

(0.11243, 8.8035)

(V) : t(s)

v_o

(A) : t(s)

Inductor cur

(A) : t(s)

Capacitor cur

Figure 5.21: Initial startup waveforms for a buck converter with D = 0.5,RL = 40kΩ, and discontinuous inductor current.

5.4.4 Simplified Analysis of the Boost Converter

In a manner similar to the analysis of the buck converter we shall also analysethe basic properties of the boost converter. The converter analysed is thatshown in Figure 5.3. As with the buck converter there are two cases to consider– the continuous inductor current case, and the discontinuous inductor currentcase.


5.4.4.1 Continuous Conduction Mode

The following discussion is in relation to Figure 5.22. Using the same approachas with the buck converter, we can say that in steady state that the time integralof the voltage across the inductor over a complete switching period is zero.Therefore, by inspection of Figure 5.22 we can write:

Vdton + (Vd − Vo)toff = 0 (5.45)

Rearranging this gives the voltage ratio of the converter: boost convertervoltage ratio

Vo

Vd=

Ts

toff=

11 − D

(5.46)

Assuming a lossless circuit we can say that Pd = Po, and hence:

VdId = VoIo (5.47)

which can be rearranged to give the current ratio of the converter: boost current ratio

Io

Id= (1 − D) (5.48)

B

vL

t

t

Vd

iL

0

0

IL

iL

vL v

L

iL

ton toff

+ - + -Vo VoC C

L L

ioio

Vd

Vd

Ts

A

V Vd o

Figure 5.22: Currents and circuit configurations for a boost converter.

Remark 5.42 Equation (5.46) indicates that the voltage ratio goes to infinityif D = 1. This arises from the fact that the steady state assumption means via(5.45) that the output voltage becomes increasingly large as D → 1.


Remark 5.43 Equation (5.46) indicates that the voltage ratio is not linear fora boost converter. A plot of the voltage ratio is shown in Figure 5.23. Note thevery large increase in the voltage ratio as D → 1. In reality this increase does notoccur. The analysis that lead to (5.46) involved ideal components. However, ifone includes resistance in the inductors and capacitors, and accounts for the verypoor switch utilisation under large duty cycles, then as D → 1, then Vo/Vd → 0,and not ∞.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

10

20

30

40

50

60

70

80

90

100

D (Duty Cycle)

V

Vo

d

Figure 5.23: Voltage ratio of a boost converter versus duty cycle.

5.4.4.2 Boundary between Continuous and Discontinuous Conduc-tion

The following discussion is with reference to Figure 5.24. This figure shows thecurrent waveform at the edge of continuous conduction. Following an analysistechnique similar to that for the buck converter, we can write that the averagevalue of the inductor current at this boundary is:inductor current

continuous currentboundary ILB =

12iLpeak (5.49)

=12

Vd

Lton (5.50)

=TsVo

2LD(1 − D) (5.51)


Equation (5.51) can be further manipulated by realising that the inductor cur-rent and the input current in this converter are the same (i.e. id = iL). Thereforeusing (5.48) we can say that Io = (1 − D)IL, and hence: output current

continuous currentboundaryIoB =

TsVo

2LD(1 − D)2 (5.52)

ton toff

iL

peak

iL

v VL d

V Vd o

0

Current is zero here

Ts

ILB

t

Figure 5.24: Current waveform on the edge of continuous current.

If we consider that the output voltage of the boost converter is kept constant,then one can differentiate (5.51) and equate to zero to get the value of D = 0.5for the maximum value of inductor current at the edge of continuous conduction.This value of current is: maximum inductor

continuous currentboundary

ILBmax =TsVo

8L(5.53)

Similarly, one can differentiate (5.52) and equate to zero to get the maximumvalue of IoB at D = 1/3. The value of IoB is: maximum output

continuous currentboundaryIoBmax =

227

TsVo

L= 0.074

TsVo

L(5.54)

Both ILB and IoB can be expresses as follows in terms of their maximumvalues:

ILB = 4D(1 − D)ILBmax (5.55)

IoB =274

D(1 − D)2IoBmax (5.56)

If we normalise (5.51) and (5.52) using (5.53) we can get the plot shown inFigure 5.25.


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1

3

D

ILB

IoB

I IoB LBmax max

0 59.

ILBmax

I

ILBmax

Figure 5.25: Plot of the normalised continuous current boundary for the boostconverter (Vo constant).


Remark 5.44 Figure 5.25 can be interpreted in the following way. If the cur-rent in the inductor is less than ILB then the converter will begin to operatewith discontinuous inductor current. This translates to the output current be-ing less than IoB, since the inductor current is not the output current for thistype of converter. Notice that the largest value of the continuous output currentboundary occurs at D = 0.33, which does not correspond to the point where thelargest value of the continuous inductor current boundary occurs. This is due tothe fact that the inductor current does not linearly relate to the output current.

Remark 5.45 Figure indicates that for continuous current flow in the inductor,either keep the inductor current above ILB, or the output current above IoB. Ifthe output is above IoB, then IL is above ILB, and vice-versa.

5.4.4.2.1 Discontinuous Current with Constant Vd. We shall assumethat Vd and D remain constant as the output load varies. Under normal operat-ing conditions there would be a controller that would vary D so as to maintainVo constant despite load variations. However, the above assumptions allow aneasier understanding of the discontinuous current condition.

The following discussion is with reference to Figure 5.26 which shows thecurrent under the discontinuous current condition.

1Ts

iL

peak

iL

v VL d

V Vd o

0

Ts

IL

t

DTs 2Ts

Current iszero here

Figure 5.26: Current waveforms for the boost converter with discontinuous cur-rent.

The integral of the voltage over one control interval must be equal to zero forthe circuit to be in steady state. Therefore we can write the following equation: discontinuous volt-

age ratioVdDTs + (Vd − Vo)∆1Ts = 0 (5.57)

∴ Vo

Vd=

∆1 + D

∆1(5.58)


Again using the fact that the converter is assumed to be lossless, then we cansay Pd = Po, and hence the current ratio under discontinuous operation is: discontinuous cur-

rent ratioIo

Id=

∆1

∆1 + D(5.59)

If we consider Figure 5.26, and using the fact that the current waveform canbe broken down into a number of triangles, we can calculate the average inputcurrent. The peak current is:

iLpeak =VdDTs

L(5.60)

and hence the average input current can be deduced to be:discontinuous aver-age input current

Id =VdDTs

2L(D + ∆1) (5.61)

Using (5.59) one can write the average output current expression as:discontinuous aver-age output current

Io =(

TsVd

2L

)D∆1 (5.62)

We can use (5.58), (5.62) and (5.54) to get an expression for the duty cycle interms of the voltage ratio and the output current. From (5.54) we can write:

Ts

L=

272Vo

IoBmax (5.63)

and from (5.58) one can write:

∆1 =D

Vo

Vd− 1

(5.64)

Substituting both of these into (5.62) and manipulating one can get the expres-sion:discontinuous duty

cycleD =

√427

Vo

Vd

(Vo

Vd− 1

)Io

IoBmax

(5.65)

Using (5.65) we can develop a plot of D versus Io/IoBmax for various Vo/Vd.The normal operating mode would be that Vo is constant, and Vd is varying.The development of this plot is slightly complicated due to the fact that theIo/IoBmax for discontinuous current is a function of the duty cycle. Using (5.56)and (5.65) it is possible to get the following expression for the limit on the dutycycle for discontinuous conduction, for a given value of Vd/Vo:

Dlim =

[2 − 1

1x (1− 1

x )

]±√[

2 − 11x (1− 1

x )

]2− 4

2(5.66)

where x = Vd

Vo. The negative of the two solutions gives a value of D in the valid

range of 0 → 1. This sets the limit on the D values, and therefore a limit onthe Io/IoBmax range via (5.56). The characteristics of the boost converter witha constant Vo are shown in Figure 5.27.

Remark 5.46 One can see from Figure 5.27 that the duty cycle has a highlynon-linear relationship to the output current in the discontinuous region of oper-ation. Once outside this region the duty cycle is constant for a particular voltageratio output.


0 0.2 0.4 0.6 0.8 1 1.20

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

DISCONTINUOUS

CURRENT REGION

CONTINUOUS

CURRENT REGION

I

Io

oBmax

D

V

Vd

o

01.

V

Vd

o

0 25.

V

Vd

o

0 5.

V

Vd

o

0 75.

V

Vd

o

0 9.

Figure 5.27: Duty cycle versus normalised output current for the boost converterwith constant Vo.


5.4.4.3 Simulation

To complete this section on the boost converter we shall construct a simulationof the circuit shown in Figure 5.28. The circuit simulated has the switch outputswitch closed, therefore the load resistance is approximately 100Ω.

The voltage output of the circuit, inductor current, load current, and en-ergy stored in the output capacitor and with a 50% duty cycle is shown inFigure 5.29. Notice that the output voltage is 2Vd, as one would predict from(5.46). After the initial startup transient the energy in the capacitor settlesto a dc value, indicating that the circuit is now in steady state. The inductorcurrent is essentially constant, which means that the current being pulled fromthe supply is very close to constant.

The effect of applying several different duty cycles when there is continuousconduction is shown in Figure 5.30. Again the simulation output conformsalmost exactly to the predicted values of the output using (5.46).

v_o

v_dc 10

BITSTREAM

prbit_l4

100e-6 40000

sw1_

l4

100

BITSTREAM

prbit_l4

50e-3

sw1_

l4

pwld

Figure 5.28: Boost converter simulated using Saber.

5.4.5 A Brief Look at the Buck-Boost Converter

We shall not carry out a complete analysis of the buck-boost converter. We canconsider the buck-boost converter can be considered to be a cascade of a buckconverter and a boost converter. Therefore, assuming that both converters areoperated with the same duty cycle, that the current conduction is continuous,then the output voltage ratio is simply the cascade of the two expressions alreadyderived for the buck and boost converters:buck-boost voltage

ratioVo

Vd=

D

1 − D(5.67)

As with the previous converters, if we use the lossless converter assumptionwe can get the current ratio for the buck-boost converter as:buck-boost current

ratioIo

ID=

1 − D

D(5.68)


(V)

0.0

20.0

40.0

t(s)

0.0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22

(A)

0.0

0.2

0.4

0.6

0.8

(A)

0.0

0.2

0.4

(J)

0.0

0.02

0.04

(V) : t(s)

v_o

(A) : t(s)

(A) : t(s)

(J) : t(s)

Inductor cur

Cap energy

I_o

Figure 5.29: Simulated waveforms for a boost converter with D = 0.5 andcontinuous current.

(V)

0.0

10.0

20.0

30.0

40.0

50.0

60.0

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225

(V) : t(s)

v_o;D=0.5

v_o;D=0.8

v_o;D=0.2

Figure 5.30: Output of a boost converter in continuous current mode withseveral different duty cycles.


Equation (5.67) can easily be shown to hold for the single switch version ofthe converter as in Figure 5.5. The situation with discontinuous current is morecomplex, and cannot be considered to be a cascade of the individual convertersunder this condition.

5.4.6 A Brief Analysis of the Cuk Converter

The following analysis is with reference to Figures 5.6, 5.31, 5.7 and 5.8. Itis assumed in the following analysis that the voltage on the capacitor VC1 isconstant. This implies that the capacitor is fairly large.

vL1

vL2

iL1

iL2

t

t

t

t

0

0

0

0

OFF

ON

ON

OFF

Vd

V V Vd C o

1

V VC o

1

Vo

IL1

IL2

( )1 D Ts DTs

( ) ton ( ) toff

Figure 5.31: Steady state currents and voltages in a Cuk converter.

Under the constant VC1 and steady state operation assumptions, the integralof the voltages across the inductors must be zero. Therefore we can write:

VdDTs + (Vd − VC1)(1 − D)Ts = 0 (5.69)

∴ VC1 =1

1 − DVd (for L1) (5.70)


and

(VC1 − Vo)DTs + (−Vo)(1 − D)Ts = 0 (5.71)

∴ VC1 =1D

Vo (for L2) (5.72)

Using (5.70) and (5.72) we can write: Cuk voltage ratio

Vo

Vd=

D

1 − D(5.73)

As with the previous converter analysis, if we assume that the converter islossless, then we can develop the current ratio: Cuk current ratio

Io

Id=

1 − D

D(5.74)

Remark 5.47 Equations (5.73) and (5.74) are the same as those for the buck-boost converter.

One can calculate the current and voltage ratios using an alternate techniquebased on the charge transferred by the capacitor. This technique is illuminatingin that it emphasises the fact that it is the capacitor that is storing the energythat is being transferred from the source to the load. It shall be assumed thatthe inductors, L1 and L2, are large enough that the ripple in the currents canbe ignored – i.e. iL1 = IL1 and iL2 − IL2 . If the circuit is in steady state thenthe total charge delivered to the capacitor over a complete control interval iszero. This can be expressed mathematically as follows:

IL1(1 − D)Ts − IL2DTs = 0 (5.75)

∴ IL2

IL1

=Io

Id=

1 − D

D(5.76)

Using the lossless argument once again (Po = Pd), then one gets:

Vo

Vd=

D

1 − D(5.77)

5.4.7 Full Bridge dc-dc Converter

We shall now consider the calculation of the output voltage ratio and currentsfor the full bridge dc-dc converter. As was previously noted, this converter iscapable of producing both ac and dc outputs, but in this analysis we shall onlyconsider dc output. The following discussion is with respect to Figure 5.9.

Assuming that the switches are switched in such a way that the current iscontinuous in the load, then the output voltage is only a function of the switchstates. Let us consider Leg A in Figure 5.9. If switch SWA+ is closed and ifio is positive then the current will flow through SWA+. If io is negative thenthe current will flow through DA+. In either case, the Leg A load connection isconnected to the positive rail of the dc supply. Therefore:

vAN = Vd (for SWA+ on and SWA− off) (5.78)


Remark 5.48 The assumption stated above essentially means that one of theswitches in a leg is switched on at a particular instant of time. As we shall seelater, if both switches are open in a leg, then the output voltage is no longer afunction of the switch states, but depends on the direction of the load currentfrom the leg.

The alternative switching position for Leg A is SWA+ off and SWA− on. Inthis case a positive current flows through DA− and a negative current throughSWA−. Hence in both cases the Leg A load connection is connected to the nega-tive of the supply, which is also the reference point for the voltage measurements.Therefore:

vAN = 0 (for SWA− on and SWA+ off) (5.79)

Remark 5.49 Expressions (5.78) and (5.79) indicate that the output voltageis dependent only on the status of the switches, and not on the direction of thecurrent.

Given Remark 5.49 then the output voltage of Leg A averaged over a completeswitching cycle Ts, depends only on the input voltage Vd and the duty ratio ofSWA+. Therefore the average Leg A voltage is:

VAN =Vdton + 0 · toff

Ts= Vd · duty cycle of SWA+ (5.80)

Similar arguments apply to Leg B. Therefore VBN is:

VBN = Vd · duty cycle of SWB+ (5.81)

independent of io.Given VAN and VBN , then we can calculate the output voltage for the con-

verter as follows:Vo = VAN − VBN (5.82)

Equation (5.82) is a general expression for the output voltage.It was mentioned in Section 5.3.5 that there are two main strategies for

arranging the switching in full bridge converters. We shall now investigatethese strategies in detail.

5.4.7.1 Bipolar Switching

This is a switching strategy where the top switch in one leg is closed and thebottom switch in the other leg is closed. Therefore the switches are grouped asdiagonal pairs in Figure 5.9.

In a manner similar to that shown in Section 5.4.2, the PWM for bipolarswitching is implemented conceptually by comparing a reference voltage with atriangular waveform. We can work out the output voltage of the converter withthis type of switching with the aid of Figure 5.32.

In the bipolar converter the basic algorithm is that when the control voltageis greater than vtri then SWA+ and SWB− are turned on. If the control voltageis less than vtri then SWA− and SWB+ are turned on. The logic behind thisswitching algorithm, is that the triangular switching waveform can be consideredto be a scaled version of the integral of the leg waveform with respect to the


vtri

vAN

vBN

v v vo AN BN

Io + ve

Io - ve

t

t

t

t

Vd

Vd

Vd

Vd

Vo

t

t

vcontrol

t1

t1

Ts

Ts / 2

100110 01 10

10 10 1001 01

10 01 10 01 10

Io

Io

$Vtri

SW

SW

A

B

D

D

A

B

SW

SW

A

B

D

D

A

B

SW

SW

A

B

io

io

SW

SW

A

B

D

D

A

B

SW

SW

A

B

SW

SW

A

B

D

D

A

B

A

B

C

D

E

F

Figure 5.32: Waveforms for a full bridge converter with a bipolar switchingstrategy.


voltage reference point. Therefore, for a particular leg voltage one has to simplyfind the scaling factor for the control voltage or the triangular wave.

From Figure 5.32A we can see that:

vtri = Vtri1(Ts

4

) t (5.83)

At the switching time t1 one can see that vtri = vcontrol. Substituting this intothe above expression we can write:

t1 =vcontrol

Vtri

Ts

4(5.84)

Again referring to Figure 5.32A we can see that the total on time for Leg A ofthe inverter is:

ton = 2t1 +12Ts (5.85)

We can now use (5.2) to give the duty cycle for the SWA+ and SWB− switchpair:Leg A duty cycle

D1 =tonTs

=12

(1 +

vcontrol

Vtri

)(5.86)

The duty cycle for the SWB+ − SWA− leg (i.e. leg B) is therefore:Leg B duty cycle

D2 = (1 − D1) (5.87)

Using (5.82) we can write:

Vo = D1Vd − D2Vd = (2D1 − 1)Vd (5.88)

which becomes, substituting (5.86) :full bridge bipolaroutput voltage

Vo =Vd

Vtri

vcontrol = kvcontrol (5.89)

Remark 5.50 Equation 5.89 indicates that the output voltage is linear withrespect to the control voltage. This makes the control of the converter fairlysimple.

Remark 5.51 From Figure 5.32 it can be seen that the voltage across the loadis bipolar in nature, hence the name of this switching strategy. It should also benoted that the fact that the voltage is going from positive to negative will resultin higher ripple in the output current, as compared to any strategy that keepsthe voltage unipolar.

Remark 5.52 From (5.88) it can be seen that as the duty cycle D1 is variedfrom 0 to 1 the output voltage varies from −Vd to Vd. This variation is indepen-dent of the direction of the current, although different switching components areresponsible for the conduction of the current depending on the current direction.This can be seen from Figure 5.32E and F, where the various conduction devicesare shown.


5.4.7.2 Unipolar Switching

An alternative switching strategy to the bipolar strategy is the unipolar strat-egy. This switching strategy takes into account another degree of freedom ascompared to the bipolar strategy. The basic idea of this switching strategy isto keep the voltage across the load unipolar if the desired voltage is unipolar.This is achieved by the voltage switching from Vd to 0.

Examination of Figure 5.9 indicates that there are two basic strategies forobtaining unipolar operation. For example, assuming that the current directionis positive, then one can have switch SWB− switched on, and then open andclose SWA+ depending on the average voltage that one desires. This wouldresult in the voltage across the load going from Vd with SWA+ closed, and 0with SWA+ open (and hence SWA− closed). The other strategy is to switch legB. For example, assuming the same current direction, one could open SWB−(and hence close SWB+), the current then circulating through via SWA+ andDB+.

Both of the above switching strategies are employed in the switching algo-rithm drawn in Figure 5.33. One could use a switching scheme similar to that ofthe bipolar case, where one has a unipolar control voltage. In this case only oneof the two switching patterns could be easily incorporated. This would result ina larger output voltage for unipolar switching as compared to bipolar switching.Both of the switching strategies could be used however, if one has the bipolarcontrol voltage shown in Figure 5.33. The switching times are determined asfollows:

SWA+ closed if: vcontrol > vtri (5.90)

and

SWB+ closed if: − vcontrol > vtri (5.91)i.e. vtri < −vcontrol (5.92)

This switching strategy allows both the positive and negative parts of the trian-gular waveform to be utilised. The net result of switching using this strategy isshown in Figure 5.33C. As compared to the bipolar strategy, or a unipolar strat-egy where only one of the switching options are used, the switching frequencyhas effectively been doubled without actually changing the switching frequencyof the switches themselves.

Remark 5.53 The effective doubling of the switching frequency means that theripple in the current using the unipolar strategy is less than the ripple using thebipolar strategy.

Examination of the waveforms in Figure 5.32B and C and Figure 5.33B andC indicate that the duty cycles are the same for the unipolar case and the bipolarcase (the VAN and VBN waveforms are the same in both cases). Rewriting thesefor convenience: full bridge duty cy-

cleD1 =12

(vcontrol

Vtri

+ 1)

(5.93)

andD2 = 1 − D1 (5.94)

Clearly then in this case the output voltage is exactly the same as that of thebipolar case – i.e.: full bridge unipolar

output voltage


vtri

vAN

vBN

v v vo AN BN

Io + ve

Io - ve

t

t

t

t

Vd

Vd

Vd

Vd

Vo

t

t

vcontrol

t1

t1

Ts

1000

10 10

10

Io

Io

$Vtri

io

io

SW

SW

A

B

A

B

C

D

E

F

vcontrol

t1

t1

t1

1110 0000 10 11

11 10 00 10 11

10 00 10 11 10 00 10 11

D

SW

A

B

21

t 21

t

SW

D

A

B

D

D

A

B

SW

SW

A

B

D

D

A

B

D

SW

A

B

SW

SW

A

B

SW

D

A

B

D

D

A

B

Figure 5.33: Waveforms for a full bridge converter with a unipolar switchingstrategy.


Vo = (2D1 − 1)Vd =Vd

Vtri

vcontrol (5.95)

Remark 5.54 Because of the effectively higher switching frequency of the unipo-lar strategy, it is the preferred method of switching for these types of converters.

5.4.8 Comparison of Basic Converter Topologies

In this section we shall attempt to compare the basic converter topologies in-troduced in this chapter. This comparison is somewhat limited, as there area great many topologies that fall into these general categories of those intro-duced, that in particular applications have advantages over others. Neverthelessthis somewhat theoretical comparison is beneficial in that it highlights some ofthe fundamental structural differences between the converters, and in additionintroduces some of the metrics used for carrying out comparisons.

One of the first points to notice about most of the converter structures thatwe have looked at is that they produce unipolar output voltages. There is oneexception to this – the full bridge converter. In addition to the unipolar opera-tion, all except the full bridge converter can only handle current in one direction;into the load. Therefore the buck, boost, buck-boost and Cuk converters aresaid to operate in one quadrant of the iovo operation plane. The full bridgeconverter on the other hand can operate on all four quadrants of the iovo plane.

5.4.8.1 Switch Utilisation

One of the important metrics of power electronic devices is the switch utilisation.This refers to how well a particular converter topology uses the voltage andcurrent ratings of the semiconductor switches used. If a switch is poorly utilisedthen a larger semiconductor switch must be used for a given power output forthe converter. This corresponds to more expensive switches.

In order to calculate the switch utilisation for the previous converters wefirstly need a few assumptions:

1. The average current is at its rated value of Io. The ripple in the currentcan be ignored.

2. The output voltage is ripple free and is at a constant rated value of Vo.

3. The input voltage is allowed to vary and the duty cycle is varied by acontrol algorithm to keep the output voltage at its fixed rated value.

Given these assumptions the peak switch voltage VT and current IT are calcu-lated. The switch peak power rating is then calculated as PT = VT IT . Theswitch utilisation is then calculated as: switch utilisation

definitionUs =

Po

PT(5.96)

where Po = VoIo.

Remark 5.55 The low ripple assumption used in the following analysis implic-itly allows one to remove the particular value of inductance used in the circuitfrom the switch utilisation expressions – i.e. the expressions are circuit valueindependent. It also serves to simplify the analysis whilst still capturing theessential character of the expressions.


Let us now consider the switch utilisation of the generic converter types thatwe have considered in this chapter.

5.4.8.1.1 Buck Converter The peak voltage across the switch is:

VT = Vd (5.97)

This can be written in terms of the output voltage using (5.9) allowing the peakswitch voltage to be written as:

VT =Vo

D(5.98)

Examination of Figure 5.2 reveals that the peak current through the switch mustbe the same as the average load current, since when the switch is closed the twocurrents have to be the same (via the no inductor current ripple assumption).Therefore:

IT = Io (5.99)Using these two expressions for VT and IT we can write the expression for theswitch rating power:

PT = VT IT =VoIo

D(5.100)

Therefore:buck converterswitch utilisation Us =

Po

PT=

VoIo(VoIo

D

) = D (5.101)

5.4.8.1.2 Boost Converter A similar analysis for the boost converter canalso be carried out. Again the basic equations for the voltage ratio, (5.46), andthe current ratio, (5.48) can be used.

The key to getting the switch utilisation in this case is to realise that theaverage input current id and the inductor current iL are the same. Since we areassuming that the inductor is large enough that there can be little ripple in theinductor current, then the switch current must also equal the inductor current.The same assumption also means that we can replace the instantaneous currentswith their average values (since they will be the same). Therefore id = Id andiL = IL. We can therefore write:

IT = Id (5.102)

Using (5.48) we can relate the Id and Io, therefore we have:

IT = Id =Io

1 − D(5.103)

From Figure 5.3 one can see that the peak voltage across the transistor isthe output voltage – i.e.:

VT = Vo (5.104)allowing the switch peak power to be written as:

PT = VT IT =VoIo

1 − D(5.105)

and the switch utilisation as:boost converterswitch utilisation

Us =Po

PT=

VoIo(VoIo

1−D

) = 1 − D (5.106)


5.4.8.1.3 Buck-Boost Converter The determination of the switch utilisa-tion for the buck-boost converter is a little more complicated than the previouscases. This complication occurs due to the fact that the average current ID isnot the peak current value flowing through the switch device (as was the casein most of the above). This occurs due to the fact that the switch disconnectsthe input from the output.

The waveform for the input current (which is also the switch current in thiscase) is shown in Figure 5.34. Note that the constant value of the current from0 to DTs is due to the large inductance assumption. It can be seen that thataverage input current is:

ID =iDDTs

Ts= iDD (5.107)

and therefore the peak current through the switch is:

iD =ID

D(5.108)

iD

ID

DTs ( )1 D Ts

Inputcurrent

t

Figure 5.34: The input current into a buck-boost converter with a large inputinductance.

Using (5.68) and (5.108) we can write:

IT = iD =(

11 − D

)Io (5.109)

The maximum voltage across the switch (from Figure 5.5) can be seen tobe:

VT = Vd + Vo (5.110)


and using (5.67) we can write:

VT =1 − D

DVo + Vo =

Vo

D(5.111)

Using (5.109) and (5.111) we can now write the peak switch power:

PT = VT IT =1

D(1 − D)VoIo (5.112)

and hence the switch utilisation factor is:buck-boost switchutilisation

Us =Po

PT= D(1 − D) = D − D2 (5.113)

The Cuk converter has the same switch utilisation as the buck-boost con-verter.

5.4.8.1.4 Full Bridge Converter When we consider the switch utilisationfor the full bridge converter we shall look at SWA+ and then divide the resultby four, because there are four switches in this converter. In other words werequire fours times the amount of semiconductor material in this converter, andhence we consider then the peak power is divide across these four devices.

Remark 5.56 The division of the single switch utilisation is a technique forsaying that the converter is using more silicon than other converters. However,it should be noted that each individual switch has to satisfy the peak power priorto being divided by four.

From Figure 5.9 it is obvious that the peak voltage across a switch is:

VT = Vd (5.114)

Similarly it is clear that the peak current is the load current:

IT = Io (5.115)

Therefore the peak switch power is:

PT = VT IT = VdIo (5.116)

We need to get the output power. Since we have expressed the peak switchpower in terms of Vd we need to get the output power in terms of this as well.This can be achieved by using (5.89) in conjunction with (5.86) which allows usto write:

vcontrol = Vtri(2D1 − 1) (5.117)

and hence:Vo = Vd(2D1 − 1) (5.118)

and therefore the output power is:

Po = VoIo = Vd(2D1 − 1)Io (5.119)


Therefore the switch utilisation for SWA+ is:

USWA+ =Po

PT= (2D1 − 1) (5.120)

In order to get the final value we divide then single switch value by four:full bridge switchutilisation

Us = 0.5D1 − 0.25 (5.121)

The best way to get an overall comparison of the switch utilisation for thevarious converters is to plot the switch utilisation versus duty cycle for them.This plot is shown in Figure 5.35.

Remark 5.57 One can see from Figure 5.35 that the buck-boost converter, theCuk and the full bridge converter do not have good switch utilisation as comparedto the buck or the boost converter. Therefore, where possible it is better to usethese converters, since a lower cost switch can be used for a given application.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Boost Buck

Buck-boostand Cuk

Full bridge

P

Po

T

D

Figure 5.35: Plot of switch utilisation for the common converter types.

Remark 5.58 If both higher and lower voltages than the supply are requiredthen one has to use either the buck-boost or the Cuk converters. A significantadvantage of the Cuk converter is that the front end of the converter looks likethat of the conventional boost converter. Therefore it shares the property of thisinverter that the input current is reasonable constant, and hence the filtering ofthe input is significantly simplified as compared to the buck-boost converter where


the input (and output) currents are highly discontinuous. Similarly the outputcurrent of this converter can also be kept almost constant. A disadvantage of theCuk converter is that the capacitor has to have a high ripple current capacity.

Remark 5.59 The full bridge converter should only be used if four quadrantoperation is required.

5.4.9 Synchronous Rectifiers

In a switching power supply is being used in very low voltage applications thedrop of voltage across the rectifier diodes can be significant. This voltage dropobviously results in less efficiency from the converter. In some of the moredemanding applications efficiency takes precedence over other considerations.

One halfway solution to the efficiency problem is to use of Schottky diodesfor the rectifier. These devices have an “on” voltage of approximately 0.2 volt,as compared to the 0.6–0.7 volt of the conventional diode. However, in the verydemanding applications this drop is still too much.

The solution employed is the use of the so-called synchronous rectifier. Thisuses a MOSFET instead of the diode. The reader should be aware that a MOS-FET has a conventional diode intrinsically built into its structure. This is notthe diode that is being used in the synchronous rectifier. The synchronous rec-tifier uses the fact that a MOSFET is a symmetric structure, and consequentlyconducts current from the Drain to the Source and vice-versa. This means thatwhen the internal diode is reverse biased the MOSFET is not turned on (therebyoperating as a reverse biased diode). But when the diode is forward biased theMOSFET is turned “on”. This effectively shorts out the internal diode since the“on” voltage of a MOSFET is significantly lower than the “on” voltage of theinternal diode. This is due to the fact that the MOSFET essentially functionsas a resistance when turned “on” hard, and the “on” state resistance of manymodern MOSFETs is very very low – of the order of 10−3mΩ. This principle isshown in Figure 5.36 which shows a conventional boost converter circuit withand without a diode rectifier.

One feature in Figure 5.36 is the parallel Schottky diode with the MOSFET.This diode is required to carry the current when the bottom MOSFET turns“off”, and the rectifier MOSFET is “off”. This gap is required so that shootthrough from the load cannot occur (and from the supply for the buck con-verter). The body diode of the MOSFET should not be allowed to carry thiscurrent because of the very high reverse recovery time.

Remark 5.60 One other advantage of using synchronous rectifiers is that onecan make sure that there is continuous conduction under all load conditions.This occurs because the current can flow in either direction through the inductorwith a series MOSFET as opposed to a diode.

5.4.10 Resonant and Soft-Switching Converters

These notes will not look at resonant converters in any detail. These types ofconverters are not in the mainstream of converter technology at this time, andin fact some people think that they are a fad [13]. Nevertheless one should knowwhat they are and what are their limitations.


+V +V

(a) (b)

Synchronousrectifier

Figure 5.36: (a) Conventional non-synchronous rectifier based boost converter.(b) Synchronous rectifier based boost converter.

A resonant converter is a converter that intentionally has a resonant LCtank circuit as a fundamental part of its operation. This tank circuit is excitedby the switching of the converter, so that the resonance is maintained duringoperation. There are a variety of different topologies to achieve this operation.

The reason for having this resonance is that if the switching of the mainpower devices occurs at the time when the voltage across, or the current throughthe device is zero. This means that the power dissipated in the device ideallyis zero. Consequently it is possible to increase the switching frequency of theconverter, without incurring excessive losses in the switching devices.

In order to have some idea of the configurations of a resonant convertersconsider Figures 5.37 and 5.38. Figure 5.37 shows a resonant buck converterthat is designed to switch when the current through the switch reaches zero.Figure 5.38 is a resonant buck converter which switches when the voltage iszero across the switch. We shall not look at the details of the operation of these(for details look in [4, 12]), but one can see that both circuits have the extraLC components represented by Cr and Lr. These are the components thatrepresent the resonant circuit that is used to assist the switching of the powerdevices.

Remark 5.61 We shall see that the concepts used in resonant converters areactually very old. These ideas were originally used in forced commutated siliconcontrolled rectifier (SCR) circuits from as far back as the 1960s.

Before considering the pros and cons of resonant converters we need to dis-tinguish between them and the so-called soft switching converters (a name often


+

-

Lr

Cr D Cf

RL

SW

Vd

Lf

Io

Figure 5.37: A zero current switching (ZCS) resonant buck converter.

+

-

Lr

Cr

D Cf

RL

SW

Vd

Lf

Io

Dr

Figure 5.38: A zero voltage switching (ZVS) resonant buck converter.


used in the literature to mean a resonant converter). Soft switched convertersare also known as quasi-resonant converters. A resonant converter is one inwhich the power waveforms (current and voltage) are sinusoidal, and switchingoccurs when the voltage and/or current go through zero. Therefore the switch-ing losses (ideally) should be zero. The quasi-resonant converter on the otherhand is intermediate between the resonant converter and the conventional PWMconverter. The circuit of these converters is so arranged that it creates a tankcircuit for a portion of the switching period so that the switch transitions arenearly lossless.

5.4.10.1 Why One Should Not Use Resonant Converters

Resonant converters have several problems in practice. The first major one isthat the switching frequency is a function of the load. This causes problems in switching frequency

is a function of theload

the design of the EMI filters.A more serious problem is that it is common to use the parasitic capacitances

parasitic capaci-tances

as one of the elements in the resonant tank circuit. This makes is virtuallyimpossible to build units that behave the same on the production line. Theobvious solution to the problem is to parallel the parasitics with a capacitorthat swamps its effects. However, this has the effect of lowering the oscillationfrequency of the tank circuit, which is the whole objective of having the resonantconverter in the first place.

In addition to the above problems, resonant converters still have problemswith large line voltage changes, short-circuited or unloaded outputs, and com-ponent tolerances in general. They also operate mainly at higher peak transistorcurrents for the same output power compared to conventional PWM inverters,and in some configurations at larger voltage stresses.

5.4.10.2 Why One Should Use Quasi-Resonant Converters

Before discussing the benefits of using these converters it may be beneficial toreview the operation of a quasi-resonant converter. Consider Figure 5.39, whichis a conceptual diagram of a quasi-resonant forward converter. Notice that themain difference between this converter and that of Figure 6.1 is the addition ofthe capacitor across the switch.

The presence of the capacitor across the switch forms an LC circuit togetherwith the magnetising inductance of the transformer. When the switch is opened,the voltage across the capacitor is zero. The current through the magnetisinginductance will continue flowing into the capacitor, and a resonant ring begins.This ring will continue until the voltage on the capacitor falls back to the sup-ply voltage. At this point the voltage on the magnetising inductance will bepositive at the dot end of the primary. This will cause the diode rectifier in thesecondary to turn on, and the remainder of the energy stored in the magnetisinginductance is transferred to the load. One can see that the quasi resonant con-verter essentially forms a zero voltage switching (ZVS) device, since the voltage zero voltage switch-

ingacross the capacitor cannot change instantaneously when the switch is opened.One must be sure to choose the LC components so that the LC ring is

complete before the start of the next control interval. However, this is not toolimiting, and there is usually a reasonable range of components that can bechosen.


Vd

VoC

L

vL

+ -

iL

D1

D2

N2

N1 R

L

SW

Switch voltage

CSW

Vd

t

Figure 5.39: A quasi-resonant forward converter.

Another possible problem is the presence of a charged capacitor across theswitching device when it is turned on. However, a few calculations for practicalsituations show that the energy dissipated in a MOSFET switch due to this isvery small.

The major advantage of the quasi-resonant converter is the fact that it es-sentially works the same as the standard hard switched PWM converters, andthe switching rate is determined by the PWM controller chip. Therefore the de-sign of the filtering and EMI circuits is greatly simplified compared to frequencywild converters such as many of the pure resonant designs.

Chapter 6

Switch Mode PowerSupplies

6.1 Introduction

In the previous chapter we looked at some fundamental topologies for switchmode converters. In this chapter we shall build on this basic information byconsidering some topologies that are used for commonly available switch modepower supplies (SMPSs). Towards the end of the chapter we shall consider someaspects of the control of these power supplies.

6.2 Isolated Converter Topologies

The converters presented in the previous chapter were all non-isolated convert-ers. However, in practice isolated converters are very common. This is due tothe fact that these converters do offer electrical isolation, but more importantlythat allow the simple production of a number of voltages that are all electricallyisolated. simple production

of a number ofvoltages

In this section the isolated converters will be related back to the basic topolo-gies of the previous chapter. We do not look at all possible isolated topologies,since there are far too many to do this. Instead we concentrate on the ba-sic types, from which all the others have common features. The fundamentalprinciples of operation are emphasised.

6.2.1 The Forward Converter

Figure 6.1 shows the basic idealised circuit for the forward converter. Theforward converter is derived from the buck converter shown in Figure 5.2. Theconnection between the two converters is not obvious at a first glance. Onemay recall that the main distinguishing feature of the buck converter is thatwhen the switch is closed the input is connected to the output. In the caseof the forward converter this is not literally true due to the isolation of thetransformer. However, when the switch is closed the secondary side of thetransformer is reflected to the primary, so in effect this connection exists.

184 Switch Mode Power Supplies

When the switch in the buck converter is opened then the input is discon-nected from the output. In the forward converter this occurs due to the factthat the voltage across the transformer reverses (because of the trapped flux inthe transformer), and the diode D1 is reversed biased and disconnects the loadfrom the transformer secondary.

Remark 6.1 The above-mentioned trapped flux in the magnetising inductanceof the transformer is a new problem that does not exist in the conventionalbuck converter. If one were to operate the forward converter as described in theparagraph above then the switch would be destroyed by the very high voltagescreated as the flux in the magnetising flux attempts to maintain the currentthrough the open switch.

Vd

VoC

L

vL

+ -

iL

D1

D2

N2

N1 R

L

SW

Figure 6.1: Basic circuit of the forward converter.

Figure 6.2 shows a practical forward converter circuit. In this circuit we in-practical forwardconverter troduce a third winding to transfer the energy trapped in the magnetising in-

ductance back to the supply. This winding plays no part when the switch isturned on, but when the switch is turned off and the voltage across the mag-netising inductance reverses then, due to the turn direction of the third winding,diode D3 turns on and current flows back into the supply. This limits the rateat which the flux collapses in the magnetising inductance, and therefore thevoltage induced by this collapse is controlled.

The operation of the circuit can be better understood by referring to theequivalent circuit in Figure 6.3. This circuit is based on using the concept ofthe ideal transformer that does not require any mmf to operate.1 Ignoring theleakage inductances, the flux is stored in the Lm inductance. When the switchis closed current builds up in this inductance, and at the same time current,i1 flows into the transformer. The voltage v1 appears across the magnetisinginductance, and this is reflected via the transformer voltage ratio to winding 2

1The transformer has a magnetic structure with infinite permeability and consequently thecoupling between the windings is one. This also implies that the primary winding has infiniteinductance.

6.2 Isolated Converter Topologies 185

VoC

L

vL

+ -

iL

D1

D2

N2 R

L

D3

N1

N3

SW

Vd

Figure 6.2: A practical forward converter.

D1

D2

D3

Ll1

Ll2

LiL

C RL Vo

Vd

SW

Lm N1

N2

N3 + -v

L

i1

i2

i3

vsw

im v1

Ideal transformer

Figure 6.3: Equivalent circuit for a practical forward converter.


(the secondary). Similarly the current i1 is reflected as i2 in winding 2 via thetransformer current ratio. This current then feeds the load via the output LCfilter.

When the switch is opened then the current im flowing in the magnetisinginductance cannot stop instantaneously. As can be seen from the equivalentcircuit the current can flow in a loop via the ideal transformer. The dot rela-tionship between the primary and ternary winding means that the voltage Vd

appears across the ternary winding. This voltage is reflected to the primarywinding voltage as v1 = −Vd. This implies that vsw = 2Vd. Therefore, thepresence of the third winding keeps the voltage across the switch to a reason-able and controllable value, and essentially returns the energy trapped in themagnetic field of the magnetising inductance to the supply.

The above discussion omitted the influence of the leakage inductance. Un-fortunately the presence of leakage disrupts the ideal operation. If we againinfluence of leakage

inductance consider Figure 6.3, we can see that the leakage inductance carries im + i1, andtherefore it would store the energy 1

2Ll1(im + i1)2. As with the magnetisingcurrent this stored energy will attempt to maintain the current in the samedirection. Therefore when the switch is opened a large voltage can be producedacross this inductance, which would also result in a high vsw voltage. Even forfairly small values, the voltage produced could result in the destruction of theswitch.

Remark 6.2 In order to minimise the leakage inductance the primary andternary winding are often bifilar wound – i.e. they are both wound on the samearm of the transformer. The secondary may not be wound like this as largevoltage isolation between the primary and secondary is often very important.

Remark 6.3 In order to catch any voltage spikes associated with the leakagesone may need some “snubbers” across the switch.

Remark 6.4 The wire used for the ternary winding can be much smaller gaugethan the secondary winding as it only has to carry the magnetising current ofthe transformer.

Now let us consider the operation of this forward converter in a little moredetail. Assuming for the moment that we are dealing with the ideal forwardconverter as depicted in Figure 6.1, and assuming that the transformer is ideal.If the switch is turned on, then there will be current flowing through the trans-former primary, and hence the secondary. Since the voltage ratio of a trans-former is:

v2

v1=

N2

N1(6.1)

then we can deduce that:

vL =N2

N1Vd − Vo for 0 < t < ton (6.2)

which is a positive value, causing iL to increase in value.When the switch is turned off then the diode D1 is reverse biased, effec-

tively disconnecting the transformer from the remainder of the secondary side


circuit. The trapped energy in the filter inductor causes the diode D2 to turnon, allowing current to circulate. In this case the inductor voltage is:

vL = −Vo for ton < t < Ts (6.3)

which is negative, resulting in a decreasing current in the filter inductor.If one integrates the inductor voltage over one complete period and equate

to zero one gets: forward convertervoltage ratioVo

Vd=

N2

N1D (6.4)

Remark 6.5 One can see from (6.4) that the voltage ratio is the same, inprinciple, as that for the buck converter. However, whilst a buck convertercan only produce voltages less than the input voltage, the forward converter canproduce voltages that are greater than the input voltage with an appropriate turnsratio for the transformer.

As we have previously noted, in a practical forward converter one must ac-count for the energy trapped in the magnetising inductance. Let us now considerhow this requirement alters the operational range of the converter output volt-ages. The following discussion is with reference to Figures 6.3 and 6.4. When

Vd

v1

N

NV

d

1

3

t

t

t

iL

ton toff

Ts

isw

i1 im

i im1

tm

Figure 6.4: Current waveforms for a practical forward converter.

the switch is closed then:

v1 = Vd for 0 < t < ton (6.5)


and the current through the magnetising inductance, im, increases at a linearrate (as can be seen in Figure 6.4). When the switch is opened at time ton, theimton

must instantaneously keep flowing. This is achieved via the primary coilof the ideal transformer.

Note 6.1 The capacity for the magnetising current to flow through the primaryof the ideal transformer is due to a property of transformers. The circuitryconnected to the secondary winding of the transformer is reflected (via a turnsratio relationship) to the primary. Therefore, the current is actually flowing inthe secondary circuit, but reflects in such a way as to create the illusion that it isflowing in the primary. From this point of view Figure 6.3 is a little deceptive.

When the switch is opened, as previously mentioned, the voltage induced inwinding 2 is such that the diode D1 is reversed biased, thereby disconnectingthe secondary circuit. At the same time, diode D3 turns on due to the voltageinduced in winding 3. Therefore this winding effectively becomes the secondaryunder this condition. Under this condition the currents flowing in the circuitsare: i1 = −im, i2 = 0 and i3 becomes (from the normal current ratio for anideal transformer):

i3 =N1

N3im (6.6)

During the time tm, when the i3 current flows, the voltage across the transformerprimary is:

v1 = −N1

N3Vd for ton < t < ton + tm (6.7)

since Vd is the voltage across winding 3.When the transformer demagnetises, then im = 0 and v1 = 0. The time

can be obtained by realising that the time integral of the voltage across themagnetising inductance must be zero over a complete time period (for steadystate operation). Considering Figure 6.4 one can see that:

VdDTs −N1

N3Vdtm = 0 (6.8)

∴ tmTs

=N3

N1D (6.9)

If the transformer has to be totally demagnetised before the start of the nextcontrol interval, then the maximum value of tm/Ts = 1 − D. Therefore themaximum duty cycle, using (6.9) is:Forward converter

maximum duty cy-cle (1 − Dmax) =

N3

N1Dmax (6.10)

∴ Dmax =1

1 + N3N1

(6.11)

Remark 6.6 Equation (6.11) indicates that the maximum duty cycle is 0.5 ifN1 = N3 (a common choice in many designs).

6.2.1.1 Other Forward Converter Topologies

We shall not go into detail into the other forward converter topologies, but shallsimply show the basic design and highlight a few pertinent properties. Only asubset of the available of forward converter topologies will be presented.


6.2.1.1.1 Two Switch Converter This topology is shown in Figure 6.5.In this converter each of the switches are turned on and off simultaneously.Consequently each switch only has to stand a maximum voltage of Vd/2. Oneof the other nice features of the circuit is that the magnetising and leakagecurrents can flow via the diodes to the supply, thereby eliminating the ternarywinding on the transformer, and negating the requirement for snubbing acrossthe switches. A Dmax = 0.5 limitation applies to this converter.

Vd Vo

N2

N1

SW2

SW1

Figure 6.5: Circuit diagram of a two switch forward converter.

6.2.1.1.2 Push-Pull Converter This topology is shown in Figure 6.6. Thesalient feature of this topology is the centre tap transformer used. One of themain limitations of the previous forward converters was that the duty cycle waslimited to a maximum value of 0.5. This limitation occurred due to the needto demagnetise the transformer prior to the start of the next switching cycle.The push-pull form of the forward converter effectively allows one to get a fullduty cycle range, at the cost of a more elaborate transformer and two switchingdevices.

We shall spend a little more time investigating this circuit because a fewimportant concepts can be gleaned from this that are of use in Power Electronicsand circuits in general.

One can see from Figure 6.6 that only one half of the transformer is activeat any one time, since only one of the switches is turned on at any one time.For example, if SW1 is closed then current will flow from the supply via thetop half of the primary through SW1. This will result in a voltage developingacross the top half of the secondary winding consistent with the dot conventionof the windings. The resultant current flows via diode D1 to the load.

If SW2 is closed (then SW1 is open) a similar pattern occurs. In this case thecurrent flows from the source via the bottom half of the primary through SW2.The dot convention with this half of the primary in relation to the secondary


SW1

SW2

N1

N1

N2

N2V

d

Vo

D1

D2

L

RLC

Figure 6.6: Push-pull forward converter.

means that diode D2 is forward biased (and D1 is reverse biased). Thereforeagain current flows to the load. The diode arrangement on the secondary is aconventional full wave rectifier circuit.

As with the previous cases one ends up with magnetic energy trapped in themagnetising inductance of the primary. In this particular case the other halfof the primary winding that is not conducting current when the correspondingswitch is closed corresponds to the ternary winding shown in Figure 6.2. Thetwo halves of the primary essentially form an autotransformer. If we operatethe circuit so that there is a period of operation when both of the switches areoff, then a question that immediately arises is “what happens to the trappedmagnetic energy in the core of the transformer?”. This turns out to not bean easy answer in the sense that the solution takes a deal of insight into howtransformers work.

We shall consider the operation of the circuit if both switches are in theoff state using two approaches – the first is the conventional equivalent circuitapproach, and the second is based on realising that the total mmf in the circuitcannot change instantaneously.

Consider the situation where switch SW1 has been closed and then it hasbeen opened. Switch SW2 is left open. When SW1 was closed then the top halfof the secondary transformer would be positive, and consequently the diode D1

is forward biased. We shall assume that the filter inductor L is large enoughthat the current iL is constant. Hence the current iL flows through D1.

When SW1 is opened then there is flux in the core of the transformer. Thisflux must be maintained by a current. This current is often called the mag-netising current, and it is assumed to flow through a “fictitious” circuit elementcalled the magnetising inductance. This element is usually placed in the primaryside of a transformer.

From Figure 6.7 one can see that the current flowing through SW1 is com-posed of two components – the load current (with the appropriate turns ratio)and the magnetising current. Normally the magnetising current is small com-pared to the load component. We are assuming that the transformer is ideal –


i.e. it does not require any mmf to magnetise it. The magnetising current isflowing through the magnetising inductance to produce the flux that is presentin any “real” transformer.

When SW1 is opened then we have the situation shown in Figure 6.8. Onthe primary side of the transformer there are two main effects to consider.The current shown in Figure 6.7 flowing through the leakage inductance of theprimary (Ll) wishes to continue flowing. Therefore a voltage is developed acrossthe leakage in an effort to achieve this. This voltage appears in conjunction withthe supply voltage across SW1 – this is voltage vLl

+Vd in Figure 6.8. A snubberis often required across the transistors to cope with this voltage spike.

N1

N1

N2

N2

Vo

D1

D2

L

RLC

Vd

im Lm

Ll

SW1

N

Ni iL m

2

1

iL

Ideal transformer

N

NiL

2

1

Diode is opencircuit.

N

NV

d

2

1

Vd

N

NV

d

2

1

Figure 6.7: Currents flowing in the push-pull forward converter with SW1 closed.

The second salient point on the primary side of the circuit is that the currentflowing through the magnetising inductance cannot be changed instantaneously.Therefore a voltage would normally develop across the magnetising inductancein an effort to maintain this current. This voltage has a polarity with thepositive on non-dotted terminal of the top half of the transformer. However,this is coupled by the ideal transformer to the secondary. This would producea positive voltage on the non-dotted terminals of the secondary. Consequentlythe diode D2 would become forward biased. Diode D1 also remains forwardbiased as well, meaning that the (constant) iL current splits between D1 andD2. This then provides a path for the magnetising current to flow. If this circuitwas a normal push-pull inverter circuit then the diode across SW2 would turnon and clamp the voltage across the top half of the winding to Vd. However,the presence of the full wave rectifier circuit on the secondary side of the circuitchanges this “normal” scenario.

One point that is not obvious in Figure 6.8 is why does the current iL splitbetween the two secondary windings? When D2 becomes forward biased whydoesn’t D1 become reverse biased? The answer to these questions is that theconstant load inductor current prevents this from happening. If D1 attempts


N1

N1

N2

N2

Vo

D1

D2

L

RLC

Vd

im Lm

Ll

SW1

iL

Ideal transformer

im

vL

l+

v VL d

l

+

Both diodesshort circuit

iL

i N

NiLm

21

2

i N

NiLm

21

2

Figure 6.8: Currents flowing in the push-pull forward converter with SW1 andSW2 open.

to turn off, then the load current would immediately be diverted into the lowerhalf of the secondary. This would mean that a voltage would be induced inthis part of the winding (since a rate of change of flux in the core would result)such that diode D2 would turn off, and D1 would turn on. Therefore the stablesituation is that shown in Figure 6.8. Note that due to the dots on the secondary,the iL/2 current in each half of the windings would produce fluxes that canceleach other. Therefore the only component of flux producing current is themagnetising component reflected into the secondary which circulates around theloop comprising the two diodes and the transformer secondaries. Another wayof reasoning this is to realise that when SW1 is opened the reflected iL currentmust become zero. Consequently the effective iL current through the secondaryof the transformer must also be zero (else we cannot have zero reflected iL onthe primary side). Given that iL is held constant by the filter inductor, theonly way that this can be achieved is if there is net zero flux produced by thesecondary winding due to iL. This is achieved by D1 and D2 both being on,since this results in flux cancellation in the secondary winding.

There is an alternative way of reasoning the splitting of the inductor currentbetween the two secondary windings. This technique is simple, and can beapplied to very complex coupled winding situations. For the moment considerthe transformer to be ideal – i.e. the magnetising inductance is infinite. WithSW1 closed all the current flowing in the primary is reflected into the secondary.In terms of mmf, an ideal transformer does not require any mmf to set up theflux in the core. Therefore we have:

N1i1 + N2iL = 0 (6.12)

i.e. no net mmf in the transformer.When SW1 opens the net mmf in the core cannot change instantaneously,

as this would imply that there is a change in the flux in the core (which has


to remain at zero because it is an ideal transformer). The current in the loadinductor is constant, therefore this current must split between the two secondarywindings so that the flux produced by one is cancelled by that produced by theother, thereby keeping the flux in the core zero. In terms of mmf, when theswitch is opened i1 = 0, therefore the second term in the mmf expression mustalso be zero. This occurs if the other term is 1

2N2iL + (− 12N2iL), which implies

the above-mentioned splitting of the currents.The overall result of D1 and D2 being on simultaneously is that the secondary

windings are short circuited. This value is mirrored to the primary, and itsvoltage will be zero (if D1 and D2 are ideal).

It can be shown that the voltage ratio [4] for this converter is: push-pull voltageratio

Vo

Vd= 2

N2

N1D (6.13)

where 0 < D < 0.5. Therefore, even though the range of the duty cycle islimited to 0.5, the output voltage can achieve values as if the duty cycle has arange from 0 to 1.

Remark 6.7 One potential problem with the push-pull converter is that theswitches are subject to maximum voltages of 2Vd. For low voltage applicationsthis is of little consequence, but for mains line applications with 240VAC thismeans that the devices will be subject to minimum voltages of 700V. Therefore,1000V MOSFETs are required to ensure that there is sufficient over voltagecapacity.

Remark 6.8 One of the potential problems with the push-pull circuit is thatsmall differences in the timing of the duty cycles of the two switches can lead tooffsets in the flux of the transformer. These timing differences can occur becauseof differences between the turn-on times of the transistors, or differences in thespeeds of the firing circuits. Consider Figure 6.9 which shows a typical BH curvefor a ferro-magnetic material. As the ideal push-pull circuit operates it normallymoves from B1 to B2 via the hysteresis loop shown. If the “on” transistor isdriving the flux density to B2, and its on-time is a little less than the othertransistor, then the flux density may not quite get to B2, but instead only getsto B2a. Therefore, when the other device turns on it will drive the flux densityto a value a little higher than B1, B1a. This process will continue, and themaximum flux density B1a will creep up higher on the BH characteristic. If theprocess continues then the core will saturate at the higher flux densities and themagnetising inductance of the core will become very small and excessive currentswill flow through the transistor that is on when this occurs. This often resultsin transistor failure. Current mode control is often used to fix this problem.MOSFET transistors also help, as they have a positive temperature coefficient,and as they heat up more of the voltage is dropped across the device, therebyrobbing volt seconds from the magnetising inductance. The resistance of theprimary also helps via a similar mechanism.

Practical Issue 6.1 One very nice feature of the push-pull converter is thatboth of the transistors are referenced to the same ground rail. This simplifiesthe drive circuits for transistors as compared to other topologies where one hastransistors floating at different voltage levels.


H

B

B1

B2

Normaloperation

loop

Loop withflux imbalance

B B1 2

B

a2

Ba1

Figure 6.9: Flux imbalance in the push-pull circuit.

6.2.2 The Flyback Converter

The Flyback converter is an isolated converter that is derived from the buck-boost converter described in Section 5.3.3 of the previous chapter. Figure 6.10diagrammatically shows this connection. Recall from Section 5.3.3 that theimportant properties of the buck-boost were that when the switch is closed itperforms similarly to a boost converter, with the input disconnected from theoutput and the current flowing through an inductor storing energy. When theswitch is opened then the energy stored in the inductor is then transferred to thesecondary winding, and in the process of doing this the energy storage inductoreffectively becomes the filter inductor in the load section of the circuit. Thisinductor connects the input to the output when the switch is open.

If we compare the buck-boost shown in Figure 6.10 with the Flyback con-verter, then we can see that the magnetising inductance of the transformercarries out the same function as the storage inductor in the traditional circuit.During the phase when the switch is closed current flows through the magnetis-ing inductance. During the time the output circuit is disconnected from theinput because the diode is reversed biased. When the switch is opened, thecurrent through the magnetising inductance wishes to keep flowing in the samedirection. It therefore produces a positive voltage on the non-dot end of theprimary, resulting in a corresponding positive voltage on the non-dot end of thesecondary. Consequently the diode in the secondary becomes forward biased,and the magnetising current in the primary is reflected (via the turns ratio)in the secondary. This current flows into the output capacitor. In effect themagnetising inductance in the primary has been reflected into the secondary,and it performs the same function as the filter inductor in the classical buckconverter circuit.

Now let us consider the operation of the Flyback converter in more detail.Again we shall assume steady state operation, and the output voltage is consid-


Vd

SW

Vd

N1

N2

Buck-Boost Converter Flyback Converter

Vo

Vo

Figure 6.10: Connection between the Buck-Boost and Flyback converter.

ered constant. We shall look in some detail at the variation of the flux in thecore, since it is the flux that stores the energy that is transferred to the load.

One can calculate the flux in an inductor by using Faraday’s Law:

vL =Ndφ

dt(6.14)

∴ φ(t) =1N

∫ t

0

vL(τ)dτ + φ(0) (6.15)

In the case when the switch is closed, as shown in Figure 6.11, there is a constantvoltage of Vd applied across the magnetising inductance, Lm. The secondary sideof the circuit may as well not be there, since the diode in the secondary effectivelydisconnects the load from the primary. The load current Io is supported bythe capacitor. It is therefore important that the capacitor be large enough tosupport the current and voltage appropriately during the switch “on” period.Equation (6.15) can therefore be written as:

φ(t) = φ(0) +Vd

N1t for 0 < t < ton (6.16)

and clearly the peak flux in the magnetising inductance at the end of the “on”period is: flyback peak flux

φ = φ(0) +Vd

N1ton (6.17)

At the end of the time ton the switch is opened. Because the current flowingin the magnetising inductance cannot change instantaneously, or alternativelythe total mmf in the transformer cannot change instantaneously, then a voltageis induced on the secondary (the polarity determined by the dot convention), insuch a manner as to turn on the diode in the secondary. The circuit configurationthen changes to that shown in Figure 6.12. As can be seen from the figure avoltage of Vo is produced across the secondary so that the diode turns on. Thevoltage N1

N2Vo is produced across the primary, with a polarity that will cause

the magnetising current to decrease. Another way to look at this is to realisethat the secondary circuit is reflected to the primary by the transformer, andtherefore the magnetising current can flow in this reflected circuit.


Diode reverse biased

SW

Lmim v1

Vd

Vo

iD

0

N1

N2

N

Nv

N

NV

d

2

1

12

1

Io

C RL

Figure 6.11: Flyback converter with the switch closed.

Diode forward biased

SW open

Lmim

Vd

Vo

iD

N1

N2 Vo

vN

NVo1

1

2

Io

C RL

Figure 6.12: Flyback converter with the switch open.


During the “off” stage of operation, the flux in the transformer core willdecrease from the peak value calculated in (6.17). Therefore the time evolutionof the flux during this time is again given by applying Faraday’s Law:

φ(t) = φ −N1N2

Vo

N1(t − ton) (6.18)

∴ φ(t) = φ − Vo

N2(t − ton) for ton < t < Ts (6.19)

From (6.19) one can deduce, using (6.19) and (6.17), that the flux at the end ofthe control interval: flyback flux at Ts

φ(Ts) = φ − Vo

N2(Ts − ton) (6.20)

= φ(0) +Vd

N1ton − Vo

N2(Ts − ton) (6.21)

We are again assuming that the system is in steady state, therefore the flux atthe beginning and end of a control interval must be the same. This means that:

φ(Ts) = φ(0) (6.22)

which, using (6.21) allows us the write:

φ(0) +Vd

N1ton − Vo

N2(Ts − ton) = φ(0) (6.23)

∴ Vd

N1ton =

Vo

N2(Ts − ton) (6.24)

Rearranging this, and using (5.2) we can write: flyback voltage ratio

Vo

Vd=

N2

N1

(D

1 − D

)(6.25)

Remark 6.9 The voltage ratio in (6.25) is identical to the voltage ratio calcu-lated for the buck-boost converter, as shown in (5.67).

The currents flowing in the circuit under the switch “on” and “off” conditionsare shown in Figure 6.13

Let us calculate the currents flowing in the Flyback converter. This analysisbasically follows the same procedure as the calculation of the magnetising flux.Assume that the current at the beginning of a control interval has an initialvalue of im(0). Therefore during the ton period the magnetising and switchcurrent is:

im(t) = im(0) +Vd

Lmt for 0 < t < ton (6.26)

As with the flux, the peak magnetising current at the end of the “on” period is: peak magnetisingand switch current

im = im(0) +Vd

Lmton (6.27)

Remark 6.10 Note that im is also the peak current flowing through the switch.


t

t

t

v1

Vd

N

NVo

1

2

tont

off

0

Io

( )0

$

iD

N

Nim

2

1

Ts

Figure 6.13: The voltage, current and flux in the ideal Flyback Converter.


During the “off” period the switch current is obviously zero. During this timethe voltage across the magnetising inductance is of a polarity so that the currentdecreases. The current during this period is:

im(t) = im −N1N2

Vo

Lm(t − ton) (6.28)

The current in the diode during this period is simply a scaled version of theinductor current (by the transformer turns ratio). i.e.: flyback diode cur-

rent

iD(t) =N1

N2im(t) =

N1

N2

[im −

N1N2

Vo

Lm(t − ton)

](6.29)

Using the equations that we have derived it is now possible to get the peakmagnetising current in terms of the load current and voltage and the dutycycle. This is an important equation for this type of converter, since the peakmagnetising current needs to be known so that saturation of the core can beavoided, and the switches can be sized. The first step is to work out the averageexpression for the diode current, which is also equal to the average load current(in steady state).

Taking the average of (6.29) and rearranging we can get the expression forthe peak current in terms of the average load current and the output voltage: peak switch current

im =N2

N1

Io

(1 − D)+

12

Vo

(N1N2

)Lm

(1 − D)Ts (6.30)

The peak voltage across the switch can be seen to be the supply voltage plusthe voltage produced by the transformer:

vsw = Vd +N1

N2Vo (6.31)

which can be written, using (6.25), as:

vsw =Vd

(1 − D)(6.32)

6.2.3 Utilisation of Magnetics

One important factor in the performance of converters is the utilisation of themagnetic material. Converters such as the boost and flyback converter arestoring energy in the magnetic field and then transferring this stored energy tothe load when the switching device is turned off. A converter such as the forwardconverter is transferring energy via direct transformer action – the stored energyis a nuisance in that it has to be transferred somewhere when the power deviceis turned off. Despite this two different modes of operation, both these convertertypes are only magnetising the core in one direction. The full bridge converter,on the other hand, is really a variant of the forward converter, but it is differentin that the core is magnetised on both directions during normal operation.This bidirectional magnetisation has implications on the utilisation of the corematerial.


One of the main motivations for the use of SMPSs is their low weight andvolume. Therefore it is essential that the magnetic material is well utilised toachieve these objectives.

Consider Figure 6.14 which shows a typical BH curve for a magnetic material.The flux density Bm is the maximum flux density that can be achieved whenthe material is saturated. The flux density Br1 is the remnant flux density whenthe core is not being subject to an mmf.

H

B

Bm

Br1

Original magneticmaterial (no air gap)

Magnetic materialwith air gap

Br2

Figure 6.14: Typical BH loop for a magnetic material.

Figure 6.15 shows the excitation waveforms for a forward converter witha feedback winding such that N1 = N3 (Figure 6.15(a)), and a full bridgeconverter (Figure 6.15(b)) with the same primary turns. The voltage v1 is thevoltage across the primary winding. We shall assume that both converters areoperating with D = 0.5. ∆Bmax is the excursion of the flux density from theaverage value of the flux density.

Note 6.2 It should be noted that the use of a full bridge converter in this modeis entirely artifical. Under a duty cycle of 0.5 the average output voltage of thisconverter is zero. The output could be used to drive a transformer connectedto a rectifier to get a different output voltage. If a modulation strategy usingzero voltage application is used then control of the DC output voltage could beobtained.

The reason for the artifical D = 0.5 restriction is that this will force the fluxin the core (under appropriate start up conditions) to be bidirectional.

Remark 6.11 A better converter to use for this example is the push-pull con-verter. This converter can perform all the functions of the full bridge if a DCoutput is required, only involves two switches, and can be made to operate withsymmetric bidirectional flux in the core of the transformer (with modified firingof the switches using a combination of current control and zero voltage applica-tion).

Let us consider the expression for the maximum deviation of the flux densityaway from the average value. We know from Faraday’s Law, (6.14), and the


t

t t

t

1v

1v

B B

( )maxB( )maxB

Tf

s

s

( )1

Tf

s

s

( )1

ton tontoff

toff

Vd

Vd

0

0 0

0

(a) (b)

Vd

Vd

Figure 6.15: Core excitation waveforms. (a) forward converter. (b) full bridgeconverter.


relationship φ = BAc, where Ac the area of the core, that flux density canbe written as:

B =1

N1Ac

∫ ton

0

v1dτ + B(0) (6.33)

We are interested in the total change in B from whatever initial condition thereis. We shall call this ∆B. This allows us to ignore the initial condition B(0)in the following evaluation.2 Assuming that D = 0.5 (which implies that ton =Ts/2), and v = Vd then we can write:

∆B =1

N1Ac

∫ Ts2

0

Vddτ (6.34)

=VdTs

2N1Ac=

Vd

2N1Acfs(6.35)

This value corresponds to the peak value of the flux in Figure 6.15(a). Toevaluate the average value we calculate the area under the ∆B curve and divideby the time (since in Figure 6.15(a) the ∆B waveform is triangular). Thereforeusing (6.35) the expression for ∆Bave is:

∆Bave =

(Vd

2N1Acfs

)Ts

2

Ts(6.36)

=Vd

4N1Acfsfor D = 0.5 (6.37)

We can now find ∆Bmax, the maximum deviation of the flux from the averageflux, by subtracting (6.37) from (6.35) to give:

∆Bmax =Vd

4N1Acfsfor D = 0.5 (6.38)

which is valid for both converters.Maximum flux ex-cursion. A little earlier we mentioned that we had ignored the initial value of the flux

density, but in the footnote we noted that this would be important. Referringto Figure 6.14, one can see that when there is no excitation of the core thatthe remnant flux density is Br. Therefore this point on the BH characteristicis the starting point for any unidirectional flux excursion – i.e it is the initialcondition B(0) in (6.33). Therefore, using the definitions in Figure 6.14 theforward converter flux excursion ∆Bmax becomes:

∆Bmax =12(Bm − Br) (6.39)

i.e. the flux excursion is limited by the remnant flux density in the core. Becausethe flux is starting off with the Br offset, then the flux cannot undergo largeflux excursions.

In the case of the full bridge converter, the flux undergoes symmetric fluxdensity excursions about the zero flux density point in Figure 6.14.3 Therefore

2Note the the initial condition is very important when it comes to evaluating the magneticutilisation, as we shall see.

3This is achieved because of the switch drive circuits are designed to produce these fluxexcursions. Note that it is not intrinsic in the design of these converters that this wouldhappen.


∆Bmax is limited only by the saturation flux of the core – i.e.:

∆Bmax = Bm (6.40)

What are the implications of these differences in the maximum flux densitythat can be achieved with these converters? These can be gleaned by considering(6.38) in the light of the above comments. Rearranging (6.38) we get:

Ac =Vd

4N1(∆B)maxfs(6.41)

We can see from this expression that if ∆Bmax is large then Ac can be smaller.Therefore, given the same applied voltages, duty cycle and switching frequency,and for the same number of turns on the primary, the full bridge converter willhave a significantly smaller core for the magnetics as compared to the forwardconverter.

Remark 6.12 Equation (6.41) assumes that fs is the same and N1 is the sameunder the condition of smaller core cross-sectional area. However, as can be seenfrom (7.23) in the following chapter, reproduced here for convenience:

L =µN2

1 Ac

lc(6.42)

where lc is the magnetic path length of the core, the inductance of the core ismuch less. This should also be obvious from the definition of inductance:

L =λ

i=

N1BAc

i(6.43)

If Ac is smaller, then for the same current i the B will be the same (via AmperesLaw), and therefore λ will be smaller.

Therefore implicit in (6.41) is the fact that the current is allowed to increasewhen we have the smaller core area, since the same voltage is applied by theconverter across the winding for the same time, but the inductance is less.

Remark 6.13 As can be gleened from Remark 6.12 there is a trade-off forthe reduced size magnetics under the condition specified – for the same poweroutput we have a larger magnetising current, therefore higher losses, and largerswitching devices.

Remark 6.14 The fact that one does not have to demagnetise the core in thepush-pull converter means, without considering the maximum flux density issue,one can produce more power from the same magnetic core. The effective maxi-mum duty cycle is 1, whereas for the forward converter it is 0.5 (depending onthe relative turns ratio of the ternary winding).

Remark 6.15 In general a bidirectional flux density change type of converteruses the magnetic material more effectively than a unidirectional flux densityconverter.

Remark 6.16 One can see from (6.39) that the maximum excursion of the fluxin the forward converter is limited by the remnant flux in the core. Therefore


one way to utilise the magnetics better in these types of converters is to reducethe remanence. This can be achieved by putting an air gap in the core. Thisto a large degree linearises the core operation, and also dramatically lowers theremnant flux density. This effect is shown diagrammatically by the dashed BHcharacteristic in Figure 6.14.

Under the condition of identical duty cycle, identical turns in the primarywinding and identical core area (i.e. the magnetising inductance of both coresis the same), then flux in the cores is:

Forward converter:

Bmax = Bave + ∆Bmax + Br (6.44)

Bave =(2∆Bmax)Ts

2Ts(6.45)

∴ Bmax = 2∆Bmax + Br (6.46)

For the push-pull converter, assuming appropriate control (i.e. current con-trol), then:

Bave = 0 (6.47)∴ Bmax = 0 + ∆Bmax = ∆Bmax (6.48)

Therefore the push-pull converter has less than half the peak flux density in thecore. This would means that the core losses in this converter would be lowerthan the the forward converter (see below on core losses).

The other issue that can limit the utilisation of magnetic cores in switchingpower supplies are core losses. The general expression for the core loss per unitvolume or weight is of the form:

Core Loss density = kfas [(∆B)max]

b (6.49)

where the k, a, and b are determined from the particular material.One can see from this expression that the core losses are a complex func-

tion of frequency of switching and the maximum flux density excursion. If, forexample, the switching frequency is increased, then the maximum flux densitybecomes less, with everything else the same. Therefore, depending on the spe-cific values of a and b, the overall losses will be smaller. Also the total corevolume will be smaller, since the maximum flux density is less. On the otherhand, the switching losses in the active devices will increase with increased fre-quency. One can see that the optimisation of the core losses must be carriedout for each specific device.

6.3 Introduction to Control Techniques for Switch-ing Power Supplies

Now that we have looked in detail at several idealised converter topologies suit-able for switching power supplies, we shall now look at overall topological andcontrol issues. Due to the varying background of the students doing this subjectwe shall not delve deeply into the control issues, but instead, an overview of the

6.3 Introduction to Control Techniques for Switching Power Supplies 205

concepts involved will be presented. There are many references on issues relatedto the control of switching supplies, both in books and in several of the IEEETransactions, namely Power Electronics, Industrial Electronics, and IndustryApplications. Some of the books on these issues are [4, 12,13].

Before looking at the control issues, we shall consider some broader topolog-ical and practical issues of switching supplies. Consider Figure 6.16 which is ablock diagram of a typical switching power supply (from [4]).

ErrorAmplifier

PWMController

Base and gatedrive circuitry

RectifierandfilterSwitches

Rectifierandfilter

EMIfilter

Rectifierandfilter

DC

DC

MainsSupply

Vo

Vo -ref

Isolationbarrier

HFSignal

Transformer

HFPower

Transformer

SmallMains

Transformer

DC-DC power convertion

Feedback circuitry

AC

Figure 6.16: Block diagram of a typical switch mode power supply.

As can be seen from Figure 6.16 we have looked at the detail of the dc-dcconversion section of the power supply in the first part of this chapter. The lowerhalf of the diagram is related to sensing of the feedback signals and the controlcircuitry. The important point to note here is that the feedback signals haveto be isolated from the input if we are to have an isolated power supply. Thiscomplicates the design of the supply considerably. The circuit of Figure 6.16is a conceptual diagram of one way of designing the isolated feedback. In thisconfiguration the control circuitry and PWM generation is on the output sideof the isolation. The other alternative is to have this circuity on the supply sideof the isolation, and only the output voltage is feedback in an isolated fashion. feedback isolation

The relative merits of the control circuitry on the supply side and the outputside are not clear cut. Having the control circuitry on the output side (as inFigure 6.16) has the advantage that one is transmitting pulsed signals (basicallyfiring pulses) across the isolation. This would also allow one to use an opto-coupler instead of a signal transformer. On the negative side the base drivecircuitry is a little more complicated.

If the PWM and control circuitry is on the supply side then the base drive


circuitry is usually a little simpler compared to the output side circuitry. On thenegative side, getting the output voltage and/or current in an isolated fashioncan be difficult. One technique is to use a voltage-to-frequency converter onthe output side, and a frequency-to-voltage converter on the supply side. Somepower supplies attempt to use opto-couplers in a linear mode of operation.However, opto-couplers are an inherently non-linear device, and this is difficultto do. To complicate the issue even further they are subject to temperaturevariations.

One rather nice and simple technique of getting isolated feedback variableswith the control on the supply side is the circuit shown in Figure 6.17 which wasproposed in [13]. This circuit uses a small forward converter to transfer the ana-logue voltage value of the output voltage across the isolation barrier. The BJTis connected to the output of the main power converter, and is turned off and onby the pulsating voltage here. This then operates a low power forward converterthat transfers the main converter output voltage via the transformer to mainconverter primary reference. The small transformer would have a turns ratio sothat the output voltage is higher than the main converter output voltage. Bydoing this any voltage drop across the rectifying Schottky diode is insignificant.One crucial aspect of the performance of this circuit is that the duty cycle of themain converter (which is used to control the small feedback forward converter)does not affect the output voltage. This is achieved because the output circuitis a peak detector, and the precise duty cycle does not affect the peak detected.The peak is related to the output voltage of the main converter. The forwardfeedback converter output voltage is then resistive divided to give a voltage thatis appropriate for the error amplifier. It is claimed that this circuit is capableof giving an accuracy of 2% and has a bandwidth that is controlled by the RCtime constant of the capacitor/resistive divider network at the output of thefeedback circuit.

6.3.1 Start-Up

Another interesting practical aspect of a SMPS is how to start it up. Thedilemma takes the form of a chicken or egg argument – one needs power to startthe switching, and one needs switching to get power. The solution to this prob-lem could take the form of that shown in Figure 6.16, where we have a separatepower transformer for the control logic. Power is therefore immediately availablefor the PWM and feedback circuitry when the main power is applied. However,in many situations this would be considered to be an expensive solution.

Another much lower cost solution is to use a control logic power winding, aresistor and a capacitor [13]. This is suitable for converters where the controllogic is referenced to the primary. A circuit for this is shown in Figure 6.18.Initially the transformer section of the circuit is inoperative. When power isapplied to the power supply the unregulated DC supply comes on-line. Conse-quently the electrolytic capacitor in Figure 6.18 will charge up. The zener diodeis to limit the voltage to a value safe for the PWM generator IC. The PWMgenerator now has enough voltage to operate.

Unfortunately many PWM generator ICs only have a small hysteresis bandof operation around the nominal voltage of operation. For example, the UC3825PWM generator IC by Unitrode Semiconductor Products (now owned byTexas Instruments) operates with voltages from 9 Volts to a maximum of


S

P

SR1

R2

Feedback circuitry

Vo

P

vfeedback

P S

Forwardconverter

Main converteroutput

Isolationbarrier

Figure 6.17: Feedback circuit using a small forward converter.

30 Volts. There is a 400mV hysteresis around the 9 Volt minimum voltage.Therefore, once the circuit starts operating (at 9 Volts) then it will continue tooperate until the voltage falls to (9 - 0.4) Volts. This implies that the capacitorvoltage in Figure 6.18 cannot fall by the 0.4 Volt hysteresis value during thetime that the main power circuit starts to supply power to the PWM genera-tor. If the voltage does fall by this amount then the PWM generator will stopworking, and the resistive charging process will cause the cycle to repeat. Thecircuit will therefore operate in a type of limit cycle.

In order to make the onset of limit cycle behaviour less likely during start-up of the power supply, one needs to create a larger hysteresis in the operatingsupply of the PWM IC. The PWM IC is designed limited to a certain hystere-sis, so the increased range must be obtained by circuitry external to the chip.Figure 6.19 shows one way of achieving this [13]. improved power

start-up circuitThis circuit effectively allows the capacitor to charge up to a higher voltagebefore the PWM IC is allowed to operate. The capacitor charges up as describedfor Figure 6.18. When the voltage on the capacitor reaches a value equal tothe value of the breakdown voltage of zener Z2 plus the threshold voltage ofthe MOSFET, then the MOSFET will turn on. This then allows the PNPtransistor to turn on and voltage is applied to the PWM IC, which begins tooperate. The resistor RG feeds back voltage to the gate of the MOSFET so thatit will remain on, even if the voltage across zener Z2 drops below its thresholdvoltage. The feedback will remain active while the voltage on the gate of theMOSFET remains above the threshold voltage.

As a specific example of the operation of this circuit, consider zener Z2 to be


+

Vcc

PWMGeneratorChip

UnregulatedDC supply

Power windingwhen running

Initialchargingresistor

Figure 6.18: Example of a simple bootstrap power circuit for a PWM generatorchip.

12 Volt and the gate threshold of the MOSFET to be 2 Volt. Therefore whenthe voltage on the capacitor reaches approximately 14 Volt, zener both Z2 andthe MOSFET will be on. Consequently the PNP will turn on, and the 14 Volton the capacitor will appear on the Vcc pin of the PWM IC. The capacitorwill then begin to discharge. The PWM IC will continue to operate until thecapacitor voltage falls below its minimum operating voltage, which in the caseof a UC3825 is 9 Volt. Therefore, the circuit has created a voltage hysteresisfor 14 − 9 = 5 Volt.

Remark 6.17 The increased hysteresis created by the circuit shown on Fig-ure 6.19 means that the capacitor can be a smaller size and still be able to keepthe PWM IC running long enough to allow the auxiliary winding to start tosupply the power to the PWM IC.

Remark 6.18 The charging resistor shown in Figures 6.18 and 6.19 is con-stantly connected on the circuit. Therefore, even when the switch mode supplyis running, it will still dissipate power. However, this resistor can be made quitelarge so that the power dissipated can be made small – the charging time of thecapacitor is not that important (within reason). The resistor is no longer reallysupplying the current in the turn on phase, as it was with the previous circuit.Alternatively one can use auxiliary circuitry to switch the resistor out, therebyallowing a smaller resistor to be used.


+

Vcc

PWMGeneratorChip

UnregulatedDC supply

Power windingwhen running

Initialchargingresistor

RG1

RBZ

2Z

1

Hysteresis circuit

RG2

Figure 6.19: Bootstrap circuitry modified for increased hysteresis range.

6.3.2 Protection Issues

6.3.2.1 Soft Start

Soft starting refers to generating voltage output very slowly when power isfirst applied. This is required because when power is first applied the controlcircuitry will apply the maximum duty cycle to the power stage. This can resultin excessive current flow in the components which can be potentially destructive.In order to prevent this a special mode of operation is required so that the dutycycle ramps up from a very small value to the value required by the controlcircuitry. Soft starting is also used to recover a SMPS from fault conditions.

Soft starting is handled internally in most PWM ICs, therefore it does notrequire any specific action by a designer.

6.3.2.2 Voltage Protection

Most SMPS integrated control circuits have a pin which can be connected to anexternal circuit. This circuit will generate a voltage into the pin of the IC whenthe input voltage rises above a certain value. Most ICs also contain circuitrythat detects under voltage conditions. Internally the shutdown circuitry usuallystops the internal latch from functioning and sets the outputs into a non-drivingstate.

A block diagram of the Unitrode 1825 switch mode PWM generator chipis shown in Figure 6.20. Notice that the “Output Inhibit” is activated for low


voltage to the chip itself, as well as from the Ilim/SD input (i.e. pin 9). Thelater is activated by external circuitry to detect over voltage/under voltage tothe power circuit.

3/97

BLOCK DIAGRAM

U DG-92030-2

Figure 6.20: Block diagram of the Unitrode high speed PWM generator.

6.3.2.3 Current Limiting

Current limiting is included in most PWM control ICs to protect the powersupply under short circuit conditions. There are two types of current limiting:

• Constant current limiting.

• Foldback current limiting.

Constant current limiting, as the name implies, is a form of current limitconstant currentlimit where the current can only go to a particular value and then it will not increase

any more, regardless of the load. Therefore, even under short circuit conditionsthe current will not increase appreciably above this limit value. This concept isshown in a V0I0 diagram in Figure 6.21. One point to note about this diagramis that the voltage at the output of the converter can be appreciable under thiscondition, depending on the impedance of the load.

Remark 6.19 The constant current limit may not be satisfactory in many ap-plications, since the limit current may, over time, result in the thermal rating ofthe inductor or transformer windings being exceeded. Therefore, if such a limitis to be used, then one must ensure that the windings and power devices cansupport the limit current indefinitely.

A slightly different limit is the foldback current limit. This limit is motivatedfoldback currentlimit by the desire of reducing the currents flowing in abnormal short circuit or near

short circuit conditions. The operation of this current limit philosophy is shown


Io, rated

Ilimit

Vo1

Vo2

Vo

Io

R RL

1

R RL

2

Load lines

Vo, rated

Figure 6.21: Operation of a constant current limit.

in Figure 6.22. In this case when the current reaches a limit value of Io, limit

then the current limit drops with the output voltage. Therefore under shortcircuit conditions the current is reduced to a much lower value than in theprevious case. The power that is being supplied to the external circuit underthis condition is not nearly as high as in the constant current limit situation.

Remark 6.20 The foldback current limit does not solve the overheating problemmentioned in the previous remark. If the circuit is operating at Io, limit then theproblem is the same as in the constant current limit case.

Vo, rated

Io,limit

Io,rated

Io

Vo

Vo1

Vo2

Io, foldback

R RL

1

R RL

2

Load lines

Figure 6.22: Operation of a foldback current limit.


Most PWM ICs implement a two stage current limit. The current throughthe switch is fed through a sense resistor, and the fed into the current limit pinof the PWM IC. If the voltage on this pin reaches a certain value the switchturn on pulse is turned off until the next control cycle. Therefore the currentlimiting is carried out on a switching interval basis. If the voltage goes higherand reaches a second limit, then the controller stops switching and restarts insoft start mode. The power supply can then oscillate in this mode until theshort or the fault is rectified.

Current limiting is actually a little more complicated than has been madeout so far. Consider the situation when one has a converter with a transformerand multiple output windings. If the current sensing is set up on the primary,then the current limit has to be set for the current pulled under full load fromall the windings. However, if all the secondaries, except one, are unloaded, thenif there is a short on this winding the full current of the inverter can go throughthis winding before there is a trip. This situation could result in the destructionof this winding, or destruction of the rectifier components on this winding.

There is no easy way out of this problem. Probably the most economicalsolution is to sense the current limit of each winding individually, and then takethe output of these limit circuits and “OR” them together. This forms the tripsignal to the PWM chip.

6.3.3 Control Architecture of a Switch Mode Power Sup-ply System

6.3.3.1 Voltage Mode Control

Figure 6.23 shows a conceptual diagram of a SMPS system from a control per-spective (as opposed to an implementation perspective). The compensatingamplifier is shown with generic feedback components Z1 and Z2. These com-ponents can contain reactive circuit elements, which allow a variety of differenttransfer functions to be set up in the feedback loop.

Zi

Zf

Vo,ref

+

- PWMController

Power stageand output

filter

vo

Compensating amplifier

vc d

Vd

Figure 6.23: Conceptual diagram of a control system for a switch mode powersupply.


In general the main objective of the control system of Figure 6.23 is tocontrol the output voltage to be a specific value under varying load conditions.In order to design the feedback compensation, one needs to obtain a model ofthe system suitable for control analysis. This is achieved by using an approachcalled state space averaging. This allows one to obtain a state space model ofthe system, accounting for the switching in the circuit in an average sense [4].We shall not look at the detail of the process. The net result of this modellingprocess is that one can obtain a small signal linearised model of the converterand its control of the form shown in Figure 6.24. This figure shows each ofthe converter components as a transfer function. In this form one can applystandard classical control system design techniques to the system.

PWMcontroller

Power stageand output

filter

Compensatingerror

amplifier

~ ( ),

v so ref +

-

~ ( )v serr~ ( )v sc

~( )d s ~ ( )v so

T sd s

v sm

c

( )

~( )

~ ( ) T s

v s

d sp

c( )~ ( )~( )

T sv s

v sc

c1( )

~ ( )~ ( )

Figure 6.24: Linearised model of a switch mode power supply.

Whilst switching power supplies seem to be very simple circuits, their oper-ation from a control viewpoint is more complex than one might initially expect.Consider, for example, the flyback and boost converter. Because these two con-verters store energy in the magnetic field of an inductor before transferring it tothe load they exhibit an effect caused by having a right half plane zero in theirtransfer function. Such systems are known as non-minimum phase systems. Forthe non-control literate reader, a right half plane pole corresponds to a responsethat tends to go in the wrong direction to correct a disturbance. non-minimum

phaseConsider the following example of a right half plane zero effect. If we have aflyback converter, and there is a sudden decrease in the output voltage due toan increased output load on the converter. The natural reaction of the controlsystem is to increase the duty cycle, D, so that more energy is transferred tothe load to restore the voltage. However, due to the above-mentioned energystorage operation principle of this converter, the initial increase in the dutycycle can result in a further decrease in the output voltage. This is due to thefact that increasing D instantaneously delays the next delivery of energy fromthe magnetic field to the load, as compared to what would have happened ifthere had been no change in D. One can see that if the feedback is very highbandwidth then this will result in a further increase in D, and the process willrepeat. We effectively have positive feedback. Of course the process will stopwhen we get to the limit of the duty cycle (this is a non-linear effect that is notaccounted for in our linear explanation). The presence of a right half plane zero


in these converters limits the control bandwidth of these types of converters.Figure 6.23 shows a basic diagram for a switch mode control system. Many

real systems actually use a hierarchical control system consisting of two nestedcontrol loops. The inner most of the control loops is a current control loop, andthe outer control loop is the traditional voltage control loop. The advantages ofusing the current control loop will be discussed in detail in a following section.Suffice to say that the disturbance rejection properties of the controller areimproved using this structure. A block diagram of this hierarchical controlsystem appears in Figure 6.25. Notice that the voltage vc appears as a currentreference to the section of the circuit that controls the current.

Power stages andoutput filters

H s( )

+

-

Voltage loopfeedback

compensator

G s( )

iL

vo

vo

iL

Comparatorand latch

vo,ref vo,err vc

Switchingsignal

Figure 6.25: Block diagram of a nested loop control system for a switch modepower supply.

6.3.3.2 Voltage Feed-forward PWM Control

All of the diagrams for control of the SMPSs thus-far have relied totally onfeedback control. However, in the case of input voltage fluctuations one can feed-forward the change of input voltage to the controller so that it can be accountedfor before it would affect the output. This is usually achieve in practice byfeeding the input voltage into the PWM IC. This chip usually accounts for thesupply variation by altering the amplitude of the triangular waveform that isused internally to generate the PWM. One can see from (5.7) that if vst isincreased (corresponding to an increase in the peak of the triangular waveform)then the duty cycle decreases. Therefore if this value is controlled by the inputvoltage then it is possible to get near perfect input disturbance rejection.input disturbance

rejection6.3.3.3 Current Mode Control

Current mode control is a term used in the SMPSs literature to refer to a nestedloop control system, such as that depicted in Figure 6.25, where the inner loopcontrols the inductor current, and the outer loop controls the output capacitorvoltage.

There are a number of very good reasons for complicating the control struc-ture of the addition of the current control loop:

• Switch current limiting. It was mentioned in Section 6.2.1.1.2 that one ofthe problems with the push-pull converter was that small differences in the


switching times of the switching devices could cause eventual saturationof the transformer. Employing current mode control the peak switchingcurrents in the two switches of such converters can be balanced so thatthis phenomena does not occur. Note that the current mode control inthis situation would be from each of the two switches.

• Simplified converter dynamics. Current control effectively removes thepole introduced by the output inductor. This simplifies the dynamics ofthe converter system, effectively allowing the bandwidth of the controlloop to be increased (because of the increased gain and phase marginachieved). This is especially useful in converters that have a right halfplane zero in their response.

• Simplified paralleling of converters. The presence of the current controlloop allows the possibility of paralleling of several SMPSs, with each powersupply contributing the same amount of current to the load. This isachieved by feeding each of the supplies with the same control voltage.

• Automatic voltage feed-forward. The desirable properties of voltage feed-forward are implicitly achieved when current mode control. If the inputvoltage increases, the current will reach the current limit sooner. Thereforethe duty cycle will decrease with out the delay of waiting for the voltageto vary at the output.

In a current mode controlled SMPS, as depicted in Figure 6.25, the controlvoltage vc, which is derived from the error between the desired output voltageand the actual output voltage, represents a desired inductor output current, ora switch current. This is achieved in a number of different ways [4]:

1. Tolerance band control.

2. Constant “off” time control.

3. Constant frequency control with turn-on at clock time.

Let us look at how each of these schemes works in a little more detail. In tolerance band con-troltolerance band control the inductor current is kept within a band, and the

control voltage is effectively controlling the average value of the current. Thewidth of the band is a design parameter, and by choosing it the designer isalso influencing the switching frequency of the converter (which is also relatedto other parameters of the converter). Tolerance band control is essentially aclassical hysteresis or bang bang type of control strategy.

The operation of tolerance band control is depicted in Figure 6.26. The ∆iLvalue is one of the design parameters for the controller. If ∆iL is very smallthen, for the same converter parameters, the frequency of switching will be muchlarger. One can also see that if the load current is larger (which correspondsto a larger slope on the current sawtooth) then the frequency will be higher.Therefore the switching frequency is also a function of the load. These propertiesare an undesirable property of this type of controller. Another problem withthe tolerance band controller is that it only really works properly in continuousmode operation. If the current becomes discontinuous, then the desired averageinductor current can become negative. If the current is discontinuous then thelower switch on limit would have to be zero – the circuit has to be designed


t

iL

vc

IL

iL

/ 2

iL

/ 2

Switchturnson

Switchturnsoff

Switchturnson

toff

ton

Figure 6.26: Waveforms for tolerance band current control.

to handle this. If the controller is not specially designed, the controller willrespond to driving the inductor current to zero, and it will then stay there.There is also a problem of very high switching frequencies at low current values,this corresponding to a very small hysteresis band.

Constant “off” time control controls the peak current in the inductor. In thisstrategy the control voltage specifies the maximum or peak current. When thispeak current is reached the switch is opened for a fixed period of time. It is thenclosed again and the process repeats. This situation is depicted in Figure 6.27.This control strategy also suffers from the problem that the switching frequencyis dependent on the load and the converter parameters.constant “off” time

controlconstant frequencywith turn-on clocktime control

The constant-frequency with turn-on at clock time control is the controlstrategy most commonly used. This is due to the fact that the switching fre-quency is user definable in the strategy. One is effectively trading off the ripplecontrol achievable with tolerance band control for the constant switching fre-quency. This allows one to control more accurately the losses in the switchingdevices, and makes the design of the output filter much simpler. Figure 6.28shows the waveforms that occur with this control. The switch is closed at atime determined by a clock signal. The switch remains on until the currentlimit is reached, and then it turns off until the beginning of the next controlperiod. The process then repeats. The fact that the switch only turns on at thebeginning of a clock pulse means that the frequency is fixed by the clock period(which of course is user definable).

There is a problem with straight current mode control that we have notmentioned in the discussion thus-far. If the converter duty cycle exceeds 50%the converter output will possibly oscillate at a subharmonic of the switchingfrequency – specifically at half the switching frequency. This occurs becausesubharmonicsthe current control loop works by turning off a switch when the current reachesa particular value. It is possible if the duty cycle is larger than 50% that thecurrent will not return to the value at the beginning of the control interval.


t

iL

vc

IL

Switchturnson

Switchturnsoff

Switchturnson

ton

toff

ton

toff

Constantoff

t

Figure 6.27: Waveforms for constant “off” time control.

Therefore in the next control interval the current will reach the desired valuesooner (since it is starting off with an offset). Therefore the switch will turn offsooner than it otherwise would, and consequently the “off” time will be longer.Therefore at the end of this interval the current may be lower than the desiredvalue. This would result in the control deciding to turn the switch on longer,since we are now starting from a negative offset compared with the correctvalue if this phenomena were not occurring. One can see that the period of theoscillation caused by this jitter in the duty cycle results in a frequency that ishalf the switching frequency.

In addition to the subharmonic oscillation problem, one also has a form ofopen loop instability with current mode control [14]. The following discussion open loop instabilityis with reference to Figures 6.29(a), (b) and (c). Consider Figure 6.29(a) showsthe effect of a perturbation of the inductor current (dashed line) away from thenominal current (the solid line). Notice that the perturbation dies away in thiscase. The effective duty cycle changes due to the way that current mode controlworks.

Figure 6.29(b) shows a similar situation, but in this case the duty cycle islarger than 0.5. One can see that instead of the error between the nominalinductor current and the perturbed version getting less, it actually increaseswith each successive control interval. Therefore, there is effectively positivefeedback in this case.

6.3.3.3.1 Slope Compensation Many of the problems with current modecontrol can be overcome by using the technique called slope compensation. Thistechnique involves adding a sawtooth waveform to the current feedback wave-


t

iL

vc

IL

ton

toff

ton

toff

Clock Clock ClockTs Ts

Constant periodbetween clock

pulses

Figure 6.28: Waveforms for constant frequency with turn-on at clock time con-trol.


Ve

Ve

Ve

t

t

t(a) Duty cycle < 0.5

(b) Duty cycle > 0.5

(c) Duty cycle > 0.5, slope compensation

m1

m2

m

Compensated voltagereference

D

D

D

iL

iL

iL

m1

m2

m1

m2

i0

i0

i0

Figure 6.29: Open loop instability of current mode control. (a) stability withduty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with dutycycle > 0.5 and slope compensation.


form, or alternatively subtracting a sawtooth from the voltage error signal fedto the current mode controller comparator.

Figure 6.29 shows the effect of slope compensation. In this case the sawtoothwaveform is subtracted from the error voltage, Ve coming from the voltage erroramplifier. This effectively forms a new reference for the current control section ofthe loop. In this case, even though the duty cycle is larger than 0.5 the perturbedcurrent returns to the nominal current (as was the case for D < 0.5). Theadded ramp has a constant value, and therefore the sensitivity of the feedbackto variations in the current measurement becomes less. To understand how thisworks one can look at the extreme case when the current in the load is very lowand the ramp is added to the current measurement. In this situation the controlvoltage from the error amplifier is being compared to the slope compensationvoltage, and hence the circuit is essentially operating in the normal triangularwave comparison mode of voltage control. Therefore, the addition of the slopecompensation brings in some features of voltage control into the current modeloop, and under the situation of low currents it effectively behaves as voltagecontrol (and therefore would have the dynamics of voltage control).

Let us consider this situation in a little more detail. One can see fromFigure 6.30 that the current perturbation error at the beginning of a controlinterval, ∆i0, is related to the current perturbation error at the end of the nextcontrol interval, ∆i1, as follows:

∆i1 = −∆i0

(m2

m1

)(6.50)

Remark 6.21 Equation (6.50) shows that if |m2| > |m1| then |∆i1| > |∆i0|– i.e. the error has increased after one control interval. This situation wouldcontinue.

This situation correlates to D > 0.5, since for the circuit to be in steadystate, i at the beginning of the interval, must be equal to the value at the end.This implies that |m2| > |m1|. Therefore the two conditions are synonymous.

As mentioned above the compensation can be carried out by adding theslope compensation waveform to the current, or subtracting from the voltage.The techniques can be shown to be equivalent. Therefore, assuming that we areadding to the current we can modify (6.50) by adding the slope compensationto give:

∆i1 = −∆i0

(m2 + m

m1 + m

)(6.51)

If the duty cycle is near 100% then the slope m1 ≈ 0. Furthermore, we wishthat ∆i1 < ∆i0 for the error to be decreasing over successive control intervals.Using these facts we can write the following:

−∆i0

(m2 + m

m1 + m

)< ∆i0 (6.52)

∴ −(

m2 + m

m1 + m

)< 1 (6.53)

implying m > −12m2 (6.54)


i0

i1

m1

m2

xi

m

0

1

xi

m

1

2

t

Figure 6.30: Geometrical relationship of the current waveform slopes when thereis a current perturbation.

Remark 6.22 Equation 6.54 shows that the slope of the ramp that must beadded to the current or subtracted from the voltage error must be greater thanhalf the magnitude of the down slope of the inductor current.

If one considers (6.51), and consider it to be a discrete iterative expression,then the inductor current behaves as though it is an underdamped RLC circuit.This is shown in Figure 6.31. This RLC response can be damped out (akin tocritical damping) by choosing m = −m2. The effect of this is shown graphicallyin Figure 6.32.

i im m

m mn n

FHG

IKJ( )1

2

1

2T1T 3T 4T 5T

t

Figure 6.31: Inductor current response of current mode converter.


m2

m m2

t

m1

Ve

io

Figure 6.32: Optimal slope compensation to eliminate RLC type oscillations.

Chapter 7

Introduction to PracticalDesign of Switch ModePower Supplies

7.1 Introduction

In this chapter we shall briefly look at the most important aspects of the physicalcomponent design of a switch mode power supply (SMPS). The approach takenis a very practical one, with some theory where appropriate.

The design of a switch mode power supply, like most electronics design, iscomplicated because of the large number of design trade-offs that are available.This fact means that this presentation is far from exhaustive, nevertheless thesalient issues in making design choices will be emphasised. The design of SMPSsis complicated even further by the fact that virtually all SMPS’s use magneticsin their design. Consequently much of this chapter will be concerned with thedesign of these magnetics.

The first section of this chapter will consider issues related to the selectionof the electronic components of a SMPS. The second section of the chapter willlook in some detail at the design of SMPS magnetics. Much of the material inthis chapter is closely based on [13].

7.2 Component Selection

The information on the selection of components for SMPSs is usually materialthat ends up in vendor’s application notes (if one is lucky), or in the mind of adesigner. This information therefore is often very inaccessible to a new designer,and is often attained by many disappointing design exercises. In this sectionwe shall attempt to highlight some of these hard-to-find selection criteria for avariety of components: resistors, capacitors, Schottky diodes, rectifier diodes,BJTs, MOSFETs, op amps, and comparators.

224 Introduction to Practical Design of Switch Mode Power Supplies

7.2.1 Resistors

The resistor is probably the most ubiquitous of all electronic components. Con-sequently most electronic designers don’t pay a lot of attention to details otherthan its value and power rating.

7.2.1.1 Values

There is a practical maximum value for a resistor that is used on a PCB. Thispractical limit occurs for several reasons:

• Large resistor values are not commonly available (although they can beobtained for specialised applications).

• If a very large value of resistor is used, then the resistance across the PCBbetween the resistor legs may be comparable or less than the resistor value.Therefore the resistor is ineffective.

• Using large resistor values makes the circuit very susceptible to electri-cal noise. A large value of resistance means that very small capacitivelycoupled currents can result in large coupled voltages.

Remark 7.1 Don’t use large values of resistance in your designs if at all possi-ble. Even values of 220kΩ can cause significant noise pickup problems, especiallyin switching applications which are inherently noisy in any case.

7.2.1.2 Resistor Types

Obviously choosing the correct resistor for the job is necessary in electronicsdesign. There are several resistor choices, depending on the application.carbon composite

The oldest style of common resistor is the carbon composite resistor. Onecan usually tell these resistors by the large size for their power rating. One maystill find these resistors in a hobbyist store, but for professional circuit designthey are no longer used, as there are much smaller, lower cost, and more reliableresistors available.Another interesting point about carbon resistors is that thepreferred values made were far fewer than the more modern resistors (only 12per decade).metal film

The most commonly used resistor today is the metal film resistor. These areavailable in a wide range of values, and low to moderate power ratings (severalwatts).As noted in the previous paragraph, there are a lot more preferred valuesin these resistors (48 to 96 values per decade, depending on tolerance).wire wound

For higher power rating applications there are several choices. The wirewound resistor is the one that most people would be familar with (a heatingradiator element is an extreme form of this type of resistor). They are gener-ally available in power ratings from 1W to approximately 1kW (and sometimeslarger values for special applications such as regeneration banks in large in-verter systems). One problem with wire wound resistors is that they have highinductance, which makes a conventional wire wound resistor unsuitable for highfrequency applications. Fortunately, it is possible to wind the resistor with equalturns in two different winding directions so that the inductance can almost beeliminated (the flux produced from each winding direction cancels). Variable

7.2 Component Selection 225

resistance wire wound resistors are called Rheostats. These are most commonlyused in laboratories for experiments, rather than in commercial products.shunt

Another common type of resistor used for current sensing applications is thecurrent shunt. This resistor type usually has a very low, but precisely knownvalue. One can detect the voltage across the resistor, and then use Ohm’s Lawto deduce the current through the shunt. The shunt itself is made of metalsthat have a very low temperature coefficient. A low cost shunt can be createdusing a PCB track itself. This should only be considered where cost is theprimary consideration, since the accuracy of such a shunt is not very good. Itshould be noted that shunts provide a non-isolated measurement of current.In many applications this is all right, but in other applications where isolationis important then additional measures must be used to gain isolation of themeasurement. Table 7.1 summarises these comments.

Type Suggested Applications

Carbon composite Not commonly used anymoreMetal film General purpose – replace carbonWire wound (inductive) and rheostat Used for high power load resistorsWire wound (non-inductive) Used in high frequency applicationsShunt Used for measuring large currentsPCB track Used for low cost measurement of currents

Table 7.1: Resistor application selection guide

7.2.1.3 Tolerance

One important attribute of a resistor is its accuracy. Many years ago the “gardenvariety” resistor had a tolerance of 5%, and the exotic resistors had a toleranceof 1%. These days the default tolerance of resistors is 1%, and at slightly higherprice one can have resistors with 0.1% tolerance.

7.2.1.4 Selecting Values

In many designs the specific value of a resistor does not matter (although insome it does as well). If this is the case then only the ratio between resistorsis important. Therefore, in order to minimise the number of components thatneed to be ordered it is better to try an choose the same values of resistor wherepossible. For example, if sections of the circuit rely on resistor ratios, thenchoose one resistor out of the two to be say, 10kΩ. One can then choose theother to satisfy the ratio requirement.

7.2.1.5 Maximum Voltage

Voltage ratings are not a parameter that immediately comes to mind whenthinking of resistors. However, in the case of surface mount resistors, the spacingbetween the ends of the resistor means that voltage rating must be considered.In SMPS circuits one can be dealing with voltages anywhere from 10s of volts


to 100s of volts, and at the top end of this range resistor voltage rating can beimportant.

7.2.1.6 Temperature Coefficient

Most modern metal film resistors have a very small temperature coefficient ofthe order of 50–250ppm/C. Wire wound resistors however, depending on thematerial they are made from, can exhibit substantial changes of resistance withtemperature. This is especially a problem with these resistors, since by defini-tion they will undergo large temperature changes. Shunt resistors, as mentionedin Section 7.2.1.2, are purpose designed to exhibit very low temperature coeffi-cients. They also usually have a very low value so that power dissipation is lowin the resistor, and hence temperature rise is kept to a minimum.

7.2.1.7 Power Rating

All resistors have a maximum power rating. However, a resistor should not beoperated at its maximum power rating, since it is severely stressing the compo-nent. This severe stress usually results in a high failure rate of components.half power opera-

tion In order to ensure high reliability of resistors it is recommended that a re-sistor, at worst, is operated at half its nameplate power rating. It is probablybetter to be even more conservative than this and operate the resistor at ap-proximately 1/3rd of its power rating.

Practical Issue 7.1 Select resistor power ratings so that they are operating atapproximately 1/3rd of the device specified power rating.

pulsed powerThe above comments are implicitly for continuous power dissipation. How-

ever, one can modify them in relation to pulses of power, especially for wirewound resistors. Manufacturers of these resistances will sometimes give a tableof pulsed powers for pulses of less than 100msec.

Practical Issue 7.2 Power ratings for non-wire wound resistors should be strictlyadhered to. It is alright to have power pulses up to the maximum rating of theresistor for short durations (say less than 100msec) providing the repetition rateis not too high.

RheostatA Rheostat is a variable power resistor, as opposed to a Potentiometer which

is a variable signal level resistor. Rheostats usually consist of a wire woundresistor that has a sliding contact. The power rating for the device is for thewhole resistor. Therefore if the sliding contact is halfway along the resistor,so that only half the resistor is being used, then the power rating is half thenameplate value (so that the maximum temperature of each of the wire turnsis the same as for the full resistor). One must be particularly careful with usingthese resistors on a voltage source, as it is easy to move the slide around so thatthe maximum power rating of the active section of the Rheostat will be exceeded.One can put a current meter in the circuit to make sure that the current ratingof the device is not exceeded as adjustments are made, or alternatively anotherresistor can be put in series with the Rheostat to prevent overload.


7.2.1.8 Shunts

Whilst a shunt is a resistor, it is not used for the normal application of theresistor, which is to somehow limit current flow. With a shunt one wishes toimpede the current flow as little as possible.

A shunt is generally constructed of a near zero coefficient metal such asmanganin, attached to heavy duty terminal blocks made of brass. Shunts comein a variety of sizes, ranging from very low current shunts, up to shunts thatcan handle thousands of amps. Typically a shunt is designed to produce either50mV or 100mV at its rated current. Shunts are generally used if one wishes tomeasure low frequency or DC currents. In AC applications, current transformersare often used instead since they offer isolation.

Remark 7.2 It should be noted that the use of shunts in high power PowerElectronic applications is not very common these days. For example, it is notcommon for shunts to be used to measure the currents in inverter systems. In-stead Hall Effect transducers are used, since they have good frequency responseand offer isolation.

Consider a 100A shunt with a 100mV output. This means that the resistanceof the shunt is 100mV / 100A = 1mΩ. In addition to the resistance of the shuntthere is a parasitic inductance. For a 1in shunt, this inductance is of the orderof 10–20nH. If we assume 20nH, then we have an AC model for the shunt asshown in Figure 7.1. Obviously the impedance of this circuit is Rshunt+jωLshunt

which is frequency dependent. Clearly there is a zero in the impedance frequencyresponse, and hence above a certain frequency the voltage across the shunt willincrease due to the effect of the inductance.

Rshunt

Lshunt

Figure 7.1: Equivalent circuit model of a current shuntinductance effects

We found above that the value of resistance for a shunt is usually low. There-fore, even though the parasitic Lshunt is low, the frequency at which the zerooccurs can also be relatively low. If we use the specific values from the pre-vious paragraph, then we have that the zero in the impedance occurs whenωLshunt/Rshunt = 1 which gives f = 1mΩ/(2π × 20nH) = 8kHz. In many realapplications for shunts the currents will contain frequencies above 8kHz, andhence one would be getting erroneous current readings.

Remark 7.3 One way to raise the frequency at which the impedance zero occurswith the shunt is to raise the resistance of the shunt. However, in high currentapplications this is not feasible.

An alternative strategy is to lower the inductance of the shunt by making itfrom stacked layers of metal, instead of a single piece. There are practical limitson how far this can be taken.

A control person would immediately think of another solution to the shuntfrequency response problem – try and arrange a pole-zero cancellation so that


infinite frequency response can be obtained. The obvious way to do this is toplace a capacitor in parallel with the shunt – i.e. in parallel with the equivalentcircuit of Figure 7.1. The impedance function with the capacitor can be easilysown to be:

Zeq =Rshunt + jωLshunt

(1 − ω2CcompLshunt) + jωCcompRshunt(7.1)

where Ccomp the compensating capacitor value.If we make the assumption in (7.1) that ω2CcompLshunt 1 then:

Zeq ≈Rshunt(1 + jω Lshunt

Rshunt)

1 + jωCcompRshunt(7.2)

Clearly for pole zero cancellation we require:

CcompRshunt =Lshunt

Rshunt(7.3)

which means that:

Ccomp =Lshunt

R2shunt

(7.4)

Substituting in the values for the 1mΩ shunt one gets:

Ccomp =20nH

(1mΩ)2= 20, 000µF (7.5)

Clearly this is not a practical value of capacitance. Fortunately there is a wayto achieve the same effect in the op amp amplifier circuit that is required toamplify the current shunt voltage signals. The value of capacitance used in thiscircuit are much more reasonable values (usually in the nF range) [13].

7.2.1.9 PCB Track Resistors

If one is looking for a budget priced version of the shunt one can use the resis-tance of a PCB track. This type of shunt will have poor accuracy because itrelies on the accuracy of the track width and thickness, and the temperature co-efficient for copper is very poor (0.4%/C). However, this type of current sensecan be used for overcurrent protection.

Practical Issue 7.3 The resistance of a trace is approximately given by theformula [13]:

R = 0.5mΩlengthwidth

(1 oz. copper) (7.6)

at room temperature. Two-ounce copper has half this value.

7.2.2 Capacitors

Just as there are different types of resistors, there are different types of capaci-tors. In any design it is usually not possible to use just one type of capacitor –the correct capacitor technology must be used for the application.


7.2.2.1 Types of Capacitors

Capacitor types are defined by their construction technology. The main typesof capacitors in common use are:

Electrolytic This is one of the most common types of capacitors used forlarge capacitance. There are a variety of choices available, with the mostcommon being the aluminium electrolytics. These capacitors can havevery large values – well into the millifarad range, and many hundredsof volts. Note that these capacitors are physically very large. Thereare also tantalum electrolytic capacitors, which are available in solid andwet varieties. These capacitors tend to have maximum sizes that aresmaller than those attainable in the aluminium electrolytic variety, butthey have better high frequency performance. A distinguishing feature ofall electrolytic capacitors is that they have a polarity.

Ceramic These are the flat, disc like capacitors that home hobbyists wouldbe familar with. They are used for timing and bypass purposes. Theyare available in values from a few picofarads to 1µF. New in this rangeof capacitors are the multilayer ceramic (MLC) variety, which have verylow effective series resistance and larger maximum values (several hundredmicrofarads) as compared to the older ceramics.

Plastic These capacitors can withstand very high dv/dt across them, particu-larly the polypropylene variety. They are used in circuits such as quasi-resonant SMPSs. Another variety, Polystyrene, are more specialised, andare used where very low leakage is required, such as in sample-hold appli-cations.

Type Suggested Applications

Aluminium Electrolytic Used when large capacitance needed. Low frequencies. Bulky.Tantalum Electrolytic Use for moderate capacitances. Medium frequencies. Less bulk.Ceramic Timing and bypass applications.Multilayer ceramic High frequency bypass, low leakage applications.Plastic Use for high dv/dt applications. Low leakage current applications.

Table 7.2: Capacitor application guide

The information in the above description is summarised in the Table 7.2.

7.2.2.2 Standard Values

Capacitors do not have the same range of values as modern resistors do – in factthe preferred values are basically the same as those available in the old carbonresistor ranges: 1.0, 1.2 1.5, 1.8, 2.2, 2.7, 3.3, 4.7, 5.6, 6.8, 8.2. Note that 5.6and 8.2 are not always available.

One can get away with this crudely spaced set of values because the toler-ances for capacitors are generally not all that accurate anyway. Also, in manyapplications, it is the value of a capacitor in relation to a resistor that is the


important quantity. Therefore, one can adjust the resistor to get the desiredresult.

Practical Issue 7.4 Just as large resistor values should be avoided, one shouldalso avoid the use of capacitor values less than approximately 22pF. The reasonfor this is that capacitance exists between any parallel plates, and consequentlyparasitic capacitances on a PCB can swamp out the designed low values of ca-pacitance.

7.2.2.3 Tolerance

The tolerances on capacitors are usualy very poor – typically ±20%. Electrolyticcapacitors can have even worse tolerances than this. The other variable toconsider is the temperature range that the capacitor will operate over. Thecapacitance value can vary substantially with temperature, e.g. some types ofcapacitors can loose 80% of their capacitance at -40C.

7.2.2.4 ESR and Power Dissipation

The equivalent series resistance (ESR) of a capacitor is a very important vari-able, since it determines the performance of the capacitor in many applications,and is also closely related to the power dissipation in the capacitor. Most man-ufacturers quote the ESR at 100 or 120Hz. The reason for this is that theyimagine that the capacitor is being used in power supply smoothing applica-tions. These values of ESR are useless in determining the ESR at say 100kHz(which is necessary in power electronics applications). Therefore, if you are us-ing a capacitor in a power electronic application with high frequency currents,make sure that you have a relevant value of ESR.

Remark 7.4 The ESR resistive can have a very important effect on the voltageripple from a capacitor. For example, if one is pulling 1 Amp of ripple current at100kHz from a capacitor, and the ESR is 100mΩ, then there is 100mV of rippleintroduced by the voltage drop across this internal resistance. Therefore, if onerequires 50mV of ripple maximum, then one would need at least two capacitorsin parallel, and we have not even taken into account the amount of capacitancerequired to supply the charge to the load. The situation in relation to the ESRcould be even worse if the capacitor has to operate over a wide temperaturerange.

7.2.2.5 Aging

Aging of capacitors, especially in relation to electrolytics, can be very impor-tant. Electrolytic capacitors may have a life time figure associated with a certaintemperature of operation. Values could be 1000 hours, 2000 hours, or even bet-ter 5000 hours. When a capacitor approaches its design age the capacitancedecreases, and the capacitor will be out of specification. In the worst circum-stances the capacitor may fail.

Fortunately, for every 10C drop in temperature, a capacitors life doubles.For example, is a capacitor is rated at 2000 hours at 85C, then if it is operatedat an average temperature of 25C, then it will last 2000× 26 = 128, 000 hours,or 16 years.


Remark 7.5 The use of the average temperature the capacitor is subjected inthe above calculation is important.

7.2.2.6 dv/dt Rating

There are two forms of dv/dt rating for capacitors depending on the applicationand the technology of the capacitor. Electrolytic capacitors, for example, usuallyhave a rating on the amount of rms ripple current that they can tolerate. Thisrating is related to the average i2R lose in the ESR resistor, and the thermalproperties of the capacitor package.

Metallised plastic capacitors used in resonant and quasi-resonant convertershave a dv/dt rating. In these applications these capacitors can sometimes besubject to very rapid rates of change of voltage across them. This in turn leadsto very large current flows via the expression i = C(dv/dt). These large peakcurrents can cause instantaneous heating in the capacitor, which can result inthe destruction of the capacitor if the rating is exceeded.

Remark 7.6 Depending on the application the ripple current or the dv/dt rat-ing may be important. Ripple current tends to be the appropriate measure whenthe capacitor is being used in an application where the voltage across the capaci-tor is relatively constant. dv/dt is relevant with the voltage across the capacitorundergoes large and rapid transients.

7.2.2.7 Series Connection of Capacitors

Sometimes capacitors are series connected in order to get the required voltagerating. However, if precautions are not taken one will find that one of thecapacitors will be supporting more of the voltage than the other. This is due tothe fact that the capacitance of so-called identical capacitors are not the same.Since the same current flows into each capacitor, then one will inevitably havea higher voltage than the other.

The way to force better sharing of the voltage across the capacitors is toparallel resistors with the capacitors, as shown in Figure 7.2. This arrangementwill keep the capacitor voltages equal at DC, but depending on the values of theresistors and capacitors, there may be some degree of imbalance in a situationwhere there is a large ripple.

7.2.3 Diodes

There are two main types of diodes used in SMPS circuits – normal restifierdiodes, and Schottky diodes. We shall see in Section 8.2.1 that there are specialPN junction diodes required for very high powered applications, but we shallnot be considering these here.

7.2.3.1 Schottky Diodes

Schottky diodes are constructed using a metal-semiconductor junction, as com-pared to a normal diode which has a semiconductor-semiconductor PN junction.The special property of the Schottky diode is that it does not have the chargestorage problems that normal PN diodes have. Consequently these diodes willturn off almost instantly when a reverse voltage is applied to them. The other


+

+

Figure 7.2: Method of voltage sharing for series capacitors.

advantage if the Schottky diode, as compared to the PN diode, is that the for-ward voltage drop is much lower – approximately 0.2V for the Schottky, and0.6V for the PN diode.

There are a few caveats associated with Schottky diodes – they can onlyoperate at fairly low voltages, up to about 100V; the higher voltage Schottkydiodes tend to have a forward voltage that is approaching a PN diode; theinternal space charge capacitance of a high voltage Schottky diode can be high,thus resulting in reverse current when the capacitance is charging as the diodeis reverse biased.

7.2.3.2 PN diodes

These are the conventional diodes. They are available in many different types,from “slow” rectifer diodes, to ultrafast signal diodes. The latter are more akinto the diodes used in SMPS circuits. The ultrafast refers to the reverse recoverycharacteristics of the diode. The fast diodes have the ability to get the storedminority charge out of the diode very rapidly when the device is reverse biased.Whilst the stored charge is disappearing the diode is able to conduct current inthe reverse direction. This phenomenon is known as reverse recovery.reverse recovery

+ -

i i

+-

Forward current Reverse recovery current

v v

Figure 7.3: Reverse recovery in a converter secondary circuit.

Reverse recovery can have a variety of effects from poor converter efficiency,


+

Forward current

Reverse recoverycurrent

Figure 7.4: Reverse recovery in a boost converter circuit.

to destruction of power devices. These two situations are illustrated in Fig-ures 7.3 and 7.4.

In Figure 7.3 one can see that when the voltage across the diode reverses,the diode will conduct current for a short period of time. This current couldpotentially be very large since the impedance opposing it would be small, andthe voltage driving it large (a combination of the output filter capacitor voltagein series with the voltage appearing across the secondary of the transformerwinding, which would now aid the reverse current flow). Clearly this situationis not good for converter efficiency, and the rapid rate of change of the reverseflowing current through the diode would result in a lot of EMI being produced.

Figure 7.4 is a basic schematic of the boost converter circuit. When theMOSFET turns on energy is stored in the inductor, and the diode is reversebiased. When the MOSFET turns off the current has to continue flowing, andthe diode immediately becomes forward biased. The current then flows throughthe the load and its filters. The reverse recovery problem occurs in the nextevent. The MOSFET again turns on to store more energy in the inductor.However, because the inductor has been forward biased it has stored minoritycarriers in it. When it becomes reverse biased, these minority carriers resultin the diode conducting reverse current as well as it did when forward biased.The only limitation to the current flow is the impedance of the circuit, whichis very low in this case. Consequently, in some circumstances the MOSFETmay receive too much current and destory itself. Even if this does not happenthere will be excessive power dissipated in the device, and large amounts of EMIgenerated.

Practical Issue 7.5 Most converters will use either ultrafast diodes, or Schot-tky diodes to prevent reverse recovery problems.

Remark 7.7 Synchronous rectifiers are a very low loss rectifier emplying a


MOSFET. Even with these devices a Schottky diode is placed in parallel withthe MOSFET to take the instantaneous currents that need a path when theMOSFET is not on during the forward bias period. The body of a MOSFEThas a parasitic diode around the device, but this diode is very slow. A Schottkydiode in parallel with the device prevents the internal diode from being used.

Remark 7.8 Ultrafast diodes themselves generate a lot of EMI. This occursbecause an ultrafast diode still has reverse recovery current, the ultrafast bitbeing that it only last for a short period of time. However, as the diode rapidlydecreases the reverse current, it generates a very rapid rate of change of current,and consequent EMI.

7.2.4 The BJT

I shall not spend much time on describing the practical issues of using BipolarJunction Transistors (BFTs), since they are not commonly used today. For smallto medium power SMPSs MOSFETs have large enough current and voltagerange for most applications. For very high power applications, Insulated GateBipolar Junction Transistors (IGBTs) are more commonly used. We shall notlook at these devices here since they will be described in detail in Section 8.2.4.

Power BJT transistors were the device of choice for SMPS applications some15 to 20 years ago. They are not used today because of the difficulty in usingthe devices. For example, power BJT transistors have a very low current gain(typically known as the β of the device), especially in higher voltage applications.This means that considerable current must be supplied to the base of the deviceif there is a large current from the collector to emitter. This may not be aproblem for small converters, but it is an issue at larger powers. The consequenceof this high current is a complex and expensive base drive circuit.

A second problem is the voltage drop across the device. Even when a transis-tor is turned hard on the collector to emitter voltage is approximately 0.2 volt.Therefore the power lost in the device is approximately icvce. A MOSFET onthe other hand would have a much lower voltage drop, and therefore much lowerpower loss.

A final problem with the BJT is turning the device off. As with the diode,the BJT is a minority carrier device. Therefore it also suffers from chargestorage problems. Consequently, when the device is turned off it will continueto conduct current from the collector to the emitter until the stored chargedisappears. Special base drive circuitry must be used to get rid of the storedcharge as quickly as possible.

7.2.5 The MOSFET

As mentioned in Section 7.2.4, the MOSFET is by far the most common tran-sistor used in SMPS systems. There are two main types of MOSFETs used– n-channel devices (the most common ones), and p-channel devices – usefulin certain situations. The n-channel device turns on when there is a positivevoltage exceeding the threshold voltage, between the source and gate of the de-vice. The p-channel device is the dual of this, and turns on when the gate has avoltage that is negative compared to the source. If the source of the p-channel


device is connected to the positive supply rail of a system, then the device canbe turned on by simply connecting the gate to ground.

Remark 7.9 One could consider the p-channel MOSFET to be a device thatturns on with an active low signal, whereas the n-channel device requires anactive high signal.

Remark 7.10 The n-channel device is more commonly used because the resis-tance of these devices is less for the same size die. Consequently the cost for agiven current rating is less.

7.2.5.1 Bi-directional Conduction

It should be noted that MOSFETs can conduct current in both directions –i.e. from drain to source, and source to drain. We have seen this fact used insynchronous rectifiers in Section 5.4.9.

7.2.5.2 Power Losses

There are three sources of losses in MOSFETs used in switching applications:

Conduction losses These are the losses in the MOSFET resistance when itis on. The calculation of this loss is simple – P = I2RDSon . However,one should be aware that the MOSFET has a positive temperature coef-ficient, so as the device heats up its RDSon increases based on the typicalexpression:

R(T ) = R(25C) × 1.0078e(T−25) (7.7)

Therefore to calculate the power, one must first work out an initial powerusing the 25C value of RDSon , and then work out the temperature rise(using the package thermal resistance), and recalculate the power. Thisprocedure is carried out iteratively until the power value converges to avalue.1

Gate Charge Losses This is not really a loss in the MOSFET, but a losein the gate drive circuitry driving the MOSFET. This is due to the factthat the gate of a MOSFET looks like a capacitor. Therefore in orderto get the voltage of the gate to rise quickly a substantial current mustmomentarily flow into the gate. Many data sheets give the total charge tobring the gate voltage to a certain voltage level, Qg. If the voltage levelyou are using is different then a reasonable approximation is to multiplythe Qg data value by the ratio of your voltage to the data sheet voltage.The power can then be calculated by using P = QgV fs where fs is theswitching frequency.

Switching Losses This is a loss that is dissipated in the MOSFET itself.When a hard switching converter is turned off there is a period of timewhere the MOSFET is conducting a substantial current and is supportinga substantial voltage. During this period there is substantial power dis-sipation in the device. Clearly the more times the device is switched per

1Usually this calculation only requires one or two iterations. The thermal resistance is apoorly known parameter, and if convergence does not occur then one is probably dissipatingtoo much power.


unit time, then the more average power will be dissipated in the device.In order to roughly calculate the losses due to switching one can assumethat as the device turns off or on that the voltage rises or falls as a linearfunction of time. Whilst this is happening the current through the deviceis more or less constant. Therefore the expression for the power dissipa-tion for one on-off event would be the average voltage times the current –i.e. P ′ = IpkVpkts/2, where ts is the time for the on-off switching event.Therefore the total power dissipated over a one second interval (i.e. the to-tal energy dissipated in the device per second) is the energy dissipated perswitching event multiplied by the number of switching events per second– i.e. P = IpkVpktsfs/2

Remark 7.11 By calculating the conduction and switching losses, and usingthe thermal resistance of the MOSFET package one can come up with an esti-mate of the temperature rise of the device. This estimate is a good measure ofwhether the device is going to run hot or cool.

7.2.5.3 MOSFET Gate Resistors

You should always put a resistor in series with the gate of a MOSFET. This isrequired because the gate capacitance in series with the gate lead inductanceforms a high Q series LC resonant circuit. These circuits can oscillate at fre-quencies in the 100s of MHz range. They result in excessive heating of theMOSFET and the emission of copious EMI radiation from the circuit. Theinclusion of the gate resistor provides the necessary damping to lower the Q ofthe resonant circuit so that any oscillations are damped out quickly.

Practical Issue 7.6 If you have two MOSFETs in parallel you should put anindividual resistor in series with each of the gates. If a single resistor is sharedbetween two gates then oscillations can occur between the two MOSFET gates.

7.2.5.4 Maximum Gate Voltage

Some designers decide to make the gate-source voltage very high in order to getthe gate voltage past the threshold voltage of the MOSFET in the minimumtime. If the gate-source voltage exceeds approximately 20 volt, then the MOS-FET is likely to be damaged. To turn a device on the most important thing isto have a very low impedance gate drive so that the current can be sourced tocharge up the gate capacitance.

7.2.6 Operational Amplifiers

Operational amplifiers are used extensively in SMPS control systems. We havebriefly considered control aspects of SMPS in Section 6.3. This discussion how-ever, did not consider some of the practical issues involved in using Op Amps.These practical issues are related to the non-ideal behavious of Op Amps. Muchof the following discussion is relevant to general usage of Op Amps, and is notparticular to their use in SMPSs.


7.2.6.1 Offsets

There are two main types of offsets in Op Amps:

1. Input Offset Voltage. This is effectively a voltage between the + and− terminals of the Op Amp. It is a result of manufacturing differencesbetween the electronics of the input circuitry of the Op Amp. The offsetvoltage is usually a small value – i.e. mV or µV.

2. Input Offset Current. The input impedance of a real Op Amp is not infin-ity. Therefore current will flow into the terminals. Due to manufacturingtolerances, the current in the + and − terminals can be different. Theinput offset current is very small in absolute terms – usually of the orderof nAmp.

Considering the small values for the offset voltage and current one migh betempted to say; “What is the problem?”. The problem with the offsets is dueto the fact that an Op Amp has a very high open loop gain, which is usuallygreater than 106. Therefore, if one has, say a 2mV offset voltage at the input,then the output would be 2 × 10−3 × 106 = 2 × 103. Most Op Amps operateon a power supply of 12 to 15 volt. Therefore the offset voltage would result inthe output of the Op Amp being saturated to the supply rail.

The immediate retort to the above paragraph is that Op Amps are neveroperated in open loop, but have feedback around them that lowers the effectgain. However, even with feedback, the gain can still be quite high, resulting insignificant output offset voltage. Similar arguments can be mounted with offsetcurrent when there are resistances in series with the inputs.

+

-

100k

10k9.09k

LM2902

Figure 7.5: Operational amplifier circuit for discussion of offsets.

7.2.6.1.1 Input Offset Voltage The following discussion is with referenceto the circuit of Figure 7.5. This shows a typical Op Amp circuit, with the non-inverting input shorted to ground. If the Op Amp was ideal then the outputvoltage would be zero under these conditions. However, the offset voltage fora LM2902 Op Amp is approximately 2mV. This means that there is effectively


2mV between the + and − terminals. The gain of the amplifier is 10 in thiscase, making the output with a zero input voltage equal to ±2mV ×10 = ±0.02volt. In many applications this may not be a problem. However, if the gain was1000 then the output offset would be 2 volt, which is clearly unacceptable.

Remark 7.12 Note that the output offset due to input offset voltage is not adirect function of the resistors used, but is related to the gain of the amplifier.

7.2.6.1.2 Input Offset Current The following discussion is also with re-spect to Figure 7.5. In this case we shall assume that the offset voltage is zero.Because the inputs to a real Op Amp take slightly different currents, then thevoltage at each of the input pins can be slightly different due to the differeingvoltage drops across the resistors. For example, in the case of the LM2902, thedifference between the input currents can be as much as 5nA. Therefore the volt-age difference between the two terminals can be 9.09× 103 × 5× 10−9 = 45µV.This voltage, in turn, is amplified by the gain of the amplifier to give 450µVoutput voltage. As with the offset voltage case, in many applications this is notserious, but if the gain is high, or very high precision is required, then the effectof the input current offset may cause significant output voltage offset.

Remark 7.13 The effects of input current offset occur simultaneously with in-put voltage offset, therefore the output offsets have to be added together.

Remark 7.14 Input current offset will become more pronounced if larger resis-tance values are used.

Remark 7.15 More expensive amplifiers are laser trimmed internally in orderto lower the input offset current.

7.2.6.1.3 Input Bias Current The input bias current is the current thatflows into the input terminals even if there is no input offset current effect.The input bias current can cause offset problems if the resistances in the inputterminal leads are mismatched. In the case of Figure 7.5 we have been carefulto choose the resistors so that the effective resistance through which the biascurrents flow is the same. However, if there is a mismatch in the resistancevalues due to resistor tolerances, or alternatively due to other external circuitconsiderations, then there will be different voltage drops across the input circuitresistors. This results in the generation of different voltages on the input pinsto the Op Amp.

As a specific example, if we assume that the resistor to ground from thenon-inverting terminal is 19.09kΩ, and the input bias current for the LM2902 is90nA, then the difference in the resistance seen by the two bias currents is 10kΩ.Consequently the bias current offset voltage is V = 90nA×10kΩ = 900µV. Thisvoltage in turn is amplified by the amplifier gain of 10, giving an output offsetof 9mV.

Remark 7.16 Clearly, one should try and get the resistance in series with theOp Amp inputs to be the same values to eliminate the effect of bias currents onthe output.


Summary 7.1 Given the above discussion, we can develop and expression forthe output offset:

V = [Vos + IosR + Ib∆R]Acl (7.8)

where Vos the input offset voltage, Ios the input offset current, Ib theinput bias current, R the average value of the input resistors, ∆R thedifference between the values of the resistors, and Acl the closed loop gain ofthe amplifier.

Remark 7.17 One can see from (7.8) that in order to minimise the outputoffset one must:

• Keep the resistor values as small as feasible to minimise the effect of theIos current.

• Make sure the input resistor values are closely matched so that ∆R ≈ 0 .

• Choose an amplifier with a very small Vos. Note that a low Vos Op Ampoften has a lower gain-bandwidth product.

7.2.6.2 Limits on Resistor Values

+

-

10k

10M

10k

Figure 7.6: Conventional inverting Op Amp circuit with a gain of 1000.

It has been previously mentioned in Section 7.2.1.1 that it is not desirablein general to choose large values of resistors. In Op Amp circuits there is oftena temptation to do this when one is endeavoring to get a high gain feedbackamplifier. Let us consider the specific example circuit shown in Figure 7.6. Thisis a conventional inverting Op Amp circuit, and the resistors have been choosenso that the feedback gain of the circuit is 1000. The other requirement is thatthe input impedance of the circuit is 10kΩ. Consequently the feedback resistoris 10MΩ. This value of resistor is far too large to be practical. Besides theproblem that it will pick up a lot of electrical noise, it may not even be effectivesince the leakage impedance across the PCB is probably lower than this value.2

2If one did not have the input impedance constraint then a smaller value for the inputresistor could be choosen so that the feedback resistor would be less than or equal to 1MΩ.


+

-

R1

R2

R1

R3

R4

vinvo

Figure 7.7: Inverting Op Amp circuit with alternative feedback network.

An alternative circuit that can be used in this situation is shown in Fig-ure 7.7. In this case the feedback voltage is lower by the inclusion of the voltagedivider network comprised of R3 and R4. This result of this network is thatthe output voltage has to be higher in magnitude than it otherwise would be toget the full input current (vin/R1) to flow through the R2 resistor. The benefitthat one obtains is that there is much more freedom to choose the resistors sothat one can keep reasonable values and obtain the required gain.

If one calculates the gain of the Op Amp circuit of Figure 7.7 then it can beshown that it is:

vo

vin= −R2R4 + R3R4 + R2R3

R1R3(7.9)

Let us consider the specific example of a gain of 1000. If we assume that theinput resistance of the circuit has to be 10kΩ, then this makes R1 = 10kΩ.Let us then choose R3 = 1kΩ, which will result in a significant voltage divisioneffect through the feedback network without having the other resistor valuestoo large. We still have two other resistor values to choose – R2 and R4. Letus arbitrary choose R2 = 100kΩ. The denominator of (7.9) now has a value of10MΩ, which means that the numerator must have a value of 1010Ω to achievethe required 1000 gain. The only unknown now is R4. Substituting the knownvalues into the numerator expression of (7.9), and equating to 1010, one cancalculate that R4 = 98kΩ. Therefore, to summarise, the resistor values are:R1 = 10kΩ, R2 = 100kΩ, R3 = 1kΩ, and R4 = 98kΩ. We have achieved therequired gain from the circuit without having to resort to any resistor valuesgreater than 100kΩ. This would reduce the noise pick of this amplifier circuitconsiderably.

Remark 7.18 A similar feddback resistor arrangement can be used for in-verting amplifiers. However, in this case one is not constrained by the inputimpedance requirement, and therefore one has more freedom to choose the resis-tors in the conventional non-inverting feedback amplifier.


log f

Gain (dB)

Gain bandwidthproduct

Aol

Acl

0

fcl3dbfol3db

funity

Figure 7.8: Gain-bandwidth product of an Op Amp.

7.2.6.3 Gain-Bandwidth Product

Consider Figure 7.8 which shows a typical frequency response of an amplifier.The open loop gain, Aol, of the amplifier is very high – a gain greater than 106

is normal. However, the open loop frequency response rolls off at a very lowfrequency, usually 1 to 2 Hz. Since Op Amps are not designed to be used in openloop this is not a concern. Eventually the open loop gain of the amplifier goes toone. The frequency at which this occurs is the gain-bandwidth product of theamplifier. This figure is a constant for the amplifier. Therefore, if one appliesfeedback around the amplifier, this will lower the gain to say Acl. Thereforethe roll-off frequency of the amplifier will be increased. The frequency of the-3db roll-off multiplied by the gain at this point is equal to the gain-bandwidthproduct. Therefore Aolfol−3db = Aclfcl−3db = funity.

The importance of the gain-bandwidth product is that it indicates whetherone can simultaneously achieve the gain and bandwidth specifications from anOp Amp circuit design. There are many different Op Amps available, withwidely varying gain-bandwidth products. In SMPS applications one can findthat high gains are required to moderate bandwidths – for example a gain of300 and an bandwidth of 20kHz. In this case one would need an amplifier with again-bandwidth product of 300×20×103 = 6MHz. Whilst this is a very modestgain-bandwidth product for a discrete Op Amp, it may actually be larger thanthat of an integrated Op Amp that is inside a PWM IC. The effect of exceedingthe gain-bandwidth product of the amplifier on the performance of the SMPSsystem may be poor disturbance rejection, or even worse instability (due toexcessive phase shift in the feedback).

7.2.6.4 Phase Shift

Phase shift is related to the frequency response of the amplifier circuit shownin Figure 7.8. It is well known from control theory that at the -3dB point


of a single pole frequency response the phase shift from input to output is−45. At approxmately a decade above this the phase shift has convergedto approximatley −90. In an Op Amp circuit the situation is often morecomplicated than this due to the effects of internal compensation within the OpAmp itself. This can result in even more phase shift due to the introduction ofmore poles in the higher frequency areas of the frequency response.

The only way to accurately determine the phase shift characteristics of anOp Amp is to actually meaure them over the frequency range of interest. Itis not always true that amplifier with higher gain-bandwidth product will haveless phase shift.

Remark 7.19 Excessive phase shift through an error amplifier in a feedbackloop can result in a degraded phase margin. The result on the performance isringing when there are step changes in the system, or marginal stability.

7.2.6.5 Slew Rate Limits

Slew rate limits are a non-linear effect related to the current limitations on theoutput stages of an Op Amp. Any Op Amp has a maximum rate at which theoutput can change. This is different from the gain-bandwidth product whereone is assuming that the high frequency signals are very small in amplitude,and therefore do not encounter slew rate limit problems.

Consider the situation where an Op Amp circuit is being driven by a sinewave. The maximum rate of change of the sine wave occurs when it goesthrough zero. The slope of the sine wave at that point is given by its deriva-tive, Vmω cos ωt, evaluated when ωt = nπ, n = 0, 1, 2 · · · . One can see that themaximum slope increases with both frequency and amplitude of the sine wave.Therefore, if the amplitude is increased at a given frequency then it may bepossible to exceed the slew rate limit of the amplifier.

If one had an amplifier of gain 10, with a 1 V p-p input sine wave input, thenthe output would be 10 V p-p. If the frequency of the input is 200kHz, thenthe maximum rate of change of the output would be 10 × 2 × π × 200 × 103 =12.6V/µsec. Many low power Op Amps cannot slew their output this fast.When the slew rate limit is hit, the output tends to increase as a straight lineat the slew rate.

The slew rate becomes important in high-bandwidth SMPSs. When there isa rapid tranient at the output, the error amplifier will see a large input. If theoutput slew rate of this amplifier is hit, then it will effectively introduce a phaselag in the feedback. This can result in poor distrubance rejection. It could alsoaffect phase margins.

7.2.7 Comparators

A comparator is a special type of Op Amp specialised for comparison applica-tions. In relation to voltage and current offsets the same principles apply to thecomparator.

7.2.7.1 Hysteresis

Almost always whenever a comparator is being used it should incorporate hys-teresis in the input. This is to prevent false triggering and potential oscillation


of the device.

+

-

R1

R2

Vref

vin

vo

Figure 7.9: Comparator with hysteresis.

Figure 7.9 shows a comparator circuit with hysteresis established by thejudicious application of positive feedback. If one carries out a little analysis onthis circuit then one can see:

v+ = vin

(1 − R1

R1 + R2

)+(

R1

R1 + R2

)vo (7.10)

where v+ the voltage on the ‘+’ terminal of the comparator.To understand how this works, let us consider a specific example. Assume

that R1 = 1kOmega and R2 = 100kΩ, which means that R1/(R1 + R2) ≈ 0.01. Under thiscondition:

v+ = 0.99vin + 0.01vo (7.11)

If v+ < v−, then vo = −V , the negative supply voltage. If this is substitutedinto (7.11) and the expression is rearranged, then for v+ = Vref we have:

vin =Vref + 0.01V

0.99(7.12)

Therefore the input voltage, vin, has to be greater than the reference approx-imately by 0.01V (it is actually a little more than this). At this input thecomparator would switch so that the output voltage would become +V . Wecan then repeat (7.12) for this case and get:

vin =Vref − 0.01V

0.99(7.13)

As we can see the input voltage has to be less than the reference voltage, again byapproximately 0.01V for the comparator to reach the switching state. Thereforewe have implemented classic hysteresis by the process, with the hysteresis bandbeing approximately 0.01V around the nominal reference voltage.


7.2.7.2 Comparator Interfacing

Comparators that have a single supply rail often don’t pull the output rightdown to the dround rail when the output should be zero. This can have adramatic effect if the device is driving a BJT or a logic gate. For example, somecomparators are only guaranteed to have a low output of approximately 0.6-0.7V when sinking 6mA of current.

Practical Issue 7.7 If the comparator output does not pull to near zero at thecurrent level the output will be operating at, then the output voltage under thelow condition must be accounted for when calculating the resistors for hysteresis.

+

-

+V

+V

10k

Figure 7.10: Interfacing a comparator to an NPN transistor.

Figure 7.10 shows a technique for interfacing a comparator to a NPN tran-sistor. If the comparator only pulls down to say 0.7V, then the 0.7V drop acrossthe diode will ensure that the transistor is still off. The 10kΩ resistor ensuresthat the base of the transistor is firmly connected to ground when the diode isturned off. For the comparator to turn the transistor on the output needs to begreater than 1.4V.

7.3 Introduction to Magnetics Design

The design of magnetics for a real application is a complex task. there aremany application specific decisions that have to be made – the core material,core style, type of conductor etc. There is usually no corect answer, since theparticular solution that a designer ends up with depends on the criteria used todecide the optimal solution.

The following discussion is far from an exhaustive treatise on the design ofmagnetic for SMPSs. The presentation closely follows that in [13], and willconcentrate on some of the main practical issues. A more detailed treatment ofthe design on magnetics for SMPSs can be found in [12].

7.3 Introduction to Magnetics Design 245

7.3.1 Review of the Fundamentals

Before looking a the specifics of SMPS magnetics design, it may be opportuneto review the fundamental concepts and expressions that are required.

7.3.1.1 Ampere’s Law

The law that connects the magnetic field intensity and mmf produced. It alsoconnects the magnetic field intensity and the flux produced. The normal integralequation for Ampere’s Law in a physics or electromagnetics text is:

F =∮

H · dl (7.14)

where boldfacing means that the quantity is a vector, and F the mmf inAmpere-turns, H the magnetic field intensity vector in Ampere-turns/metre,and dl an incremental path length vector. The direction of the H vector isthe same as the direction of the flux vector in a isotropic medium. The directionof the magnetic flux density vector, B, can be determined by other techniques,but is defined for practical purposes by the right hand rule.

Let us consider the application of (7.14) to a single strand of wire. We knowapriori that the F value in this case is I, the current being carried in the wire.Since the H and dl vectors are coincident around a circular path of integration(since the H vector is in the same direction as the B vector), and the total pathlength is 2πr, then one can conclude that:

H =I

2πr(7.15)

where r the radius of the path of integration.

Remark 7.20 Equation (7.15) implies that the magnetic field intensity can bedefined as:

H =mmf

l=

F

l=

NI

l(7.16)

The relationship between Ampere’s Law and the magnetic field intensity isdefined by the follwoing:

B = µrµ0H = µH (7.17)

where µr the relative permeability, and µ0 the permeability of free space.Equation (7.17) allows Ampere’s Law to be recast into a flux density form:

F =1µ

∮B · dl (7.18)

In certain circumstances Ampere’s Law can be used to evaluate the magneticfield intensity, and under some circumstances the magnetic flux density. Fortu-nately, the design of transformers is one of the applications where the geometryis constrained in such a way that Ampere’s Law can be successfully applied ina simple fashion.


7.3.1.2 Faraday’s Law

Faraday’s Law is one of the fundamental laws of electricity. It was origi-nally determined experimentally, and later derived from the more fundamentalMaxwell’s equations, and subsequently from relativity theory. Every electricalengineer should know Faraday’s Law, but we will restate it here for complete-ness. Figure 7.11 shows a typical situation where Faraday’s Law is active. Here

B(t)

Area Av(t)

Figure 7.11: A loop of wire enclosing an area of time varying flux density.

we have a loop of wire, and orthogonal to the surface of the loop there is a timevarying flux density, B(t).3 A voltage, v(t) is generated between the ends ofthe wire under this circumstance. Faraday’s Law tells us the magnitude of thevoltage under this condition:

v(t) =dλ

dt= N

dφ

dt= NA

dB

dt(7.19)

where λ the flux linkage, φ the flux, and N the number of turns of thecoil.

7.3.1.3 Inductance

We know from Ampere’s Law that a wire produces magnetic field intensity, andconsequently magnetic flux density. The inductance of a coil is a number thattells us something about how well the physical configuration of the coil producesflux density. For example, if a coil has more turns on it then it would have moreinductance, if a coil has a large area then its inductance is larger, and it a coilis wrapped around a high permeable core material then its inductance will behigher. In all these situations, a higher inductance indicates that the coil isbetter at producing flux.

The fundamental definition of inductance is:

L =dλ

di(7.20)

3If the magnetic flux density vector is not orthogonal to the surface area, then it is thecomponent that is that contributes to the Faraday voltage effect.


In the case of linear magnetic materials (i.e. the flux density varies linearly withthe current through the coil) this expression can simply be written as:

L =λ

I(7.21)

Remark 7.21 A verbal definition of inductance is that it is the flux linkageproduced though the coil per unit current flowing through the coil.

Remark 7.22 Equation (7.20) is evaluated around some point of operation.Strictly speaking this definition is called the incremental inductance, since it isoperating point dependent (i.e. dependent on the values of λ and i).

Equation (7.21) can be used to develop the expression for the inductance interms of the physical parameters of a coil. From (7.21) one can write:

L =Nφ

I=

NAB

I(7.22)

Since B = µH = µNI

l

∴ L =µN2A

l(7.23)

where l the length of the magnetic path.

Remark 7.23 One can see from (7.23) that the inductance is defined entirelyin terms of the physical characteristics of the coil. Note that the inductance isrelated to the square of the coil turns.

Remark 7.24 In the case of a high permeability material as the coil the lengthof the magnetic path is easy to determine in (7.23).

One can develop Faraday’s Law in terms of inductance using the flux formof Faraday’s Law and (7.22). From (7.22) one can write:

NAB = Li (7.24)

where the lower case i indicates that the current is changing. Substituting thisinto (7.19) one can easily see that:

v =dLi

dt= L

di

dtfor L constant (7.25)

which is the familiar voltage relationship from circuits.

Remark 7.25 Note that the L constant is not correct when the core materialin a ferro-magnetic material which saturates.

7.3.1.4 A Note on Units

Unfortunately the area of magnetics is permeated with inconsistent units. Thissituation exists for largely historical reasons. Most of the unit confusion occursbetween the mks system of units, and the cgs system. Just to make things evenmore confusing imperial units are also sometimes thrown in as well. Whereverpossible I will use mks units in these notes.


7.3.1.5 The Three R’s

In magnetic circuits three terms beginning with the letter R are often used –Reactance, Remanence and Reluctance. We shall briefly review these (mostelectrical engineering students should already know what they are).

7.3.1.5.1 Reactance This is a quantity similar to resistance that is usedwhen a circuit contains reactive elements such as inductors and capacitors. Thereactance can be used in a generalised form of Ohm’s Law.

For an inductor the magnitude of the reactance is Zl = 2πfL where f isthe frequency of the voltage across or the current through the inductor. Thevoltage across the inductor is related to the reactance by Vl = ZlI, where Vl

and I are AC phasors. A similar situation occurs with capacitance, where themagnitude of the reactance is Zc = 1

2πfC .If both resistance and reactance are both present, the impedance magnitude

is:

|Z| =√

R2 + Z2 (7.26)

where Z is the generic impedance of the reactive element.

H

B

Bm

Br

Figure 7.12: A BH loop for a magnetic material.

7.3.1.5.2 Remanence Figure 7.12 shows a BH loop for a ferro-magneticmaterial. Notice that if the H is applied so that b = Bm and then driven backto zero there is some remenant flux still in the core. The level of this flux is theremanence of the core, and varies depending on the material. If the core is air,then the remanence is zero.

Remark 7.26 Remanence is important as it relates to core utilisation andlosses. For example a core with high remanence used in a uni-fluxed SMPSwill have a lower core utilisation. If use in a flux reversing type of SMPS thehysteresis losses will be high.


7.3.1.5.3 Reluctance Reluctance is often used in circuit analogies of mag-netic systems. Reluctance can be used in a way that is analogous to resistancein conventional circuit theory. Just as with resistance, the reluctance of a “mag-netic circuit” is related to the physical attributes of the circuit.

One way of developing the magnetic circuit analogy is to consider the mmfin a similar way to voltage is considered in a conventional circuit. This makessome intuitive sense because one can consider that the mmf is the driving forcethat produces the flux. We can subsitute (7.16) into (7.17) to give:

B = µH =µNI

l(7.27)

Multiplying both sides of (7.27) by the area of the core, A, gives:

φ = BA =µANI

l(7.28)

This expression can be rearranged to make the mmf the subject of the expres-sion:

F = NI =l

µAφ (7.29)

From (7.29) we can then identify the reluctance term as:

R =l

µA(7.30)

Therefore (7.29) can be written as:

F = Rφ (7.31)

where the flux, φ, is analogous to the current in a conventional circuit.

Remark 7.27 “Magnetic circuit” analogies are particularly useful in trans-former applications because the magnetic paths are very well defined and theirreluctances are known.

Remark 7.28 Notice that the reluctance defined in (7.30) obeys the same in-tuition as resistance of wires. For example, if one doubles the cross-section ofthe core (i.e. doubling A) then the reluctance drops, just as resistance would ifa wire diameter is doubled. Similarly, if the length of the core is increased thenthe reluctance increases. A similar effect also occurs with resistance.

7.3.2 The Ideal Transformer

It is beyond the scope of these notes to give a full treatise of transformers.Therefore we shall concentrate on the basic properties that are required tounderstand their design and operation in SMPS applications. We shall begin beconsidering the ideal transformer, since this is a useful concept to understandthe operation of transformers. In addition, ferro-magnetic cored transformersare a reasonable approximation to the ideal transformer.

Figure 7.13 shows the conventional circuit symbol for an iron cored trans-former. The primary winding is the winding that is being driven by the source,and the secondary winding is usually connected to a load of some description.


Core

Secondary coilPrimary coil

N1 turns N2 turns

Figure 7.13: Circuit symbol for a transformer.

The dots on the ends of the coils indicate the way that the wire is wound onthe core. If current is injected into the lead at the dotted end of the primarywinding, then the flux produced in the core will have the same direction asthat produced by the secondary winding if current is injected into its dottedterminal. From a voltage viewpoint, if a positive voltage appears on the dot-ted terminal of one of the windings, then a positive voltage will appear on thedotted terminal of the other winding.

An ideal transformer is a transformer that has a core material of infinitepermeability. This means that no mmf is required to set up a flux in the core,since the reluctance of the core is zero (regardless of its length or area). Theinfinite permeability has the implications that there will be no leakage flux inthe transformer – i.e. all the flux produced by the primary winding will link tothe secondary winding.

We can calculate some of the basic properties of ideal transformers by apply-ing Faraday’s Law using the properties mentioned in the previous paragraphs.Consider the voltage on the primary side of the transformer:

v1 = N1A1dB1

dt(7.32)

Similarly for the secondary we can write:

v2 = N2A2dB2

dt(7.33)

Since both windings are wound on the same transformer core, then A1 = A2.Furthermore, since there is no leakage of flux density from the primary to thesecondary (and vice-versa), then B1 = B2. Consequently we can write:

dB1

dt=

dB2

dt=

v1

N1=

v2

N2(7.34)

Remark 7.29 Notice that the implication of (7.34) is that the volts/turn of thetransformer are constant for both the primary and the secondary.


Since the ideal transformer requires not mmf to establish flux in the core,we can write:

N1i1 + N2i2 = 0 (7.35)

which implies:i1N2

= − i2N1

(7.36)

Remark 7.30 Equation (7.36) could also be deduced using conservation of en-ergy together with (7.34):

v1i1 + v2i2 = 0 (7.37)

Using (7.34) one can write:

v2N1

N2i1 + v2i2 = 0

∴ N1

N2i1 = −i2

ori1N2

= − i2N1

(7.38)

Remark 7.31 The negative sign in (7.38) indicates that the secondary currentdirection is opposite to the primary current direction.

Remark 7.32 The implications of (7.34) and (7.38) are that if the voltage isstepped up between the primary and the secondary then the current steps down(and vice-versa).

7.3.3 Real Transformers

Real transformers do not have core materials composed of infinite permeabilitymaterial. The relative permeability of iron based laminations is in the range of1000-2000. Many of the power based core materials, which are widely used inSMPS applications, have permeabilities in the low hundreds range. The conse-quence of having finite permeability core materials is that not all the flux that isproduced by one winding is linked to the other winding. Another consequenceis that it takes mmf to produce flux in the core, since the core has reluctanceto be overcome.

Models of real transformers are often based on taking the ideal transformerand adding some extra elements around it to account for the non-ideal be-haviour. Consider the flux required in the core to induce voltages in the sec-ondary winding. If the secondary winding is open circuit, and if we apply avoltage to the primary, then the voltage across the primary is related to therate of change of flux in the primary inductance. A small proportion of theprimary flux does not link the secondary winding, and this is called the leakageflux. The inductance associated with this flux is called the leakage inductance.Most of the flux produced by the primary links to the secondary winding, andthis is called the magnetising flux, and the inductance associated with it is calledthe magnetising inductance.

If the secondary winding has a circuit connected to it, then the voltageinduced in the secondary by the magnetising flux will cause a current to flow inthis circuit. Consequently there will be flux produced by the secondary winding.


Lm

Ll

Ideal transformer

Magnetisinginductance

Leakage inductance

Figure 7.14: Simplified model of a real transformer.

This flux will be in such a direction in the core that it will tend to cancelthe magnetising flux. However, the flux in the primary is fixed by the appliedvoltage and its frequency (via Faraday’s Law), therefore this cancellation of fluxwill result in more current being drawn from the primary circuit to compensatefor the cancelled flux. This is effectively the load current on the secondary beingreflected back into the primary circuit. These arguments lead to the diagram ofFigure 7.14. Notice that the magnetising inductance effectively shunts currentaway from the ideal transformer. Therefore the magnetising current is “wasted”in the sense that it does not contribute to the output current.4 Similarly, theleakage inductance will support voltage across it, and this voltage does notappear across the primary of the ideal transformer, and will therefore not betransformed to the secondary.

7.3.3.1 Core Materials

As mentioned in the previous section real core materials have finite permeability.In addition they also exhibit properties such as saturation, eddy current andhysteresis losses. These practical issues manifest themselves in different waysin different applications. Table 7.3 summarises that main types of materialsavailable, and their relative merits and uses.

7.3.3.2 Saturation

Saturation is a phenonmena in ferro-magnetic cores which causes the perme-ability of the core to change from the normal high value to a value near thepermeability of air as the flux density in the core increases. Another way ofstating this is that when the core saturates an increase in the current in thewinding around the core results in only a very slight increase in the flux densityin the core.

Saturation is usually a phenonmena that one is wishing to avoid, since theincremental inductance of the core decreases dramatically as the core saturates.

4The magnetising current is usually large so that the magnetising current is only a fewpercent of the load current of the transformer.


Material Consideration

Air Pro Air core magnetics cannot saturate.

Con The relative permeability of air is one, so one cannot getlarge inductances. Furthermore, the leakage of an air coretransformer would be very high.

Usage Primarily find application in rf circuits. Not used inSMPS applications.

Ferrite Pro Ferrite magnetic materials are very widely used in both elec-tronic and SMPS applications. They have very high perme-ability and therefore can be used to produce large values ofinductance. These materials are usually relatively low cost.A variety of different materials are available for differentfrequency bands (to help control the losses).

Con Ferrites usually saturate hard. Poorly controlled initial per-meability.

Usage Ferrites are often used in power transformers and noisefilters.

Molyperm (MPP) Pro Soft saturation. Wide variety of different permeabilities, andthere values are well controlled by the manufacturer.

Con Higher losses than ferrites at a particular switching fre-quency.

Usage Used for inductors and noise filters at high DC currents.Powdered iron Pro Lower cost than MPP cores.

Con Slightly harder saturation than MPP, and lower permeabil-ity generally than MPP.

Usage Same applications as MPP where cost is a more importantconsideration than size.

Steel laminations Pro Very high saturation flux density, allowing the production ofvery high inductances.

Con Comparatively expensive, heavy. Saturates hard, and hashigh losses, especially at high frequencies. New amphorousiron overcomes some of the deficiencies in relation to losses.

Usage Low frequency transformers, power inductors.

Table 7.3: Core materials and their uses.


If the core inductance is restricting current flow in the circuit, then this decreasein inductance could result in a catastrophic increase in the current.

There are two types of saturation associated with cores – hard saturation,and soft saturation. Hard saturation refers to a rapid saturation – i.e. a smallincrease in the flux density results in a very rapid change in the permeability.Ferrites and steel laminations fall into this category. Soft saturation is wherethere is not a clearly defined saturation flux density, but instead the permeabilitychanges gradually with increased flux density. MPP cores display this saturationcharacteristic.

Remark 7.33 A core is said to be saturated if the current flow in the windingof the core has reduced its permeability to 20% of its permeability at very lowcurrents.

7.3.3.3 Other Core Limitations

7.3.3.3.1 Curie Temperature This is the temperature where the corelooses all its magnetic properties. When the core reaches that temperaturethe thermal agitation of the core domains is so severe that the domain align-ment is destroyed, and hence the permeability of the material decreases. Oncethis starts then there is a form of positive feedback occurring, and the collapseof the field continues. As the field collapses the domains have less field to keepthem aligned, and therefore the thermal agitation becomes even more dominant.

For many of the magnetic core materials the Curie temperature is of theorder of 200C. This temperature is so high that the wire insulation and bobbinmaterials would be damaged it it were reached. Some inductors may not havea bobbin, and employ special high temperature wire insulation. In this case theCurie temperature could be an important limitation.

7.3.3.3.2 Core Losses Changing flux in any ferro-magnetic material resultsin losses in the material. These losses are in two different forms – Eddy currentlosses, and hysteresis losses.

Eddy current losses are due to induced current in the core by the changingflux. These currents result in resistive losses. A general expression for Eddycurrent losses is [15]:

pe = keω2B2 W/m2 (7.39)

where ke is a constant related to the particular type of material.The expression for hysteresis loss is [15]:

ph = khωBn (7.40)

where kh and n are emphircal constant dependent on the type of material.Typical values of n are 1.5 < n < 2.5 for conventional lamination steel materials.

Remark 7.34 Notice from (7.39) that the Eddy current loss is dependent in asquared sense on the applied frequency, whereas hysteresis loss in only linearlydependent on the frequency. Theefore it is very important to have a high resis-tivity for the core material in high frequency applications. The bonded type corematerials such as ferrite, MPP, and iron powder to designed to achieve this.


Let us assume that we have a magnetic structure, such as an inductor, thatis driven by a sinusoidal voltage source. It is easy to show that the maximumflux density in the magnetic structure is:

B =V

NAω(7.41)

where V the amplitude of the sinusoidal voltage source, and ω its frequency.N and A are the turns of the coil and area of the core respectively.

Remark 7.35 One can immediately see from (7.41) that if B is to be madesmaller, then N or A must be made bigger.

Consider the situation where the power loss in the core of our magneticstructure is less than the total copper losses. Based on (7.39) and (7.40) we cansee that we must increase the peak flux density experienced by the core, giventhat the excitation frequency is fixed, and the core dimensions are fixed. FromRemark 7.35 one can deduce that this means that the number of turns woundonto the core must be decreased. This will result in a lower inductance for thecore, and hence for a fixed supply voltage, a larger peak current. Therefore,even though the wire resistance would have dropped, the higher rms currentinto the core will result in higher copper losses.

7.3.4 Optimal Design Issues

It can be shown that minimum power loss is obtained in a combined electri-cal/magnetic structure if:

• The core losses are equal to the copper losses.

• The primary copper loss is equal to the secondary copper loss.

Remark 7.36 The core losses equal to copper losses equality for minimumoverall losses applies equally well to electrical machines as to inductors andtransformers.

Remark 7.37 Core losses equal to copper losses equality for minimum losses isanalogous to the maximum power transfer theorem in circuit theory. You mayrecall that this theorem says that the load resistance should be equal to the sourceresistance for the maximum power to be transferred to the load from the source.Therefore, in this case one has the same losses in the source resistance and theload resistance.5

Assuming that one has a transformer type of structure, consider the followingscenario. The power loss in the magnetics is less than that in the copper.Therefore, we wish to increase the power loss in the core and reduce the lossesin the copper. The power losses in the core can be increased if the number ofturns on the primary winding are decreased. This can be seen if we assume that

5In the case of maximum power transfer one is trying to maximise the power. In electri-cal/magnetic systems the power is minimised.


the structure in being driven at a voltage source:

v(t) = V sinωt

∴ B(t) =1

NA

∫v sin ωt dt (from Faraday’s Law)

=V

NAωcos ωt

⇒ B =V

NAω(7.42)

which is the same as the expression mentioned in (7.41).

Remark 7.38 Equation (7.42) shows that the peak flux density in the core isincreased if the number of turns in the coil are lowered.

If the number of turns in the primary coil are lowered, then the length of thecopper wire is lowered, and hence the wire resistance. If the turns in the primaryis lowered, then the turns of the secondary are lowered to maintain the sameturns ratio. If we maintain the same amount of copper under this condition, thenwe can increase the diameter of the wire, this again decreasing the resistance ofthe primary and secondary windings. These two effects mean that the overalllosses of the secondary will be reduced, since maintaining the same turns ratiomeaning that the secondary current would not change.6 One can mount asimilar argument if the losses in the core are larger than the copper losses. Inthis case the turns on the primary are increased.

To help keep the primary and secondary winding losses approximately thesame one should allocate similar area to the primary and secondary windings.If the secondary has more turns, it must have proportionately smaller wire.If there are multiple secondaries, allocate their winding area by output power(higher getting more winding area).

If one is designing an inductor, then the magnetic losses can be traded offagainst the copper losses by adjusting the cross-section of the core. For example,if the magnetic losses are low, then they can be increased by decreasing the corecross-section and therefore increasing the flux density. The total losses in thecore are related to the losses per unit volume, and of course the volume ofthe core. If the cross-sectional area is decreased then the core volume dropsin proportion to the decrease. The flux density increases in proportion to thedecreased area. However, the total losses will increase since the losses per unitvolume are related to the peak flux density squared.

Example 7.1 Assume that the core cross-section of the typical transformer corehas been halved. This will mean that the volume of the core has been halved. Theresult of the area increase, assuming that the mmf is the same and the core isnot saturated, is that the peak flux density will double. The Eddy current lossesper unit volume in the core are proportional to B2, therefore the losses per unitvolume increase by 4. The total losses would therefore by 1/2 × 4 = 2 timesthose before the change in core area.

6Note that in this discussion we are assuming that the losses in the primary due to themagnetising current can be neglected. The losses due to this component of the current actuallyincrease with the reduction in the number of turns of the primary.


7.3.5 Design of an Inductor

In this section we shall proceed through the practical design of an inductor. Thereason for this is that this is the simplest magnetic structure that is useful in aSMPS design. For example, inductors are required in the buck converter for theoutput filter. In the following design we shall be referring to graphs from [2,3],which is a data manual and selection guide for products by Ferroxcube, formerlyPhilips. The specifications for the inductor are shown in Table 7.4.

Parameter Specification

Inductance 35µHDC current 2 AmpMax power dissipation 300mWOperation frequency 250kHzAverage voltage 10V

Table 7.4: Inductor specifications.

From Table 7.4 we need to calculate a few other values that will aid in theselection of a core material. We know from the maximum power dissipationspecification that:

R <Pmax

I2=

300 × 10−3

22= 0.075Ω (7.43)

Remark 7.39 Equation (7.43) does not account for losses in the magnetic ma-terial. Therefore this value is simply an upper bound on the winding resistance.

Let us check to see if we can consider this application to be a DC inductorapplication. The input voltage to the buck converter is 15V and the outputvoltage is 5V. Using (5.3) one can deduce that the duty cycle is 33% or 1/3.The switching period, T , is 4µsec. Using the circuit expression for the voltageacross an inductor we can write:

di =VL dt

L=

10 × 4µsec × 13

35µH= 0.381Amp pk-to-pk (7.44)

Remark 7.40 The di in (7.44) is relatively small compared to the DC currentof 2A, therefore the inductor can be considered to be fulfilling the function of theDC choke.

Remark 7.41 The implication of (7.44) is that the permeability of the mag-netic material should be fairly low to prevent the magnetic system from saturat-ing. The other alternative is that a high permeability core be used with an airgap.

Given that the inductor can be considered a DC power inductor (or a DCchoke) one can consult [2] to find out what magnetic types are suggested forthis application. The relevant table from [2] is shown in Figure 7.15. Thissuggests that the 2P range of iron powder cores are suitable for this application,since the operating frequency is less than 500kHz. One could also choose the


Figure 7.15: Ferrite choice (from [2]).

Figure 7.16: Initial permeability with respect to frequency for 2P iron powderFerroxcube material (from [3]).


Figure 7.17: Incremental permeability as a function of magnetic field strengthfor 2P iron powder Ferroxcube material (from [3]).

3C range of cores – these cores have much higher initial µi compared to the2P range. Since the inductance that we desire is not very high then we canafford to use a low permeability material. Another advantage of this is that onewould not have to consider introducing a air gap to prevent core saturation.Figure 7.16 shows the initial permeability for a selection of different 2P ironpowder materials with respect to frequency of operation. Notice that the relativepermeability of the 2P90 material ia approximately 90 over the frequency rangeof interest. Another important, and related figure, is Figure 7.17, which showsthe incremental permeability of the material versus magnetic field strength. Theincremental permeability is the permeability of the material for small variationsof the magnetic field strength on a DC bias field. This is precisely the situationthat occurs in a filter inductor of the type we are designing.

Given that we have decide to use a 2P type material from Ferroxcube, wefirstly have to make an estimate of the number of turns required to obtain thedesired inductance. An important parameter supplied by the core manufacturersis the AL value. This value is the inductance per turn for a particular core.Therefore, if we assume the initial value of permeability then we can come upwith a first estimate of the number of turns required.

Another important value that we have not considered as yet is the size of thecore we are to use – for any given material there are a number of different coresizes. Factors that influence the core size are the wire diameter and number ofturns required,7 and the maximum flux density that is allowed in the core.

7The combination of the wire size influence the core size to the extent that the core mustbe big enough to physically allow the windings to fit on the core.


7.3.5.1 Key Magnetic Parameters

A few notes on key parameters that appear in the data sheets and selectionguides for magnetics would be opportune at this juncture. The following dis-cussion is based on the parameters described in [3]. Note that we will notdescribe all the parameters in these sheets, but will concentrate on those thatare most useful for the job at hand.

7.3.5.1.1 Initial Permeability This is the relative permeability at verylow magnetic field intensity. It is formally defined as:

µi =1µ0

∆B

∆H(7.45)

where ∆H → 0.

7.3.5.1.2 Effective Permeability This is the effective permeability of thematerial when an air gap has been introduced in the magnetic circuit. Its valueis dependent on the initial permeability of the material and the effective air gap.The expression for the effective permeability is:

µe =µi

1 + µiGle

(7.46)

where:

G the air gap length.

le the effective magnetic circuit length.

This expression is only valid for relatively small air gaps. For larger air gapsfringing effects will raise the value of µe above that calculated by the aboveexpression.

7.3.5.1.3 Amplitude Permeability This is relationship between the fluxdensity and field intensity at high field strengths with the presence of a biasfield. The expression is:

µa =1µ0

B

H(7.47)

Clearly the value of this parameter depends on the applied field strength dueto the non-linear nature of the materials.

7.3.5.1.4 Incremental Permeability This is the small signal permeabilitywhen it is superimposed on a DC biased field. It is formally defined as:

µ∆ =[

1µ0

∆B

∆H

]HDC

(7.48)


7.3.5.1.5 Effective Core Dimensions Many magnetic cores have irregu-lar shapes. In order to allow design calculations on these structures the man-ufacturers supply a set of effective dimensions for the core. These effectivedimensions are the dimensions of the toroidal core that will produce the samemagnetic properties of the original core. The effective dimensions supplied areAe the effective cross-sectional area, le the effective length of the corematerial, and Ve the effective volume of the core.8

Given the above values then the effective reluctance of the core can be writtenas:

Re =le

µAe(7.49)

In many data sheets (e.g. in [3]) (7.49) is usually written as:

Re =1µ

∑(l

A

)(7.50)

where the term∑(

lA

)is known as the core factor. core factor

Using the core factor one can calculate the inductance of the core using thefollowing expression:9

L =Nφ

I=

N2

Re=

µ0N2

1µe

∑(lA

) (7.51)

If the magnetic structure is being driven by a sinusoidal source then it issimple to show that the peak flux density in the core is: peak flux with sinu-

soidal excitation

B =V

NωAe(7.52)

If the driving waveform is a square wave with a peak of V volts, then the peakflux density is given by: peak flux with

square wave excita-tionB =

πV

2NωAe(7.53)

Similarly the peak magnetic field intensity can be worked out using the effectivelength: peak magnetic field

intensityH =

NI

le(7.54)

Remark 7.42 The above calculations assume that Ae is uniform throughout thematerial. However, in many magnetic structures this is not the case. Thereforethe peak flux density is calculated using the minimum cross-section area Amin.Most cores are designed so that Ae ≈ Amin so that there is no significant increaseof flux density due to the physical core design.

7.3.5.1.6 Inductance Factor The inductance factor for a core is the in-ductance of a single turn coil for the particular core. This is related to the

8All the measurements are assumed to be in MKS units.9Note that we are using the expression NI = φRe from magnetic equivalent circuits [16].


magnetic properties of the core – i.e. namely the permeability. The definitionof the inductance factor can be simply obtained from (7.51):

AL =1Re

=µ0µe∑(

lA

) =4π × 10−7µe∑(

lA

) Henry (7.55)

Usually AL is quoted in terms of nH, therefore (7.55) is written as:

AL =1256.7µe∑(

lA

) nH (7.56)

The inductance factor is obviously related to the total inductance by theexpression:

L = N2AL (7.57)

which means that for a given desired inductance the number of turns can easilydetermined by rearranging (7.57) to give:

N =√

L

AL(7.58)

7.3.5.2 Details of Inductor Design

Figure 7.18: Core type selection table (from [3]).

Now that we have reviewed some of the key parameters that are requiredto understand magnetics data sheets we can now return to the design of theinductor.

The material was previously chosen to be Ferroxcube 2P. The next step isto choose a core type and size. We shall use a toroidal or ring core. One can seefrom the table in Figure 7.18 that this is a favourable choice for this application.

Many manufacturers provide tables to aid in the selection of a particularcore. These tables not only allow a first guess at the core selection material,


but also suggest a specific core. This then gives one an initial core size to base adesign on.10 This initial core selection for cores that have a DC current throughthe windings is often based on a graph that uses the energy stored in the core –i.e. 1

2LI2. The L and I terms in this expression are both related to the size ofthe core, L via the core length and area, and the current by size of the area toput the windings in. Figure 7.19 shows the core size data and AL parametersfor Ferroxcube iron powder 2P cores. Unfortunately the Ferroxcube selectionguide does not have such a table for the iron powder cores.

We shall select an initial core from the table in Figure 7.19 and then calculatethe number of turns required. We shall use this, together with the specificationon the power dissipation to work out the amount of area required in the centreof the core for the winding. Depending on the result of this we may have toselect another core. One other criteria for the selection of the core that was notpreviously mentioned was that one would generally want the core to be as smallas possible, since this usually correlates to minimum cost.

Let us arbitrarily choose core TN17/9.8/4.4 2P90 from Figure 7.19. As canbe seen from this figure AL = 42, therefore using (7.58) one can get:

N =

√35 × 10−6

42 × 10−9= 28.9 turns (7.59)

This has to be rounded up to an integer number of turns, so let’s make it 29turns.

The next thing to consider is the amount of wire required for this. Theturns have to be wound around the toroid, so that the copper passes throughits centre. The size of the centre of the toroid places a limit on the number ofturns for any gauge of wire used. Taking into consideration the difficulties ofwinding the core, as well as the amount of space taken by wire insulation, thetypical winding fill factor is 45–50% – i.e. only 45–50% of the available spacefor the winding can practicably be used.

To select the wire we need to consider the amount of current that it has toconduct, and the amount of power that will be dissipated in its resistance. Theskin effect should not be that important in this case since the high frequency ACcurrents are relatively small compared to the DC current flow. A first selectionof the wire can be made from a wire table. We shall use the table printedin [13], which is itself a reprint of a table produced by Magnetics Inc. in theirliterature.11 One candidate size is AWG18 wire, which nominally has a currentcapacity of 2.17 Amp. The resistance of the wire per metre is 0.02096Ω/m, andits wire area (including insulation) is 9.83 × 10−3cm2, or 9.83 × 10−7m2.

Referring to Figure 7.19 we can work out the length that the wire has to goaround the core (approximately) as 19.5mm or 0.0195m. However, this valuedoesn’t take into account the fill factor which effectively extends the length ofeach turn. An approximate expression for the length of a turn for a toroidalcore is [13]:

lt = D + 2H (7.60)

where D and H are as defined in Figure 7.19. Using (7.60) the length of a turnis 0.0181 + 2 × 0.0053 = 0.0287m.

10Often this initial selection may prove to be inadequate in some detail. The designer mayhave to choose a larger or smaller core dependent on the nature of the inadequacy.

11The Magnetics Inc Web site, http://www.mag-inc.com, has a free program that can bedownloaded for the design of filter inductors.


Figure 7.19: Core data for toroidal cores using powdered iron (from [3]).


Using the number of turns calculated in (7.59) we can calculate the resistanceas 29×0.0287×0.02096 = 0.01744Ω. Therefore the power loss in the windings isapproximately I2R = 4×0.01744 = 70mW. This is well within the specificationof less than 300mW total power loss, and leaves 230mW for the core losses.

The other issue to examine is whether the wire can be wound on the core– i.e. will it fit in the hole in the centre. The total wire area, including theinsulation, is 29× 9.83× 10−7 = 2.85× 10−5m2. The total area available in thecentre of the core is πd2/4 = 6.65 × 10−5m2. A fill factor is 0.5, therefore thearea available for the wire is 0.5 × 6.65 × 10−5 = 3.325 × 10−5m2. Therefore itis possible to wind the wire on the core.

Remark 7.43 One must also take into account the thickness of the wire. If wireis too thick then there will be trouble bending it around the core. In addition,the act of bending it around the core may also fracture the core, since ferriteand iron powder materials are very brittle.

We now need to check the core flux density. This can easily be done using(7.51) and the Ae value from Figure 7.19 to give:

B =LI

NAe=

35 × 10−6 × 229 × 15.8 × 10−6

= 152mT (7.61)

Remark 7.44 The maximum flux density is not related to the losses in thissituation, since it is primarily a constant flux density which does not causelosses. However, there is a ripple in the voltage across the inductor, that resultsin a ripple in the inductor current, and consequently an AC component sittingon top of the DC flux density. It is this component of the flux that is relevantto the loss calculations.

Remark 7.45 The DC flux density is important because of the effect that ithas on the permeability of the material.

Figure 7.20: Typical BH characeristic for 2P magnetic material (from [3]).


If we consider the BH characteristic for the 2P materials (from [3]) shownin Figure 7.20 one can see that the flux density level is far below saturation.

Figure 7.21 shows the losses for 2P material at various peak flux densitiesand frequencies. These plots are very difficult to read with any accuracy. Thebest approach is to form an equation for the relevant line on the graph.

Figure 7.21: Losses in 2P material with respect to flux density and frequency(from [3]).

The equation for a line on the graph is of the form:

Pv = aBx (7.62)

where a and x are unknowns to be found. Since we have two unknowns thenwe need two independent equations to find them.12

Considering Figure 7.21 we can write the following two expressions by ex-amining the 200kHz curve:

28 × 103 = a × (4 × 10−3)x (7.63)

800 × 103 = a × (20 × 10−3)x (7.64)

Multiplying (7.63) by (800×103)/(28×103) and equating to (7.64) we can write:

80028

a × (4 × 10−3)x = a × (20 × 10−3)x (7.65)

Cancelling out the common expressions, and taking logarithms of both sides ofthis expression we can write:

log(28.57) + x log(4 × 10−3) = x log(20 × 10−3) (7.66)

which can be solved to give x = 2.0829. We can then subsitute this into either(7.63) or (7.64) to give a = 2.766×109. The resultant equation can be multiplied

12Even using this technique it is difficult to get accurate results since it is hard to read offthe points to develop the simultaneous equations.


by 250/200 = 1.25 to account for the fact that it has been derived for a frequencyof 200kHz (this is a crude extrapolation). Therefore the resultant expression forthe losses is:

Pv = (3.4575 × 109)B2.089 W/m3 (7.67)

at a frequency of 250kHz.13

We are now in a position to calculate the losses. However, before doing thiswe must calculate the AC component of the flux density in the material (asnoted earlier). Recall from (7.44) that the current ripple through the inductoris 0.381 Amp. Therefore the AC magnetic field intensity is:

HAC =NIAC

le=

29 × 0.3810.0402

= 274.85A/m (7.68)

Assuming that the core relative permeability stays at 90 then we can work outthe peak to peak flux density as a result of the ripple current:

BAC = µ0µeHAC = 4π × 10−7 × 90 × 274.85 = 0.031Tesla (7.69)

We can now work out the losses by using the B value from (7.69) in (7.67) to givePv = 2.439e6W/m3. For the volume of material in the core (Ve = 635×10−9m3)the loss is PvVe = 1.54W. This power dissipation is outside the specification forthe inductor by a factor of 5 times. Therefore we must go back to the drawingboard with this design.14

In order to lower the losses in the core we need to go to a larger core size.Let us try the TN24/15/7.5 core. We shall quickly go through the same designprocess as carried out above. In this case the AL = 61nH, and consequently:

N =

√35 × 10−6

61 × 10−9= 23.95 turns (7.70)

Therefore we will make the turns equal to 24.Given the turns we can now work out the maximum AC flux density variation

as:

BAC =LIAC

NAe=

(35 × 10−6)(0.381)(24)(32.8 × 10−6)

= 0.0169 Tesla (7.71)

Substituting this into (7.67) gives Pv = 690, 162 W/m3. Therefore the totalpower dissipation is PT = PvVe = 690, 162 × 1895 × 10−9 = 1.3 Watts. This isless than in the previous case, but is still approximately 4 times the specification.One might suspect that we will have trouble satisfying the specification fromthe small change in the losses for the change in the core. Indeed, if one choosesthe largest core in Figure 7.19, TN33/20/11, we will still have trouble satisfyingthe specification. If this is carried out the core losses are of the order of 0.7Watts, which is still twice the specification.

The question is now what can we do. If we are to stick with the frequencyof operation we need to find a core material with lower core losses. However,

13This expression is only going to give a ball park figure for the losses. To get accuratevalues measurements must be taken.

14The above design closely follows that in [13] which uses a similar permeability and sizecore. However, the resultant losses found in [13] are approximately 1/10th those found above.The Lenk analysis uses a complex mix of units, so I am assuming that there has been an errorin one of the units conversions. I have been unable to find an error in the design calculationsabove.


if the frequency of operation is part of the design mix then we can make thislower. This will also have the effect of increasing the ripple in the current, sothe inductance value would have to be varied to allow this specification to besatisfied.

Let us briefly consider a drop in the frequency to 100kHz. If we want thesame ripple of 0.38 Amp in the 2 Amp DC current then the inductance valuecan be found to be 87µH using (7.44). The turns can nw be found to be 32turns using (7.58) and the value for AL = 87nH (for the TN33/20/11 core).Therefore BAC = 0.012 Tesla using (7.71) with the new values. Reading off theapproximate value for the losses per m3 from Figure 7.21 we can see that it isapproximately Pv = 70W/m3. The core volume is 5200 × 10−9m3, and hencethe total core losses are PT = PvVe = 0.364 Watts. This is still outside theoriginal specification in relation to the losses, but it is much closer than thosecalculated previously. A further improvement can be made in relation to thelosses by lowering the frequency further, but the number of turns required toachieve the higher inductances mean that check would have to be made to seeif there is enough winding area.

Remark 7.46 The fundamental problem with the above design is that the ma-terial chosen has too high a power dissipation per unit volume. The specificationis much easier to satisfy if a lower loss material is chosen. For example, the2P material we chosen has a lose of approximatley 200kW/m3 at 10mT fluxdensity. The 3C material by the same manufacturer has losses so low (of theorder of 1 rightarrow 2 kW/m3) that the manufacturer has not plotted thembelow approximately 10mT. Therefore the specification would have been satisfiedif this, or a similar low loss material had been chosen at the outset. For exam-ple, in [13] the same design is carried out using MPP material manufactured byMagnetics Inc.. This material has a loss of 18.2kW/m3 at 10mT flux density.In this design the core losses turn out to be 140mW.

Remark 7.47 The frequency of operation of this inductor would mean thatLitz wire should probably be used. This would change the wire area calculationsabove. The skin effect at 250kHz needs to be considered. In fact if the frequencyis above 50kHz the skin effect must be considered.

7.3.5.3 Issues in Forward Converter Transformer Design

We shall not go through a complete design of a forward converter transformer,but instead we shall highlight a few of the major issues that need to be con-sidered. We shall do this in the context of the paper design. The following isbased on an example in [13]. The basic design of a forward converter is shownin Figure 6.2.

The input voltage to the forward converter is 48VDC, and the output voltageis 5VDC at 100 Watts. This implies that the output current is Io = 100/5 = 20Amps. This is obviously a very high current, therefore it is important that theresistive losses are kept low for efficiency reasons. This means that the numberof turns on the secondary should be low, and the wire should be a thick gauge.

Let us consider the issues involved in selecting the turns ratio for the trans-former.


7.3.5.3.1 Turns Ratio = 1:1 This would imply that when 48VDC is ap-plied across the primary there is 48VDC across the secondary (ignoring theleakage inductance of the transformer). The problem with this voltage is thatone cannot obtain Schottky diodes above about 45 volt with a low forward volt-age drop. One would require a diode with a voltage rating significant higherthan 48 volt, therefore the forward voltage drop will be high.

Remark 7.48 For high current outputs forward voltage drop is important. Theloss is VfIo, and this is being dissipated in the rectifer diode, or the free-wheelingdiode. One can use synchronous rectifiers to overcome this problem, but thisrequires a significant increase in the complexity of the circuit due to their driveand control requirements.

For the diode loss reason given above the choice of a 1:1 turns ratio is not agood one.

7.3.5.3.2 Turns Ratio = 2:1 The primary has twice the turns of the sec-ondary, meaning that there is 24VDC on the secondary. This means that theduty cycle of the converter is approximately Vout/Vsec = 0.21. The currentthrough the primary of the transformer (assuming that there is a constant 20Amp current in the load) is 0.5 × 20 = 10 Amp. This quite a bit of cur-rent for a MOSFET switch. The losses in the MOSFET are approximately102 ×RDSon × 0.2. These losses may result in an expensive MOSFET, or alter-natively a large heat sink.

7.3.5.3.3 Turns Ratio = 3:1 In this case the secondary voltage is 16 voltand the primary current is approximately 7 Amp. The duty cycle is 0.31.Therefore the losses are 72 × RDSon × 0.31, which is substantially lower thanin the previous case.

7.3.5.3.4 Turns Ratio = 4:1 The secondary voltage in this case is 48V DC/4 =12V DC. Therefore the duty cycle is Vout/Vsec = 5/12 = 0.42. This duty cycleis very close to the limit cycle of many of the popular PWM ICs (which arelimited to duty cycles of 0.45). If there is any variation in the input voltage,and if the diode drops are accounted for, then it is possible for this limit to behit.

The conclusion of the above turns ratio scenarios is that a turns ratio of 3:1is probably the best one to choose.

The remainder of the design of the forward transformer involves the choiceof the core material and the magnetising current. The magnetising current isimportant, since this current does not contribute to the load current, but doescontribute to the losses in the converter. The magnetising inductance is alsoimportant from the point of view of losses in the core. Fortunately, lowering themagnetising current involves increasing the primary turns (whilst maintainingthe 3:1 turns ratio), which in turn also lowers the flux density in the core (fora fixed input voltage). There is a limit to how far this can be taken, since themore turns requires more copper in both the primary and secondary. Hence thisimpacts on the size of the transformer.


7.3.6 Design of Manufacturable Magnetics

Magnetic components are usually custom made in a factory, unlike most otherelectrical components which are mass produced in an automated fashion. Thismeans that when we design some magnetics for a product that will be massproduced we need to take into consideration how easy it is to manufacture, andalso how repeatable the specifications will be in a manufacturing environment.

7.3.6.1 Wire Gauge

The general rule in relation to wire gauge is simple – don’t select wire that istoo thick or too thin.

Practical Issue 7.8 It is best to limit the wire gauges to a maximum of #20(i.e. 7.91 × 10−7m2) and an minimum of approximately #38 (i.e. 0.132 ×10−7m2). For wire gauges thcker than #20 some machine cannot wind thecores, and above #18 there is a risk of fracturing the core as the wire is woundaround it.

Wire gauges thinner that #38 can still be machine wound, but it is difficultto build prototype cores with wire this thin – it is as thin as a human hair.Therefore it is best to use #38 wire even if you can get away with thinner wire.

Another aspect of wire gauge to consider is that one should try and limitthe number of different wire gauges being used. This will allow some volume-of-purchase economies to be obtained.

7.3.6.2 Wire Gauge Ratio

If you are winding different wires onto a magnetic structure, and these arelayered on top of each other, then try and keep the wire gauges close together.This helps prevent the thinner wire from finding its way into the crevices of thethick wire – the different windings do not form nice layers. When this happensit can effect the leakage and coupling of the magnetic circuit.

Practical Issue 7.9 Try to keep the wire gauges in a magnetic structure within10 of each other.

7.3.6.3 Toroidal Core Winding Limits

If a toroid is going to be machine wound then the only limit on the windings isthe size of the winding area and the size of the wire. However, if one is to handwind these cores there is a practical limit set on a human’s ability to concentrateand count.

Practical Issue 7.10 Hand winding a toroidal core is a real pain. If one isgoing to wind a prototype one by hand it is best the keep the number of turnsbelow approximately 200. It is very easy to forget the number of turns on thecore (even for this number).


7.3.6.4 Tape versus Wire Insulation

For safety reasons tape is often used between the primary and secondary wind-ings of a transformer. When there are high voltage differences between theprimary and secondary a flanged bobbin may be used, which divides the wind-ing area into two pieces with a piece of plastic.

In many designs there is substantial voltages between the secondaries. There-fore insulation is required between these to prevent arcing. In the case of highvoltage secondaries there may need to be insulation between the layers of thesame secondary winding.

Practical Issue 7.11 Adding tape insulation layers should be avoided if possi-ble. The tape takes up a lot of area, and even more importantly it usually mustbe put on by hand.

Remark 7.49 In many cases it may be better to go to thicker and higher classwire insulation instead of using tape. It is less labour intensive and can lead toa more compact design.

7.3.6.5 Layering of Windings

The windings should be wound from the left of the bobbin to the right and thenback from the right to the left for each of the layers (except for a toroid).

The windings should take into account where the connection pins are, andshould be designed so that a winding does not terminate half way up the bobbin.If this does happen then one would have to take the end connection to the topor bottom of the bobbin to connect to the end pins. Any other layer will thenhave a lump in it where it goes over the top of this end connection.

Practical Issue 7.12 One should take into account where windings will endwhen selecting the wire gauge. One should ensure that the winding does notterminate in the middle of layer.

The other issue in relation to the windings is the coupling. The windingsshould be bifilar wound in order to maximise the coupling and minimise theleakage inductances if there are no safety considerations. In order to do thisthe wires should be twisted together. This is often carried out with multiplesecondary windings to improve the cross-regulation.

The primary and secondary windings should be interleaved if possible. Thisenhances the inter-winding coupling from primary to secondary, and also helpsin relation to cross-regulation with respect to multiple secondary windings. Fig-ure 7.22 shows the basic structure of an interleaved winding transformer that hasalso been designed to achieve good isolation between the primary and secondarywindings.

7.3.6.6 Number of Windings

Magnetic coupling issues limit the number of windings that can be practicallywound on a core. In addition the layering becomes more difficult. Finally, mostwinding bobbins only have 8 to 12 pins available for the end connections.

Practical Issue 7.13 Most magnetic designs should be limited to a maximumof four to six windings.


High dielectric sleeving

Mylar tape

Bobbin

Secondarywinding

Primarywinding

Primarywinding

Figure 7.22: Winding interleaving for high-dielectric isolation and good primaryto secondary coupling.

7.3.6.7 Potting

Potting is the process of filling up a volume surrounding a magnetic structurewith a thermally conductiove compound for the purpose of improving heat re-moval by providing a better thermal path. It also strengthens the structure,and prevents the incursion of environment factors that may affect the life ofthe magnetic structure. The potting can also be utilised to provide mechanicalmounting points for the structure.

There can be some problems with potting – it makes the unit heavier, theshrinkage of the potting mix as it cures can result in changes to air gaps ingapped cores, and some magnetic materials (e.g. MPP) are strain sensitive,and their permeability can change as the potting shrinks.

7.3.6.8 Safety Requirements

If one has high voltage and low voltage windings wound on the same core then itis important from a safety perspective to ensure that the high voltages can neverget to the low voltage windings. Figure 7.23 shows a transformer design whichsatisfies requirements for isolation. There is a 2mm creepage distance from theend of the insulation tape to ensure that the windings can never come intocontact. In addition, leads that pass through other windings must have a highvoltage insulation rating. The windings are insulated from the core material.All these requirements take up space, therefore a transformer satisfying theserequirements will be larger.


Core

Creepage distance (4mm)

Insulating tape

High voltage sleeving

Insulation layer

PrimarySecondary

Figure 7.23: A transformer design to satisfy safety requirements.


Part III

Line CommutatedConverters and High Power

Inverters

Chapter 8

Introduction to High PowerConverter Technology

8.1 Introduction

This part of the course is an overview of power electronics that is focussed onhigh power applications. The previous two parts of the course were primarilyconcentrating on very low power digital switching, and small to medium powerswitching primarily related to dc-dc power supplies.

The term high power is not a precise term, and the distinction betweenswitch mode power supplies and some of the circuits in the following chaptersare blurred. It will be assumed that the circuits in the following chapters areused for power levels greater than 1.5 to 2kW, with the top power levels be-ing open ended. For example, the power electronics used in high voltage dcpower transmission can be handling many hundreds and possible thousands ofmegawatts. The other feature that distinguishes many of the circuits in thehigher power area are that they rely on natural commutation to turn off thepower devices – this means that they cannot be explicitly turned off using agate signal, but rely in certain external circuit conditions to cause them to turnoff.

The subject material for a course on this topic is huge, and more thanenough to fill an entire course in its own right. Therefore we shall be lookingbriefly at a subset of the possible topics, concentrating on the fundamentalconverter types and operational principles. Specifically we shall look at thepower devices that are used in the high power area, since they have a largeinfluence on the circuits, topologies and applications. The next major part ison the line frequency uncontrolled and phase controlled rectifiers and inverters.Next we look at hard switched dc-ac inverter technologies. The final part willconsider the application of these devices in electric machine drive systems. Thereare many references for this work, but the primary ones used for this courseare [4, 11,17,18].

278 Introduction to High Power Converter Technology

8.1.1 Applications of Power Converter Technology

Power electronics is becoming increasingly important in the modern world. Theability to control and transform power to forms suitable for particular appli-cations is fundamental for the operation of any technological society. The in-creasing emphasis on efficiency is spawning even more activity in the PowerElectronics area, as new techniques are needed to minimise the production ofgreen house gases. The developments in the power semiconductor area are al-lowing the application of power electronics in areas that, only a few years ago,were impossible.

Examples of modern applications of power electronic converter systems are:

• Electric vehicle propulsion systems. These systems are one of the veryhigh profile applications of modern power electronics. They incorporateinnovative electrical machines coupled with inverter, computer and bat-tery/generator technologies.

• Electronic washing machines. A current example of is the Fisher-PaykellSmartdrive washing machine, which utilises a direct drive 48 pole perma-nent magnet motor driven by a computer controlled inverter. The MaytagNeptune washing machine in the US uses an electronically controlledswitch reluctance machine.

• Photovoltaic (PV) grid interfaces. In order to convert the power producedby photovoltaics into a form suitable for domestic use or to export intothe grid, power electronic conversion is required. The application of clevercontrol techniques can optimise the amount of power that can be suppliedfor given illumination levels.

• High voltage dc transmission (HVDC) systems. These systems allow largeamounts of power to be transferred in undersea cables. For example, thepower connection between the north and south islands of New Zealanduse a HVDC link. Similarly for connections from Norway and mainlandEurope. HVDC links are also used to isolated the dynamics of large powersupply systems. For example a HVDC link is used for the NSW to Queens-land interconnection so that there is not interaction between the two dif-ferent grid systems.

• Frequency wild wind and hydro power applications. Conventional windturbines rotate at a constant speed regardless of the wind speed. In orderto extract maximum energy from the wind variable pitch blades are used.However, if the turbine is allowed to vary in speed (without the complexvariable pitch bladed) then it is possible to extract even more energy fromthe wind. By interposing an inverter system between the generator andthe grid supply, it is possible to do this, since the inverter converts thefrequency wild input into the grid frequency output. The same issuesapply to hydro turbines.

• Power system static VAR compensators. These are power electronic de-vices that are able to supply the VARs required for inductive loads onpower systems. They are commonly used to improve power factor and toaid in the stability of the power system.

8.2 Review of Power Semiconductor Devices 279

• Active filters. Modern power electronic devices on the power supply gridcan generate harmonics into the grid supply. These can cause problemswith other devices connected onto the grid. An active filter is anotherpower electronic device that is capable of cancelling out the harmonicsproduced by these other devices.

• Flywheel and superconductor energy storage. These two storage tech-niques will possibly be important in future energy systems. Power Elec-tronics plays a pivotal role in the operation of these systems, as it isrequired in order to get energy into and out of the energy storage system.

• Aerospace power systems. Power electronics, because of the weight sav-ings, play an important role in the power systems for both aircraft (civilianand military) and space systems. These applications of power electronicstend to be the leading edge of the technology.

• Uninterruptible power supplies (UPS). These are power electronic systemsthat allow battery systems to be used as power backup for mains operatedsystems in critical applications.

• Load proportional modulated air conditioning systems. Instead of turn-ing air conditioning compressors on and off to maintain a desired averagetemperature, and inverter driven compressor motor provides variable con-tinuous output. The saving are due to the fact that the compressor outputdoes not match the energy input for a considerable time after the com-pressor is first started. Energy savings up to 30% are achievable using thistechnique.

• Electronic fluorescent lamp ballast. These ballasts are based purely ona high frequency inverter of some type (no magnetic components). Theyoffer energy savings over magnetic ballasts. Furthermore, external lightcompensation can also be incorporated into the design.

The above examples are only a selection of the industrial and residentialapplications of power electronics. This technology is not always obvious to theuser, but is being incorporated into a larger variety of products. Therefore anunderstanding of at least the basics of the technology is essential for the modernelectrical engineer.

8.2 Review of Power Semiconductor Devices

At this point it is beneficial to review the current state of semiconductor devicesused for high power applications. This is required because the operation of manypower electronic circuits is intimately tied to the behaviour of various devices.

8.2.1 Diodes

Figure 8.2 shows the basic conceptual diagram for a diode. This diagram isvalid for a general purpose diode, but power diodes have a different structure inorder to improve the voltage blocking capability of the device and at the sametime keep the on-state resistance as low as possible.


The iv characteristics of conventional and power diodes are much the same,and a generic diagram is shown in Figure 8.1. Note the offset voltage of ap-proximately 1 volt. It is this voltage that leads to the majority of the powerdissipation. Also note the slope on the characteristic as the voltage across thedevice increases above 1 volt – this represents the effects of the bulk resistanceof the device. Whilst the 1 volt offset is virtually intrinsic in the operation of thediode, the bulk resistance contribution to the power losses can be minimised bychanging the doping of the semiconductor materials. The breakdown voltage,vBD, is a very important parameter in power diodes. Much of the design ofthese diodes is related to improving vBD.

1V

vBD

iD

vD

Figure 8.1: The current-voltage characteristic of a diode.

Figure 8.3 shows the conceptual structure of a power diode. Note that themain difference between this structure and that of Figure 8.2 is that there isa n− region interleaved between the normal p+ and n+ regions. This regionis known as the drift region, and under reverse bias is the region where thedepletion region lies.

At first the presence of the n− region in the device would seem to be alittle silly, since it must add to the bulk resistance of the device. Under certaincircumstances this is indeed true, but by careful control of the doping profilesthis effect can be minimised. This region is in the device to improve the voltageblocking capability. We shall not look at the equations that prove this, butheuristically the reason is that if one supports a voltage over a longer distance,then the volts per metre must be smaller than if the voltage is supported overa shorter distance. Therefore, when the device is in reverse bias, the depletionregion almost exists entirely in the n− region1, and consequently the electricfield in the semiconductor material is lowered because of its length.

As mentioned previously the problem with having the n− region would ap-pear to be that the bulk resistance of the diode would appear to increase. This

1The depletion region supports the reverse voltage.


pn

Anode

Anode Cathode

Cathode

Figure 8.2: Conceptual structure of a conventional diode.

pn n

Anode

Anode Cathode

Cathode

Wd

Drift Region

vD

+ -

iD

Forward biasvoltage andcurrentdirections

Figure 8.3: Conceptual structure of a power diode.


is true depending on how the diode is designed. There are two forms of structurein Figure 8.3:

1. The non-punch through diode.

2. The punch through diode.

The non-punch through diode refers to a diode where the depletion region liesnon-punch throughdiode entirely in the n− region under reverse bias. Therefore the depletion region does

not punch through the n− region. Other the other hand the punch through diodehas a the n− region a little narrower and more lightly doped. This structuralchange has two effects:

1. The same length n− region can support a larger reverse voltage.

2. The bulk resistance of the device is lower than that of a non-punch throughdiode.

punch throughdiode We shall not concentrate on the former effect, suffice to say that his is

achieved by keeping the peak electric field intensity lower in the device [4]. Thelower bulk resistance is achieved because of a conductivity modulation effect,this occurring because there is injection of carriers into the n− material not onlyfrom the p+ material, but also from the n+ material during forward bias. Theseextra carriers create in the n− region lower the bulk resistance of the region inforward bias.

The other important property of diodes, and especially power diodes, isthe reverse recovery. This refers to an effect when the diode can conduct areverse recoveryreverse current for a small period of time under reverse bias, after it has beenforward biased. This effect is due to stored minority carriers that accumulatein the device under forward bias conditions. These carriers must be removedbefore the device can block voltage, and it is the removal of these carriers thatconstitutes the reverse recovery current.

Figure 8.4 shows a typical reverse recovery characteristic of a diode. Initiallythe diode is forward biased and carries a forward current (i.e. anode to cathode).However as the current goes to zero it continues to flow in the reverse directionthrough the diode as the charge is removed from the device. Eventually all theminority carriers are removed, and the current then starts to decrease as thereverse voltage rises across the device. During this phase the depletion regionsare being established. Eventually all the charge has been removed and the diodethen stops conducting and it supports the full reverse voltage. The shaded arearepresents the total stored charge removed from the device.

Remark 8.1 Charge storage and the associated reverse recovery has importantpractical consequences in power electronic circuits.

Alterations can be made to the semiconductor additives in power diodesin order to minimise the reverse recovery time. These diodes are known asfast recovery diodes. The recovery time of a normal diode can be 4 to 6µsecs,fast recoverywhereas a fast recovery power diode can have a recovery time of 1 to 2µsecs.Unfortunately fast recovery diodes have a relatively large forward voltage drop(≈ 1.5 volt).

The other main type of diode that is used in power electronic applications isthe Schottky diode. Because this diode uses a metal-semiconductor junction as


iD

t

Qrr

Charge storageremoval

Depletion regionformation

Diode begins tosupport reverse

voltage

trr

Reverse recovery time

Figure 8.4: Typical reverse recovery characteristic for a diode.

the basis for the diode it does not have a charge storage problem. Furthermore,the forward turn-on voltage of the device is much lower than a conventionaldiode – of the order of 0.2 to 0.3 volt. One is tempted to ask the question “whyaren’t Schottky diodes used everywhere in power electronics?”. The answerto this is that the Schottky diode cannot support large reverse voltages, andtherefore is only suitable for low voltage applications (up to approximately 100volt).

8.2.2 Thyristors

The thyristor, or silicon controlled rectifier (SCR) is essentially a controlledturn-on diode in terms of its external characteristics. They are the oldest of thesemiconductor power electronic switches (invented in 1957 at General Electricresearch labs), but nevertheless, because of their characteristics, they will havecontinuing application in power electronics. They also have the highest powerrating out of all the power electronic devices.

Figure 8.5 is a conceptual diagram of a thyristor’s structure and its circuitsymbol. Notice that the device is a three terminal structure, with the additionof a gate terminal. This diagram also shows that the device is a three junctionstructure, consisting of what appears to be two diodes in series. It should benoted that this linear semiconductor diagram is not really representative of howthe device is physically laid out in silicon.

To understand how the device works one can develop the approximate model


p1 n

1

( )n

p2

n2

( )n

Anode Cathode

Gate

iA i

K

iG

J1

J2

J3

Anode CathodeGate

Figure 8.5: Conceptual diagram of a thyristor.

for the device shown in Figure 8.6. This diagram shows that the thyristorconsists of a feedback structure consisting of a PNP and an NPN transistor.From ones knowledge of the behaviour of the transistor one can see that if acurrent is fed into the gate (terminal G) then transistor Q2 will turn on. Thiswill result in the PNP transistor, Q1 turning on. Because the collector of Q1is connected to the base of Q2, the current from Q1 forms the base current forQ2. If the current gain around the loop of the two transistors is greater thanone then the initial turn gate current can be removed and the device will remainon.

Anode

Cathode

GateJ

3

J2

J1

iG

iK i

E2

i iA E,

1

iC 2

iB1

iB2

iC1

Q1

Q2

Figure 8.6: Transistor model of the thyristor.

Under blocking conditions one wants the gain around the loop consistingof the two transistors to be less than one. This corresponds to α1 + α2 beingsmall (which means that the transistor current gain product β1β2 < 1), whereα1,2 = iC1,2/iE1,2, . This is the normal state of the transistor.

The thyristor is turned on by changing the effective α’s for the two transis-tors. This is achieved by changing the depletion region across the J2 junction,


which effective modulates the width of the bases of the two transistors. There-fore as a larger positive voltage is applied at the anode with respect to thecathode, the depletion region grows. Eventually the α’s will get to a pointwhere the leakage currents across the junctions are enough to supply a currentwhich will begin the regenerative process. This will cause the thyristor to turnon without any gate current. The voltage that has to be applied across thedevice to cause this to happen is known as the forward break over voltage. forward break over

voltageIf a gate current is applied it is possible to cause the device to enter thepositive feedback region prior to the forward break over voltage. The gatecurrent causes carriers to be injected across J3 and diffuse to the depletionregion at J2. Here they are swept by the electric field of the depletion regioninto n1. The result is that the depletion region at J2 widens to account for theminority carriers injected. This is due to the fact that more donor atoms haveto be uncovered to account for the electrons injected from p2. The net resultis that the effective bases of the two transistors narrow, and consequently theα’s increase. Once these reach the critical value then the positive feedback willagain occur and the device will latch on. The main point to note is that thegate current has achieved this at a lower voltage than the break over voltage. Ifthe gate current is higher, then the lower the forward voltage can be when thedevice will latch on.

The above discussion is captured in the iv characteristic of a generic thyristorshown in Figure 8.6. There are several points to note about this characteristic.If the gate current is zero, and a forward voltage is applied, then if the voltagereaches the level of vBO the thyristor begins to conduct. This is known as thebreak-over voltage. Once the device begins to conduct, the voltage across thedevice falls to a low level dependent on where the load line crosses the forwardcharacteristic.

Similarly if the thyristor is reverse to a level of vRWM , the maximum reverseworking voltage, then the device will begin to conduct (as will a diode if reversebreakdown occurs). The vRWM voltage usually has about the same magnitudeas the vBO voltage (by design).

The most interesting aspect of the thyristor characteristic is the fact thatthe effective vBO voltage can be lowered by the application of a gate current.It is this fact that makes the thyristor behave as a switch. Once the device has“broken over” the device enters a negative resistance region prior to entering theforward on-state region. For the device to enter the forward on-state conditiona minimum current, iH , must be flowing through the device. This is knownas the holding current. If this current cannot be sustained then the device will holding currentre-enter the forward blocking state.

Remark 8.2 Thyristors are still the device of choice for very high power ap-plications. They are capable of withstanding very high voltages (of the order of6-7kV) and can conduct currents in the range of 2-3kA.

Remark 8.3 Another important characteristic of the thyristor is that the gatecurrent does not have to be maintained after the current through the devicereaches the holding current. However, on the downside, the gate current cannotbe used to turn the device off. The device can only be turned off if the externalcircuit conditions allow the current in the device to fall below the holding current.


vAK

iA

iH

iBO

vH

vBO

iG

0

Forward on-state

vRWM

Forward blockingstate

Increasing iG

Figure 8.7: Typical characteristic of a thyristor.

There are two external aspects of the transient performance of these devicesthat are practically very important – the turn-on and turn-off limitations.

8.2.2.1 Turn-on Transient

Figure 8.8 shows a typical turn-on transient for a thyristor. There are severalpoints that can be made about this diagram. After the gate pulse is appliedthere is a delay before the thyristor turns on (td). This is due to the time thatit takes the minority carriers to build up in the p2 material shown in Figure 8.5.After td the device starts to enter positive feedback and begins to turn on. Thecurrent in the device builds up with a slope of diA/dt, this being determined bythe voltage and the external circuit inductance. Notice that during this periodthe voltage across the device is starting to fall quite rapidly, but there is stilla substantial voltage across the device. Consequently there can be substantialpower dissipation in the device during this phase. After the rise time period hasfinished there is a further period of voltage drop across the device known as thespreading time, ts. This is the time required for the current density to becomeeven across the device cross-section.

The diA/dt time is important, since if a maximum value is exceeded thedevice can be damaged. This damage occurs because there is uneven currentdistribution in the thyristor during turn on, and if the current is increasing tooquickly hot spots may develop in the device (because there is not enough timefor the current to spread adequately over the cross-section of the device).


iG

t

iA

vAK

t

t

di

dtA

td

tr ts

IA

Figure 8.8: Typical turn-on waveforms for a thyristor.


8.2.2.2 Turn-off Transient

To turn-off a thyristor it must be reverse biased by actions of the external circuitfor a minimum period of time. In general this minimum time is considerablylonger than the turn-on time.

Figure 8.9 shows a typical turn-off transient. The current decreases at a rateof diR/dt, this rate being determined by the external circuit. As with a diode,the stored minority carriers in the four regions of device result in current flowingin a reverse direction through it. The voltage across the device remains positiveuntil either the junction J1 or J3 become reverse biased. Usually J3 becomesreverse biased first, this occurring at time t2 in Figure 8.9. At this point thevoltage across the device starts to have a reverse voltage across it.

The J3 junction cannot support a very large reverse voltage (20-30 volt) dueto the high doping levels in the n2 and p2 junctions. Therefore this junctiongoes into avalanche breakdown. However shortly after the t2 the J1 junctionstarts to become reverse biased, and at this point the current through the devicestarts to decrease.

t

t

t1

t3

Turn - off time tq

vAK

iA

irr

t2

vREV

dv

dtF

di

dtR

irr4

trr

Figure 8.9: Typical thyristor turn-off waveforms.


The large reverse over-voltage is due to the effects of external inductancesin the circuit. As the current through the device becomes zero, then the reversevoltage across the device becomes the steady state reverse voltage as imposedby the external circuit.

In power diodes when the reverse recovery current reaches some nominalvalue of irr/4, then the device was said to have turned off. However, in thecase of the thyristor there is still a substantial number of minority carriers inthe interior n1 and p2 regions. If a forward voltage is then applied to thedevice at a rate of change of dvF /dt then a forward current can again occuras these carriers recombine and are swept through the device by the growingforward fields in the device. This current can produce an effect similar to thereapplication of a gate pulse, and the device can once again turn on.

In order to prevent the device from turning on with the application of aforward voltage the following precautions must be taken:

1. If the device has been forward biased then it must be held in reverse biasfor a minimum time of tq, a time specified by the manufacturer. This timeis at least several minority carrier line times long.

2. The rate of change of the reapplied voltage, dvF /dt, must be kept belowa certain value specified by the manufacturer.

Remark 8.4 The maximum dvF /dt for slow thyristors is of the order of 100V/µsec.For devices intended for high frequency operation the dvF /dt is of the order ofseveral thousand volts per µsec.

8.2.3 Gate Turn-off Thyristors

The Gate Turn-off Thyristor (GTO) is essentially a thyristor that can be turnedoff by the application of a negative gate current. This makes the usage of theGTO in dc supply situations much simpler, as compared to the thyristor.2 Thereare significant internal structure changes made to the thyristor in order to makeit behave as a GTO. We shall not consider these in detail in this course.

The GTO works essentially the same as the thyristor. Therefore we shallconcentrate on the mechanism that effects the turn-off. If one considers Fig-ure 8.6 it can be seen that:

iB2 = α1iA − i′G (8.1)

where i′G is the negative of the normal gate current. From Figure 8.6 it is clearthat by increasing i′G one can bring Q2 out of saturation.

The collector current for the Q2 transistor, iC2, is given by:

iC2 = (1 − α1)iA (8.2)

using KCL at Q1.In order for the structure to turn off we need the following so that Q2 can

no longer supply the necessary current to keep the total loop gain greater thanone:

iB2 <iC2

β2(8.3)

2If a thyristor is used in a dc supply application it must be turned off using a forcedcommutation technique. These techniques will be considered in a later section.


where β2 = α2/(1 − α2). Using (8.1), (8.2) and (8.3) one can develop thatfollowing expression:

i′G >iA

βt off(8.4)

where the parameter βt off is the turn off gain given by:

βt off =α2

α1 + α2 − 1(8.5)

Remark 8.5 From (8.4) one can see that the βt off value should be as large aspossible to keep the i′G value as small as possible. This implies that α2 → 1and α1 should be small. Therefore the semiconductor regions in the GTO aredesigned to achieve this objective.

8.2.3.1 Snubbers and GTO Thyristors

Consider the circuit shown in Figure 8.10. This is a step down converter using aGTO and the switching element. There are several points that should be notedabout this diagram:

• The circuit symbol for the GTO (as compared to that of the thyristor).

• The Ls on inductor and associated parallel resistor and diode form a turn-on snubber3 circuit.

• The Cs off capacitor,associated resistor Rs off, and diode Ds off, form aturn-off snubber circuit. The Lσ inductance is an unwanted parasiticinductance.

turn-on snubberThe turn-on snubber is required to protect the GTO from the large currents

that can flow through it because of the reverse recovery of the freewheelingdiode Dfw, which is usually a slow device at the power levels that GTOs areused at. The presence of the series inductance Ls on limits that rate of rise ofthe current through the GTO. The resistor and diode components that are inparallel with Ls on are to dissipate the energy stored in Ls on when the GTOis turned off. These should be designed so that the energy in the inductor isdissipated before the next turn on of the GTO.

When the GTO is turned off the voltage across the device would go toVd almost instantaneously without the presence of a turn-off snubber. If thedv/dt across the device is too large then it will turn on, as was the case for thethyristor. The purpose of the snubber is to ensure that this cannot occur, sincethe voltage across Cs off cannot change instantaneously.

Remark 8.6 The use of a turn-off snubber with the GTO is absolutely essen-turn-off snubbertial. If the device is turned on prior to all the internal stored charge beingdissipated, then there is a very poor distribution of the turn-on current, result-ing in local heating and possible destruction of the device. This occurs becauseof the particular internal construction of the GTO. The presence of the turn-offsnubber prevents the “automatic” re-turn-on of the device when the voltage risesacross it too quickly.

3A snubber circuit is an auxiliary circuit that is designed to protect the main switchingelement from excessive current or voltages.


+

+

iL

Dfw

Ls_on

Vd

Cd L

Rs_off

Ds_off

Cs_off

GTO

Rs_on

Ds_on

Turn-on snubber

Turn-off snubber

Parasiticinductance

Load current

Figure 8.10: An example of a dc chopper circuit using a GTO thyristor


8.2.3.2 GTO Turn-on

We shall briefly look at what is required to turn on a GTO. Consider Figure 8.11.The turn-on is instigated by a pulse of gate current. The diG/dt and the peak iGshould be large so that the device turns on rapidly and the current distributedevenly in the device. The gate pulse should last of the order of 10µ secondsor so to ensure that the turn-on process is complete. After this period a smallgate current should be maintained to ensure that the device does not turn offagain under low anode current conditions.4 This current is often known as the“backporch” current.

t

t

t

t

vGK

vAK

iA

iG

iGT

“Backporch” current

td

tw1

0

0

0

0

Figure 8.11: Turn on waveforms for a GTO thyristor.

The other point to note in Figure 8.11 is the effect of the series inductanceLs on on the anode current during turn-on. Notice that diA/dt is limited by

4This unwanted turn-off condition could also damage the device due to uneven distributionof the current in the device if there is a sudden increase in anode current.


this inductance so that the current is distribute evenly across the device, andthe voltage across the device is shared with the inductor during turn-on. Thisinductor also stops the otherwise large reverse recovery currents in the circuit.The reverse recovery actually results in the current overshoot represented bythe overshoot during turn-on.

8.2.3.3 GTO Turn-off

Next we briefly consider the turn-off waveforms for the GTO. It should be notedthat the effect of the snubbers cannot be ignored for the GTO, since it is essentialthat they are used under normal operation (as mentioned in Remark 8.6).

In order to turn the GTO off then the gate current must be negative. Themagnitude of this current is approximately 1/5 to 1/3 of the anode current beingturned off. Therefore in high power applications this current can be substantialin magnitude. Fortunately the duration of the current is short.

Figure 8.12 shows the waveforms during turn-off. The negative diG/dt shouldbe kept as large, but it should not be made too large or undesirable tail currentsoccur in the anode current, and there is the possibility of device destruction.Therefore the diG/dt should be kept within the specifications supplied by thedevice manufacturer. The diG/dt value can be controlled by the design of theinductance in the gate drive circuit and the negative voltage applied to turn-offthe device.

During the time interval t1, the growing negative gate current is removingcharge stored in the two regions of the device. When enough of this is removedthe regenerative action is stopped, and the device starts to turn-off (i.e. theanode current begins to fall). The growing difference between the anode currentand the constant load current io flows into the snubber capacitor. There is arapid rise of the voltage across the GTO due to the parasitic inductance of thesnubber circuitry (this stray inductance has to be kept to the absolute minimumto kept this voltage small). After time t2 enough carriers have been swept out ofthe device for the gate-cathode junction to regain its reverse blocking capability.

As the gate-cathode junction recovers it reverse blocking capability, the volt-age across it starts to go negative, and the negative gate current starts to de-crease. The inductance in the gate circuit tries to keep the gate current constant,and this results in avalanche breakdown of the gate-cathode junction during thetime t3 – i.e. the gate-cathode junction is operating as a zener diode. Thisbreakdown serves to remove further minority charge from the device. The t3interval should be kept below a manufacturer specified value to prevent destruc-tion of the gate-cathode junction.

After the t3 period there is a continuation of anode current flow as the finalstored charge is removed from the device. This is known as the anode tailcurrent, and flows for time ttail. During this time the voltage across the deviceis growing at the rate of:

dvAK

dt≈ io

Cs(8.6)

and contributes a lot to the turn-off losses in the device.GTO minimum onand off timesRemark 8.7 A GTO should not be turned on too soon after it has been turned

off because of the potential for poor current sharing in the device due to residualcharge storage. The same applies for turn-off after turn-on.


t

t

t

t

vGK

vAK

iA

iG

0

0

0

0

iGT

io

t1

t2

t3

t4

ttail

dv

dt

dv

dt

max

vGG

Vd

Inductive spike due to parasitic inthe snubber circuit.

L

Figure 8.12: Turn-off waveforms for a GTO thyristor.


turn-off failureunder short circuitconditions

Remark 8.8 If the anode current becomes too large there is the possibility thatthe gate current may not be able to turn the device off (there is a limit to themagnitude of the gate current, determined by the semiconductor properties ofthe device). This is a particular problem under short circuit conditions, sincethis is an abnormal condition that would not be designed for.

Remark 8.9 Over-current protection can be achieved by using a “crowbar” toblow the fuse in the circuit if the current becomes too large. This concept isshown in Figure 8.13. The SCR across the dc link is fired, resulting in a shortcircuit on the link, and consequently the fuse will blow and protect the circuit. Ifthe GTOs are used in an inverter structure then all the devices in the invertercan be fired simultaneously to carry out the same function.

It should be noted that in Figure 8.13 we have not included the turn-onsnubber. It is this snubber that gives the SCR the extra time to turn-on prior tothe GTO destroying itself.

Remark 8.10 One problem with the crowbar protection technique is that thepresence of a fuse in the dc link introduces inductance in this part of the circuit.This can result in significant over-voltages when the main GTO is turned off.

Load

Short circuit

Fuse

Crowbar SCR

Figure 8.13: GTO thyristor circuit with additional “crowbar” SCR

Remark 8.11 There are several variants to the classical GTO that are be-ing championed by different manufacturers. For example, Asea-Brown-Boveri(ABB) has the IGCT - the Integrated Gate Commutated Thyristor. This is es-sentially a modified GTO with tightly coupled gate drive circuitry built onto acard with the GTO power device. It is a high power device – 4.5kV and 3kA. Theonboard GTO has low conduction losses and does not require a turn-off snubber.The better gating allows higher switching frequencies as compared to standardGTOs (of the order of 1000Hz). Rockwell/Allen-Bradley have a similar devicecalled the SGCT – the Symmetrical Gate Commutated Thyristor.


8.2.4 Insulated Gate Bipolar Transistors (IGBTs)

One of the more recent devices that has become pervasive in the lower to mediumpower area is the IGBT – the Insulated Gate Bipolar Transistor. This deviceis essentially a specialise MOSFET – in fact the input is a MOSFET input.The main advantage of these devices is that they can be easily turned off bycontrolling the devices gate, but unlike the GTO this turn-off process does notrequire large currents.

The basic structure of the n-channel IGBT5 is shown in Figure 8.14. Onecan see that the structure of the device is nearly identical to the MOSFET,the only major difference being the presence of the p+ injection layer. It is thepresence of this layer that results in the injection of minority carriers into thedevice, and leads to the operation of the device being something like a MOSFETfed bipolar transistor. The advantages of the device are:

• The result of the injection of minority carriers in the device is that it cancarry much larger currents as compared to the MOSFET, since the currentis carried in more than the channel of the device.

• The presence of a lengthy diode junction in the device allows it to have asignificantly larger forward blocking voltage as compared to the MOSFET.

• The injection of carriers into the device means that the on-state losses forthis device are lower than those of a comparable power MOSFET.

Remark 8.12 One could consider the IGBT to be a “super” MOSFET. Inmany IGBTs the MOSFET part of the device carries the majority (up to 90%)of the current in the device (this is to help prevent a large amount of minoritycarrier storage from occurring, which slows down the turn-off of the device).

The n+ layer between the p+ drain layer and the n− drift region is notessential for the operation of the device. As with the diode considered earlier,one can have punch-through and non-punch-through IGBTs. The n+ layer isrequired for the punch-through devices to prevent the J2 space charge regionfrom going all the way to the p+ drain region. The presence of the n+ layer cansignificantly improve the operation of the IGBT.

Remark 8.13 In Figure 8.14 there is a parasitic SCR shown. This is an unde-sirable feature of the structure, and design efforts must be made to ensure thatthe loop gain of the SCR is not greater than one so it does not turn on.

The circuit symbol for the IGBT appears in Figure 8.15(c) and (d). Note thatthe symbol in (c) is very nearly the same as that for the n-channel MOSFET,except that there is an arrow on the drain connection indicating the direction ofthe current due to the injection of carriers here. Figure 8.15(d) shows a symbolthat is emphasising the similarity of IGBT with the NPN bipolar transistor.

8.2.4.1 IGBT Operation

We shall briefly consider the salient points of IGBT operation. The followingdiscussion is with reference to Figure 8.16.

5The layer types are all reversed for a p-channel device


SiO2

SiO2

n n

p

n

n

p

Source Gate

Drain

Ls

J1

J2

J1

Bodyregion

Drain driftregion

Bufferlayer

Injectinglayer

ParasiticSCR

Figure 8.14: A schematic diagram of the basic structure of the IGBT.

Figure 8.16(a) shows the current flows in the device when it is turned on.When the gate voltage exceeds the threshold voltage an inversion layer formsbeneath the gate of the IGBT. This channel shorts the n+ to the n− layer, asoccurs in the MOSFET. The current flow through this channel also results inholes being injected from the p+ region into the n− region. These holes moveacross the n− drift region via drift and diffusion via a number of paths. Thesecarriers reach the p body region (not necessarily where the channel is) and thenare swept through to the source via recombination at the source metallisation.

The junction of the n− region and the p region is called the collector region,since is operates the same as the collector region in a thick PNP transistor.The connection between the layers and parasitic transistors is shown in Fig-ure 8.16(b). Notice that the injection layer, denoted as the p+ layer, acts as anemitter in a BJT transistor, emitting or injecting holes into the n− base regionof the device.

As current flow through the IGBT there are voltage drops in the device dueto the bulk resistance of the semiconductor materials used. These are shown inFigure 8.16 as dashed resistors. These resistance values are important for twodifferent reasons; (i) if the resistances are too high then the device will dissipatemore power; and (ii) if the voltage drops are too high in the resistances thenparasitic thyristor in the IGBT may turn on.

Figure 8.17(a) and (b) shown an equivalent circuit for the IGBT. Figure 8.17(b)is more complete, showing the parasitic thyristor, and the body spreading re-sistance. If the body spreading resistance is too high then the current gain ofthe thyristor may become greater than one, and consequently the thyristor willturn on. Once this happens then the device no longer behaves as an IGBT, andpower must be remove across the device to turn it off. Needless to say, muchdesign effort has gone into ensuring that the parasitic IGBT does not turn on.


vDS

iD

vRM

vDS

brk

Increasing vGS

0 7. V

vGSv

GS th

iD

Drain

Source

Gate

Drain

Source

Gate

(a)

(b)(c) (d)

Figure 8.15: The IGBT voltage and current transfer characteristics and circuitsymbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) n-channel IGBT circuit symbols.


8.2.4.2 IGBT Turn-on

Typical turn-on waveforms for the IGBT are shown in Figure 8.18. Thesewaveforms are very similar to those for a power MOSFET.6

We are assuming that the voltage to the input of the IGBT circuit is thevoltage waveform vGG. The voltage across the gate-source of the IGBT is vGS .Note from Figure 8.18 that this voltage is essentially an exponential, due to theinput capacitance of the IGBT, coupled with the gate resistor (which is to limitthe current flowing into the gate of the IGBT to safe levels). The time periodtd(on) is the time required for vGS to reach a voltage where the device starts toturn on. From this point the current through the device rises as it starts to turnon harder. Eventually vDS is of the order of vGS and the current stabilises at avalue determined by the external circuit.

As vDS starts to fall a significant amount of current starts to flow through theCgd capacitance. This is due to the fact that there is a changing voltage acrossthe capacitor, and that the value of the capacitance increases considerably asthe space charge region width decreases (effectively decreasing the plate sepa-ration in a parallel plate capacitor) and the stored charge in the device startsto increase. Consequently the rise of vGS flattens out as this capacitance ischarged, this being the result of the extra current being drawn through the gateresistor. Eventually vGS restarts its exponential rise again when vDS ≈ vGS ,stopping when its value reaches vGG.

The vDS waveform during the tfv2 time in Figure 8.18 is usually observedin IGBTs. It is due to two effects – the above-mentioned increase in Cgd asvDS falls (which also occurs in power MOSFETs), and the slower turn-on of thePNP section the IGBT (as compared to the MOSFET portion), which delaysthe associated conductivity modulation due to the injected carriers.

8.2.4.3 IGBT Turn-off

The waveforms for the turn-off of the IGBT are shown in Figure 8.19. The risein the voltage vDS before iD drops is typical of all step down converter circuits.This occurs because the load is considered to be effectively a current source, andtherefore it continues to supply current into the switch device until the voltageon the switch side of the load reaches the supply. At this point the diode acrossthe load will start to turn on and take the load current.

The initial part of the vGS turn-off transient, td(off), occurs because of thetime constant associated with the RG(Cgd2+Cgs) time constant of the MOSFETpart of the IGBT.7 As the drain-source voltage vDS starts to rise, the Millereffect of Cgd2 starts to take effect. This temporary arrests the decrease of vGS

during the interval trv. When vDS stabilises then this effect stops. The decreaseof vGS now continues, but with a time constant of RG(Cgd1 + Cgs), which issmaller than previously due to the change on the value of Cgd caused by thewidening of the space charge region in the device. During all the phase so-farthe IGBT is behaving as a MOSFET.

6Note that the waveforms for turn-on and turn-off are for the IGBT in a step down choppercircuit of the type shown in Figure 8.10, except that the main power device has been replacedby the IGBT and there are no snubbers.

7RG is the gate resistor that is included in the circuit to limit the gate currents to reasonablelevels.


The major difference between the IGBT turn-off and the power MOSFETturn-off is observed in the drain current waveform which has two distinct timeintervals. During the tfi1 time the MOSFET is turning off. The second timeinterval tfi2 is due to the stored charge in the n− region of the device. Sincethe MOSFET is off there is no way that these carriers can be swept out ofthe device by a negative drain current. Consequently these carriers diminishby recombination. The punch-through IGBT attempts to minimise this effectby having a small carrier lifetime in the n+ region. This results in an electronconcentration gradient from the n− region to the n+ region, thereby sweepingthe electrons from the device.8 The non-punch-through IGBT attempts to min-imise the tail off current by redesigning the IGBT so that the majority of thecurrent is carried by the MOSFET. This minimises the stored charge.

At the time of writing these notes IGBTs are in a rapid state of development.Currently the most advanced devices are capable of withstanding approximately6kV, and can conduct several thousand amperes. The turn-off times for thesedevices are of the order of 1µsec of less. For medium power systems IGBTs arecurrently the device of choice.

8.2.5 Other Devices and Developments

Thus far we have concentrated on the devices that are the most important onesin terms of current practice. However there is also significant work going on intonew devices that still have not reached the commercial stage. We shall brieflymention some of these.

8.2.5.1 Power Junction Field Effect Transistors

This device is also sometimes known as the static induction transistor (SIT). Itis effectively a JFET transistor with geometry changes to allow the device towithstand high voltages and conduct high currents. The current capability isachieved by paralleling up thousands of basic JFET cells. The main problemwith the power JFET is that it is a normally on device. This is not good froma start-up viewpoint, since the device can conduct until the control circuitrybegins to operate. Some devices are commercially available, but they have notfound widespread usage.

8.2.5.2 Field Controlled Thyristor

This device is essentially a modification of the SIT. The drain of the SIT ismodified by changing it into an injecting contact. This is achieved by making ita pn junction. The drain of the device now becomes the anode, and the sourceof the SIT becomes the cathode. In operation the device is very similar to theJFET, the main difference being quantitative – the FCT can carry much largercurrents for the same on-state voltage. The injection of the minority carriersin the device means that there is conductivity modulation and lower on-stateresistance. The device also blocks for reverse voltages due to the presence ofthe pn junction.

8It is desirable to have long carrier life times in the n− region so that the bulk resistanceis kept low in this region when the device is on.


8.2.5.3 MOS-Controlled Thyristors

The MOS-controlled thyristor (MCT) is a relatively new device which is avail-able commercially. Unfortunately, despite a lot of hype at the time of its intro-duction, it has not achieved its potential. This has been largely due to fabrica-tion problems with the device, which has resulted on low yields. Figure 8.20 isan equivalent circuit of the device, and its circuit symbol.

From Figure 8.20 one can see that the device is turned on by the ON-FET,and turned off by the OFF-FET. The main current carrying element of thedevice is the thyristor. To turn the device on a negative voltage relative to thecathode of the device is applied to the gate of the ON-FET. As a result this FETturns on, supplying current to the base of the bottom transistor of the SCR.Consequently the SCR turns on. To turn off the device, a positive voltage isapplied to the gate. This causes the ON-FET to turn off, and the OFF-FET toturn on. The result is that the base-emitter junction of the top transistor of theSCR is shorted, and because vBE drops to zero. volt it turns off. Consequentlythe regeneration process that causes the SCR latching is interrupted and thedevice turns off.

The P-MCT is given this name because the cathode is connected to P typematerial. One can also construct an N-MCT, where the cathode is connectedto N type material.

8.2.5.4 New Semiconductor Materials

Silicon is presently the only material that is widely used for the fabrication ofthe power semiconductors (and integrated circuits for that matter). The reasonfor this is the ease with which large and very pure crystals can be grown withSilicon. However, there are other materials that have superior properties ascompared to Silicon, especially in high power/high voltage applications.

Gallium Arsenide (GaAs) is a well used material, especially in high frequencyapplications, where its very high carrier mobility allows higher frequency devicesto be constructed. In addition it has a higher bandgap than Silicon, which meansthat it can support higher voltages than Silicon, and can be operated at highertemperatures (460C and compared to 300C for Si).

Silicon Carbide is a material which is currently attracting a lot of research.It has a significantly larger bandgap than Si (2.9eV as compared to 1.12ev forSi), has excellent thermal conductivity (approximately 3 times that of Si), andcan operate at temperatures of 600C, with a maximum operating temperatureof 1240C. The breakdown electric field strength is approximately 10 times thatof Si, meaning that it can withstand significantly higher voltages. SiC devicesare probably on 3 to 5 years from commercialisation.

Diamond is the ideal material for power semiconductors. It can operate atvery high temperatures (similar to SiC), it can withstand fields approximately100 times larger than Si, it has thermal conductivity 5 times larger than SiC (andtherefore 15 times larger than Si), and it has electron mobility approximatelytwice that of Si. Unfortunately there is much research to be done before we seecommercial diamond based power electronic devices (15-30 years).

One can see that there are many exciting developments occurring in the areaof power electronic devices. These new devices then open up new applications,that previously were not feasible.


SiO2

SiO2

n n

p

n

n

p

Source Gate

Drain

+++++ + + +

--

Channel

Lateral bodyspreadingresistance

i

i

Minoritycarrierinjection

SiO2

SiO2

n n

p

n

n

p

Source Gate

Drain

i

i

Minoritycarrierinjection

(b)

Collectorregion

Drift regionresistance

(a)

Figure 8.16: Current flows in the IGBT.


Drain

Source

Gate


Drain

Source

Gate


Body regionspreadingresistance

(a) (b)

Figure 8.17: Equivalent circuits for the IGBT: (a) approximate equivalent circuitfor normal operating conditions; (b) more complete equivalent circuit showingthe parasitic thyristor.


t

v vGS GG

/

0

Vd

vDS

iD

Io

vDS(on)

Rg

vDS

vGS

vGG

vGG

td(on)

tri

t

t

Cgd

CgsDefinitions

tfv1

tfv2

vGS

Figure 8.18: Typical turn-on waveforms for an IGBT.


t

v vGS GG

/

0

Vd

vDS

iD

Io

vGG

t

t

vGS

vGG

vGS Io,

vGS(th)

td(off)

trvt

fi1

tfi2

MOSFET

current

BJTcurrent

0

0

Figure 8.19: Turn-off waveforms for an IGBT.

Anode

Cathode

A

K

Gate

G

OFF-FET

ON-FET

Figure 8.20: Schematic and circuit symbol for the P-MCT.


Chapter 9

Line FrequencyUncontrolled Rectifiers

9.1 Introduction

The power input into most power electronic devices is derived from 50/60Hz acsine wave supplies provided by the electricity authorities. This supply generallyis converted into a dc supply before being used or converted into another form.The traditional and simplest way of achieving the ac–dc conversion is via anuncontrolled rectifier based on diodes. Such rectifiers only allow power to flowfrom the ac to the dc side. The vast majority of power electronic applicationscurrently use such rectifiers to do the ac–dc conversion, although this situa-tion may change in the future due to mains harmonic requirements (which aredifficult to meet using conventional rectifiers).

This chapter shall look at the basic operation single phase and three phaseuncontrolled rectifiers. Some analysis will be carried out (based on the as-sumption of ideal diodes) to ascertain the harmonic performance of the variousrectifiers. Before doing this there is some concepts that we will need to intro-duce.

9.2 Some Mathematical Preliminaries

One of the characteristics of diode rectifier circuits is that the produce non-sinusoidal currents in the ac mains. Therefore consideration of non-sinusoidalwaveforms is relevant to carrying out analysis of these types of circuits. Muchof the analysis is carried out assuming that the circuits are in steady state,and then calculating the Fourier components in the current (and in some casesthe voltage) waveforms. We shall therefore quickly review Fourier analysis asapplicable to power electronic waveforms.

308 Line Frequency Uncontrolled Rectifiers

9.2.1 Fourier Analysis of Repetitive Waveforms

In general, a non-sinusoidal waveform, f(t), which repeats with an angularfrequency of ω, can be expressed as [19]:

f(t) = F0 +∞∑

n=1

fn(t) =12a0 +

∞∑n=1

an cos(nωt) + bn sin(nωt) (9.1)

where F0 = 12a0 corresponds to the average value of the waveform (or the dc

component), and the coefficients in (9.1) are:

an =1π

∫ 2π

0

f(t) cos(nωt) d(ωt) (9.2)

bn =1π

∫ 2π

0

f(t) sin(nωt) d(ωt) (9.3)

Note that the F0 term is calculated if the harmonic number starts from 0 insteadof 1 – i.e.:

F0 =12a0 =

12π

∫ 2π

0

f(t)d(ωt) =1T

∫ T

0

f(t)dt (9.4)

which is the average value of f(t) as noted previously.Each component of the waveform can therefore be written as:

fn(t) = an cos(nωt) + bn sin(nωt) (9.5)

which can be simplified using the following trigonometric identity:

A cos θ + B sin θ =√

A2 + B2 cos(θ ± φ) (9.6)

where tan φ = ∓BA . Since via (9.6) equation (9.5) can be written as a cos

function, then we can eliminate the frequency component of the waveform andwrite the expression as a phasor:

−→F n = Fnejφn (9.7)

where:

Fn =

√a2

n + b2n√

2(9.8)

tan φn =(−bn)

an(9.9)

In many situations in power electronics the waveforms do not have a dccomponent. This coupled with the symmetry that is present can considerablysimply the generation of the Fourier coefficients. These are shown in Table 9.1for several of the common symmetries.

If the definition of the rms value1 of a waveform f(t) is applied to the functionwhen expressed in terms of its Fourier components, it can be easily shown thatthe rms amplitude is:

F =

√√√√F 20 +

∞∑n=1

F 2n (9.10)

1Definition of the rms value of a quantity is xrms =√

1T

∫ T0 x(t)2 dt.

9.2 Some Mathematical Preliminaries 309

Symmetry Condition Required Fourier CoefficientsEven f(−t) = f(t) an = 2

π

∫ π

0f(t) cos(nωt) d(ωt) bn = 0

Odd f(−t) = −f(t) an = 0 bn = 2π

∫ π

0f(t) sin(nωt) d(ωt)

Half-wave f(t) = −f(t + 12T ) an = bn = 0 for even n

an = 2π

∫ π

0f(t) cos(nωt) d(ωt) for odd n

bn = 2π

∫ π

0f(t) sin(nωt) d(ωt) for odd n

Even quarter-wave Even and half-wave an =

4π

∫ π/2

0f(t) cos(nωt) d(ωt) for odd n

0 for even nbn = 0 for all n

Odd quarter-wave Odd and half-wave an = 0 for all n

bn =

4π

∫ π/2

0f(t) sin(nωt) d(ωt) for odd n

0 for even n

Table 9.1: Fourier coefficient formulae with symmetry.

9.2.1.1 Measures of Waveform Distortion

Consider Figure 9.1 which shows the voltage and current waveforms in a situ-ation where a power electronic device is connected to the grid supply [4]. Thecurrent waveform shows significant distortion.2 The voltage on the other handis shown without distortion, since it usually does not display the same amountof distortion as the current. This is the case because the voltage distortion arisesfrom the current causing a voltage drop across the line impedances.3

t

v i,

vs

is

is1

idis

1

0

Figure 9.1: Line current waveform distortion.

Let us assume that the supply voltage can be represented as:

vs(t) =√

2Vs sin ω1t (9.11)

2The distortion in this current waveform is typical of that one would expect from a dioderectifier connected to the grid.

3The undistorted voltage assumption makes the analysis simpler in this section.


The input current is represented by its Fourier components:

is(t) = is1(t) +∞∑

n=1

isn(t) (9.12)

where:

is1 the fundamental line current

isn the harmonic components of the line current

We can write (9.12) in an expanded form as follows:

is(t) =√

2Is1 sin(ω1t − φ1) +∞∑

n=1

√2Isn sin(ωnt − φn) (9.13)

where:

φ1 the phase angle of the fundamental (9.14)

Is, Isn rms value of the relevant harmonic (9.15)

The rms value of the current can be calculated using the general expressionnoted in footnote 1. If expression (9.12) is substituted into this, the cross-product terms all integrate to zero due to the orthogonality property of cos andsin functions. The rms current therefore becomes:

Is =

√√√√I2s1 +

∞∑n=1

I2sn (9.16)

The total distortion of waveforms in general is usually measured by a pa-rameter called the total harmonic distortion, which is abbreviated as the THD.total harmonic dis-

tortion The distorted component of the current is essentially all the componentsof the current except the fundamental component. Therefore using the timedomain expressions for the currents we can write the distortion component as:

idis(t) = is(t) − is1(t) =∞∑

n=1

isn(t) (9.17)

This current is shown schematically in Figure 9.1.Therefore, using (9.16), the rms value of the distortion section of the current

can be written as:

Idis =√

I2s − I2

s1 =

√√√√ ∞∑n=1

I2sn (9.18)

The THD of the current defined as:

%THD = 100 × Idis

Is1(9.19)

= 100 ×√

I2s − I2

s1

Is1(9.20)

= 100 ×

√√√√ ∞∑n=1

(Isn

Is1

)2

(9.21)


9.2.1.2 Power and Power Factor

Clearly the purpose of a power electronic system is to convert electrical energyin different ways to allow energy (or power) to be effectively and efficiently used.Therefore it is relevant to briefly review the concept of power, and then to lookat a generalisation of the concept of power factor to systems with non-sinusoidalwaveforms.

Let us begin with single phase power expressions. Consider the followingtime domain expressions for current and voltage flowing into some arbitrarynetwork:

v = V cos ωt (9.22)i = I cos(ωt + θ) (9.23)

Using the definition of instantaneous power we can write:

P = vi (9.24)= [V cos ωt][I cos(ωt + θ)] (9.25)= V I cos ωt[cos ωt cos θ − sin ωt sin θ] (9.26)

= V I cos2 ωt cos θ − V I cos ωt sinωt sin θ (9.27)

Using cos2 ωt =12[1 + cos 2ωt] one can write (9.28)

P =V I cos θ

2[1 + cos 2ωt] − V I sin θ cos ωt sin ωt (9.29)

Using the trig relation:

cos ωt sin ωt =12

sin 2ωt

we can modify the last term of (9.29) as follows:

P =V I cos θ

2[1 + cos 2ωt] − V I

2sin 2ωt sin θ (9.30)

=V I

2cos θ +

V I

2cos θ cos 2ωt − V I

2sin θ sin 2ωt (9.31)

Using cos(x + y) = cos x cos y − sin x sin y, this can be written as

P =V I cos θ

2︸︷︷︸Average Real power

+V I

2cos(2ωt + θ)︸︷︷︸

Oscillatory component

(9.32)

The oscillatory power component represents the power flowing into and out ofthe storage element of the particular circuit.4 The average real power componentessentially causes an offset in this oscillation component so that there is anaverage value of power over a complete cycle.

The other way of representing the power expression for sinusoidal steadystate systems is in the form of the complex power: complex power

4As we shall later this component consists of two different parts, one belonging to the realpower and the other to the imaginary power.


−→S =

−→V

−→I ∗ (9.33)

where ‘∗’ represents the complex conjugate, and the −→x means that x is a phasor.Let us assume that:

−→V = Vrmse

jα (9.34)−→I = Irmse

jβ (9.35)

where Irms and Vrms represent the current and voltage RMS values.Substituting (9.35) and (9.34) into (9.33) we can write:

−→S = VrmsIrms cos θ + jVrmsIrms sin θ (9.36)

where θ = α − β.5

Equation (9.36) is broken up into two components:

P = VrmsIrms cos θ (9.37)Q = VrmsIrms sin θ (9.38)

One can see the vector relationship of these components in Figure 9.2. Noticethat the use of the complex conjugate in the complex power expression meansthat the angle used is effectively the angle of the voltage phasor with respect tothe current, despite the fact that the convention is that the currents phase ismeasured relative to the voltage.6

V

I

Real

Imag

V cos

V sin

Q VI sin

P VI cos

Figure 9.2: Phasor relationship for complex power.

The correspondence between (9.37) and the average real power componentof (9.32) is easy to see. However, the correspondence between (9.38) and the

5The angle θ is the angle from the current vector to the voltage vector.6It is possible to define complex power as

−→S =

−→I−→V ∗. In this case the angle is the current

with respect to the voltage in the power expression. The meaning of the sign of the complexpower changes with this definition.


oscillatory power part of (9.32) is not immediately obvious. Clearly Q is relatedthe component of the voltage that is orthogonal (in a temporal sense) to thecurrent, multiplied by that current. This correspondence is more easily seen bymanipulating (9.29) into the form:

P =V I cos θ

2+

V I cos θ

2cos 2ωt︸︷︷︸

Real power component

− V I sin θ

2sin 2ωt︸︷︷︸

Reactive power component

(9.39)

where V and I are the peak values of the voltage and current.We can see from this expression that the real power actually oscillates (with

the oscillation being unipolar), and has an average value of (V I/2) cos θ. Thereactive power component on the other hand does not have an offset term and itsaverage value is zero. The amplitude of this term is equal to the Q term in thecomplex power expression. Therefore the reactive power component correspondsto power that is flowing into the circuit and out again per half cycle of thefundamental voltage (or current). These components are shown in Figure 9.3for a phase angle of 30. This plot is of the normalised power, the normalisationfactor being VrmsIrms. Notice the reactive power component has no average dccomponent.

0 1 2 3 4 5 6 7-0.5

0

0.5

1

1.5

2

[rad]

Nor

mal

ised

pow

er

Total power

Real power

Reactive power

Average power

Figure 9.3: Diagram of the normalised single phase power components with a30 phase angle – the power is normalised by dividing by VrmsIrms.

Remark 9.1 The presence of reactive power is generally undesirable because itcontributes to the current in the circuit (and therefore the size of the conductorsrequired) without carrying any average power to the load.

Remark 9.2 With an inductive load the current lags the voltage (or the voltageleads the current). Therefore in the complex power expression the angle θ is


positive, and consequently Q is positive. Therefore an inductive load absorbsreactive power, which is given the units of VARs (Volt Ampere Reactive). Thisis called absorbing lagging VARs.

Conversely, a capacitive load results in the current leading the voltage (orthe voltage lags the current). Therefore in this case the θ angle is negative, andtherefore a capacitive load draws negative VARs from the supply (called leadingVARs). It can also be said that the capacitor supplies positive VARs to thesupply.

Let us now briefly consider the concept of three phase real and reactivepower. We shall assume that the phase currents and voltages in a star connectedthree phase real and

reactive power system are:7va = V cos ωtvb = V cos(ωt + 2π

3 )vc = V cos(ωt − 2π

3 )ia = I cos(ωt + θ)ib = I cos(ωt + 2π

3 + θ)ic = I cos(ωt − 2π

3 + θ)

⎫⎪⎪⎪⎪⎪⎪⎬⎪⎪⎪⎪⎪⎪⎭

(9.40)

These voltages and currents can be multiplied together to give the three phasepower expression:

P = vaia + vbib + vcic

=3V I cos θ

2+

V I cos θ

2(cos 2ωt + cos(2ωt − 2π

3) + cos(2ωt +

2π

3))

− V I sin θ

2(sin 2ωt + sin(2ωt − 2π

3) + sin(2ωt +

2π

3)) (9.41)

Terms two and three in (9.41) are zero because the cosine and sine terms eachadd to be zero. Therefore the power expression becomes:

P =3V I cos θ

2(9.42)

which is simply three times the average power in (9.39) (as one would expect).

Remark 9.3 The interesting aspect about the three phase real power is that it isconstant – i.e. the total real power flowing into a three phase system is constantdespite the fact that the individual powers in the phase are oscillating.

Let us consider the last part of (9.41). Rewriting this term one can see that:

−V I sin θ

2sin 2ωt =

V I sin θ

2

[sin(2ωt − 2π

3) + sin(2ωt +

2π

3)]

(9.43)

which means that the reactive power in one phase is being absorbed by twoother phases. Therefore the reactive power is cycling around between the threephases, and hence is not seen on the external three phase power (although thereis obviously still the single phase reactive power there in each of the individualphases). The reactive power of three phase systems is considered to be thereactive power of an individual phase, whereas the real power of a three phasesystem is three times the real power of an individual phase.

Now that we have consider the concepts of real and reactive power for singleand three phase systems, let use now revise the concept of power factor forsinusoidal systems. We know from (9.37) that the real power is:power factor

7The star connection means that there are no zero sequence currents flowing.


P = VrmsIrms cos θ (9.44)

where θ is the angle from the current to the voltage phasor. If the current andthe voltage were in phase then the power is obviously VrmsIrms. This is themaximum possible power. It is also known as the apparent power in a systemwhere there is a phase difference between the voltage and the current. Thepower factor is a measure of how close the actual real power is to the apparentpower – i.e.:

PF = cos θ =P

VrmsIrms(9.45)

The next step is to generalise the power factor expression to the case wherethe current is not sinusoidal. We begin with the basic definition of average generalised power

factorpower:

P =1T1

∫ T1

0

p(t) dt =1T1

∫ T1

0

vs(t)is(t) dt (9.46)

where T1 is the period of the fundamental waveform.

Remark 9.4 Mathematical preliminary: Using cos θ cos nθ = 12 cos(θ + nθ) +

12 cos(θ − nθ), where n = 2,3,. . ., one can write:∫ 2π

0

cos(θ) cos(nθ) dθ =∫ 2π

0

12[cos((n + 1)θ) + cos((1 − n)θ)] dθ (9.47)

=12

[∫ 2π

o

cos(n + 1)θ dθ +∫ 2π

0

cos(1 − n)θ dθ

](9.48)

=12

[sin(n + 1)θ

n + 1

]2π

0

+[sin(1 − n)θ

1 − n

]2π

0

(9.49)

=12

sin(n + 1)2π

n + 1− sin0

n + 1+

sin(1 − n)2π

1 − n− sin 0

1 − n

(9.50)

= 0 (9.51)

Note that if n = 1, then (9.47) becomes:∫ 2π

0

cos(θ) cos(θ) dθ =∫ 2π

0

cos2 θ (9.52)

=∫ 2π

0

12

[cos 2θ + cos 0] dθ (9.53)

=12

[sin 2θ

2

]2π

0

+ [θ]2π0

(9.54)

= 2π (9.55)

Remark 9.5 Remark 9.4 above shows that the product terms involving differentfrequencies integrate over the fundamental frequency to zero, whereas terms atthe same frequency integrate to give a non-zero term.

Substituting in (9.11) for vs and (9.13) for is, and noting from Remark 9.4that the the integral of the cross-product terms are zero, we can write:

P =1T1

∫ T1

0

√2Vs sin ω1t ·

√2Is1 sin(ω1t − φ1)dt = VsIs1 cos φ1 (9.56)


Remark 9.6 Equation (9.56) shows that the harmonic currents DO NOT con-tribute to the average (real) power drawn from the source. Therefore, one canconsider that the harmonics contribute to the reactive power drawn from thesource. This is the basis for the generalisation of the concept of power factor.

We can generalise the power factor expression by realising that the apparentpower is simply:

S = VsIs (9.57)

where Vs and Is are the true rms values of the voltage and the current (i.e. therms value of a non-sinusoidal current). Therefore, using the same approach asthat for sinusoidal quantities we can write:

PF =P

S(9.58)

Therefore, substituting in the definitions into this expression we can write:

PF =VsIs1 cos φ1

VsIs=

Is1

Iscos φ1 (9.59)

Remark 9.7 From (9.59) one can see that with a non-sinusoidal current sourcethat the sinusoidal power factor is modified by the term Is1/Is – i.e. the fun-damental current rms value divided by the total current rms value. Therefore,as the harmonics increase, the rms value of the current will increase, but thefundamental will not. Therefore the power factor will decrease.

The normal power factor expression is given a new name in this context – itis called the displacement power factor (DPF):

DPF = cos φ1 (9.60)

Therefore the power factor with the non-sinusoidal current is:

PF =Is1

IsDPF (9.61)

Using (9.21) it is possible to write the power in terms of the total harmonicdistortion:

PF =1√

1 + THD2i

DPF (9.62)

9.3 The Half Wave Rectifier Circuit

We shall start our study of uncontrolled rectifiers by looking at the simplestpossible rectifier circuit – a single diode rectifier.

9.3.1 Pure Resistive Load

The simplest possible load for the simplest possible rectifier is a pure resistiveload. The circuit and input and output current and voltages and shown inFigure 9.4. The operation of this circuit is very straight forward and does notwarrant much further discussion. In addition, this circuit is not generally usedbecause of the very high ripple in the output voltage and current. Because theoutput load is a pure resistance there is not output filter, and consequently theoutput voltage is not a very good dc voltage at all.

9.3 The Half Wave Rectifier Circuit 317

R

+ -

vdiode

i

vd

+

-

vs

t

v vs d,

ii v

d, v vs , diode

vdiode

Figure 9.4: Half wave rectifier with a resistive load.

9.3.2 Inductive Load

The case of a half wave rectifier with a inductive-resistive load is more interestingthan the previous case. With inductance in the load the current is more filteredthan the previous case. The following discussion is with reference to the circuitshown in Figure 9.5. The output plots have been generated by putting thecircuit of Figure 9.6, with L = 200mH and R = 50Ω, into the Saber, andrunning the simulation. The first point that one notices in Figure 9.6 is that

+ -vL

vdiode

vout

+

-

+

-

vs

+ - iL

L

R

Figure 9.5: Half wave rectifier with an LR load.

the current continues to flow even when the source voltage has gone negative.When the energy stored in the inductor reaches zero then the current stopsflowing. If the resistor value is made smaller then the current will flow furtherinto the negative half cycle. If the resistance was zero then the current wouldcontinue to flow for the whole of the negative half cycle.

Let us analyse the situation in Figure 9.6. At t = 0 then the diode becomesforward biased and current begins to flow. Assuming an ideal diode then the


(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

(A)

-0.2

0.0

0.2

0.4

0.6

0.8

t1 t

2t3

iL

vs vout v

L

vdiode

Due to simulation numerics

Area A

Area B

Figure 9.6: Plots for a half wave rectifier with an LR load – L = 200mH andR = 50Ω.

9.3 The Half Wave Rectifier Circuit 319

circuit whilst the current is flowing is:

vs = Ri + Ldi

dt(9.63)

At time t1 the current through the inductor reaches its peak value, since fromt = 0 to t1, vL = vs−vout is positive. Notice that after t1 vL becomes negative asthe source voltage decreases, and hence the current through the inductor startsto decrease. At time t2 vs becomes negative. However, the current throughthe inductor continues in the same direction due to the stored energy in theinductor. Eventually at t3 the energy in the inductor is exhausted and thecurrent drops to zero.

Because the current is zero at t = 0 and t3, we can use the inductor currentequation to write:

∆i = i(t3) − i(0) =1L

∫ t3

0

vL dt = 0 (9.64)

since i(0) = i(t3). This means that the total area under the voltage curve acrossthe inductor is zero (which it must be for the circuit to be in steady state). Theintegral in (9.64) can be written as follows:∫ t1

0

vL dt +∫ t3

t1

vL dt = 0 (9.65)

which means that:Area A − Area B = 0 (9.66)

Remark 9.8 To get the exact times for t1, t2 and t3 one needs to solve (9.63).

9.3.3 Inductive Load with Back EMF

Another case of interest is the inductor feeding a back emf scenario. This isshown schematically in Figure 9.7. The voltage source Ed could represent alarge capacitor, for example. The result of the presence of this voltage source isthat the turn-on time for the diode is change as compared to the previous case.

+ -vL

vdiode

+

-

vs

+ - iL

L

+

-E

d

Figure 9.7: Half wave rectifier circuit with an inductor and back emf.

One can see the difference in the performance of the circuit from the Saber

simulation plots shown in Figure 9.8.


(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

(A)

-0.2

0.0

0.2

(V)

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

20.0v

diode

vs

vLE

dArea A Area B

t1

t2

t3

iL

Figure 9.8: Plots for a half wave rectifier with an inductor and back emf as aload.

One can see from Figure 9.8 that the inductor current iL has much thesame shape as that shown in the Figure 9.6, but the magnitude of the currentin smaller. This is an obvious result, since the voltage that can increase thecurrent through the inductor is much smaller in this case because of the Ed

voltage. In addition the time for the current to build up is also smaller. Theother notable difference between this case in that of Figure 9.6 is that the diodereverse voltage is substantially larger in this case.

9.4 The Concept of Current Commutation

Before looking at a practical single phase rectifier circuit we shall briefly lookat the concept of current commutation in power electronic circuits. Althoughwe shall be looking at this in terms of naturally (or self) commutated circuits,the same principles also apply to force commutated circuits.

Up until this point we have not had to consider commutation issues becausewe have been dealing with a single diode circuit. Current commutation refersto the transfer of the current in a circuit from one power electronic device toanother, as one device starts to turn off and the other turn on. In the case of adiode circuit the turn on occurs because the device becomes forward biased, andthe turn off because a device becomes reverse biased. If one is dealing with anideal circuit, then the current would transfer instantaneously from one deviceto another, but if there is inductance in the circuit then this does not occurinstantaneously.

In order to study current commutation consider the test circuit in Figure 9.9.

9.4 The Concept of Current Commutation 321

D1

D2

Idvs

+

-

Ls

is

vL+ -

t

v vs d,

vd

is

vd

Waveforms with Ls 0

vD1

Figure 9.9: Test circuit used for current commutation discussion.


The following discussion is with respect to Figure 9.10. Prior to t = 0 theinput voltage vs < 0, and therefore the diode D2 is conducting the outputcurrent Id. At t = 0 vs becomes positive and the diode D1 becomes forwardbiased and turns on. However, due to the inductance Ls the current iD1 doesnot instantly go to Id. The rise in the current in Ls is limited by the value ofLs and the voltage across it.

Eventually the current in Ls will rise to the value if Id. During this risethe current iD2 will be falling at the same rate as the increase in iD1, so thatthe current to the current source is maintained at Id. When iD1 = Id then thecommutation process is complete, and the current iD2 = 0, turning off D2.

Id

vd

0

D1

D2

Ls

+ -vL

vs

+

-I

dis

iD1

iD2

Id

v vd s

D1

D2

Ls

+ -vL

0

vs

+

-

is

i Is d

(a) During commutation

(b) After commutation

Figure 9.10: Circuit configurations during current commutation of the circuitin Figure 9.9.

Let us analyse this situation as little more closely. Consider the situationwhen the input voltage vs initially becomes greater than zero. The voltage onthe load side of the inductor is zero because D2 is on. Therefore the currentacross the inductor is:

vL =√

2Vs sinωt = Lsdisdt

0 < t < tc (9.67)

where tc the time when commutation is complete.

9.4 The Concept of Current Commutation 323

We can rearrange (9.67) and integrate both sides to give:

√2Vs

∫ tc

0

sinωt dt = Ls

∫ Id

0

dis (9.68)

which becomes:Aθc

=√

2Vs(1 − cos ωtc) = ωLsId (9.69)

where Aθc the volt-second area under the inductor voltage.

Rearranging this expression we can write:

cos θc = 1 − ωLsId√2Vs

(9.70)

where θc ωtc, the commutation angle.

Remark 9.9 Equation (9.70) confirms our previous assertion that if Ls = 0then the commutation occurs immediately the diode D1 turns on – i.e. cos θc =1 ⇒ θc = 0. Also note that as Ls increases the commutation angle increases (asone would intuitively expect), and as Id increases the angle increases due to thefact that it will take longer before iD1 = Id.

Remark 9.10 Another interesting effect of the commutation is that the aver-age voltage produced at the output of the circuit is lower due to commutationnotches. These “notches” result in sections of vs not appearing at the output. commutation

notchesWaveforms for the commutation of the current are shown in Figure 9.11.

These waveforms are the outputs of a Saber simulation. These plots clearlyshow the commutation notches in the output voltage, vd. The commutationnotches appear as the voltage across the Ls inductor. The area of these com-mutation notches, where the horizontal axis is θ = ωt, was evaluated in theexpression (9.69). The plots of Figure 9.11, however, are on the time axis.Therefore, under this condition it can be shown that the expression for the areaunder the inductor notch is LsId (the ω term is omitted). Examination of thenotch integral plot of Figure 9.11 shows that the area is 0.0050081 – in otherwords Ls, which it should be since Id = 1.

It is clear from Figure 9.11 that the commutation notches lower the outputvoltage. We can calculate voltage loss analytically. Firstly we can calculate theaverage output voltage as follows:

Vd0 =12π

∫ π

0

√2Vs sin ωt d(ωt) =

2√

22π

Vs = 0.45Vs (9.71)

In the case where one has commutation notches then the average voltagecan be calculated as:

Vd =12π

∫ π

θc

√2Vs sinωt d(ωt) (9.72)

This expression can be rewritten as the average voltage with Ls = 0 minus the


(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)

0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

(A)

0.0

0.5

1.0

(V)

-20.0

-10.0

0.0

10.0

20.0

(0.020807, -0.022068)

(0.020007, 0.10216)

(V*s

ec)

0.0

0.002

0.004

0.006

(0.020805, 0.0050081)

(V) : t(s)

(A) : t(s)

(V) : t(s)

(V*sec) : t(s)

Notch Area

Comm notchesv

L

i iL s,

Inductor current

vs

vD1

Output vd

Output vd

Figure 9.11: Plots of the currents in the test circuit of Figure 9.9 – vs = 50 sin ωt,Ls = 5mH, Id = 1 Amp.

9.5 Practical Uncontrolled Single Phase Rectifiers 325

average voltage of the commutation notches:

Vd =12π

∫ π

0

√2Vs sin ωt d(ωt) − 1

2π

∫ θc

0

√2Vs sin ωt d(ωt) (9.73)

= 0.45Vs −area Aθc

2π(9.74)

= 0.45Vs −ωLs

2πId (9.75)

Remark 9.11 From equation (9.75) one can see that the loss of output voltageis:

∆Vd =area Aθc

2π=

ωLs

2πId (9.76)

9.5 Practical Uncontrolled Single Phase Recti-fiers

We have now carried out some preliminary analysis on half wave rectifiers todevelop some techniques to analyse rectifier circuits. We shall now apply thesetechniques to a practical single phase rectifier. These circuits are very important,as they form the front end of almost all switch mode power supplies used indomestic and computing applications.

Remark 9.12 The prevalence of the single phase rectifier in computer basedequipment is becoming a problem in power systems due to the harmonics thatthey inject into the power supply. This results in poor power factor, and canlead to heating problems in other pieces of equipment, and occasionally causingfalse triggering of frequency controlled equipment on the network.

The circuit which is the subject of this section is shown in Figure 9.12. Thisis typical of a rectifier used in a linear or switch mode power supply.

+

Ls Rs

vs

+

-

is

vd

Rload

Cd

id

Figure 9.12: A practical single phase rectifier.

If we assume that the current id is discontinuous due to the capacitor voltageresulting in the current going to zero before the end of the half cycle of the input


voltage (similarly to the waveforms for the circuit in Section 9.3.3), then we don’thave to worry about the current commutation from one diode to another.

We shall generate the analytical equations for the circuit under these condi-tions. We shall not solve the equations, as this is a little complicated, but thesolutions are obtainable. If there is current commutation in the circuit then thesolutions get a little more complicated.

Whilst the diodes are conducting the equivalent circuit is as shown in Fig-ure 9.13. Applying KVL to this circuit we can write the following differentialequation:

vs = Rsid + Lsdiddt

+ vd (9.77)

Similarly one can also apply KCL to the circuit to give:

id = Cddvd

dt+

vd

Rload(9.78)

Rearranging we can write the following matrix expressions when the diode isconducting: [

did

dtdvd

dt

]=[

−Rs

Ls− 1

Ls1

Cd− 1

CdRload

] [idvd

]+[

1Ls

0

]vs (9.79)

+C

d Rload

Ls Rs

vs

+

-

id

vd

Figure 9.13: Equivalent circuit of the single phase rectifier when the diodes areconducting.

During the time when the diodes are off (i.e. when the energy in Ls hasbeen expended and vs < vd), the capacitor is discharging into the load resistor.Therefore there is an exponential decay of the output voltage. The expressionfor this time is (using KCL):

Cddvd

dt+

vd

Rload= 0 (9.80)

⇒ dvd

dt= − vd

CdRload(9.81)

Remark 9.13 Using equations (9.79) and (9.81) one can solve for the completeanalytical solution for the currents and the voltages in this circuit.


We shall not attempt to solve (9.79) and (9.81), but instead we shall simulatethe circuit of Figure 9.12 using Saber. The plots in Figure 9.14 are the outputwaveforms of this circuit. In particular notice the vert “spikey” current flowinginto the rectifier, and the ripples on the output voltage due to this, and thedischarge time when all the diodes are off and the output is disconnected fromthe input.

(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2

(V)

0.0

20.0

40.0

60.0

80.0

(A)

-20.0

0.0

20.0

40.0

(V) : t(s)

(V) : t(s)

(A) : t(s)

vs

vd

is

Figure 9.14: Waveforms for the practical single phase rectifier circuit of Fig-ure 9.12.

If one evaluates that harmonics on the current waveform the plot shown inFigure 9.15 is obtained. One can see that the output voltage has a dominantdc component (as it should) which has an amplitude of approximately 47 volts.There is also a harmonic at 100Hz corresponding to the fundamental of theripple on the dc output voltage.

The main harmonic in the current is at 50Hz, but there are also significantharmonics at 150, 250 and 350Hz as well (i.e. the 3rd, 5th and 7th harmonics).One can treat each of the harmonics in the current as a phasor (as in (9.7)).The amplitudes of the real and imaginary components of these phasors can befound using the waveform analysis tools in Saber, and these are plotted inFigure 9.16.

In Figure 9.16 one can see the amplitude of the fundamental real and imag-inary harmonics – a1 = −0.40077 and −b1 = −4.6573.8 Therefore using the

8In Saber the b coefficient is called the imaginary coefficient. It is the negative of theactual b coefficient as appears in a normal Fourier series. Hence we have written the coefficient


Mag

(V)

0.0

20.0

40.0

60.0

f(Hz)

0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k

Mag

(A)

0.0

2.0

4.0

6.0

Mag(V) : f(Hz)

Mag(A) : f(Hz)

is

vd

Figure 9.15: Input current and output voltage harmonics in a single phaserectifier.


f(Hz)

0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k

Im(A

)

-6.0

-4.0

-2.0

0.0

2.0

4.0

Re(

A)

-2.0

-1.0

0.0

1.0

Im(A) : f(Hz)

Re(A) : f(Hz)

(50.0, -4.6573)

(50.0, -0.40077)

is

is

Fourier components generated before 140msec and 180msec

Figure 9.16: Real and imaginary components of the harmonic phasors for theharmonics single phase rectifier harmonics plotted in Figure 9.14.


definitions associated with (9.7) one can see that:

F (1) =√

a21 + b2

1 = 4.4745 Amp (9.82)

φ1 = tan−1 −b1

a1= 265.08 = −94.92 (9.83)

Comparison of (9.82) with the fundamental shown in Figure 9.15 indicates thatthe value appears to be correct. The phase in (9.83) is the phase of a coswaveform (which is the time domain representation of a phasor).

The harmonics in Figure 9.15 and Figure 9.16 were taken by looking atthe input current over two fundamental periods of the input voltage startingat 120msec and ending at 180msec. This was done so that the rectifier wasoperating in steady state, and the transients that can be seen in Figure 9.14would not affect the harmonic analysis. This also means that the phase in(9.83) is with respect to the voltage input waveform. Consequently we can usethe value in (9.83) to get the phase (and hence power factor) of the currentfundamental. Realising that the time domain form of the phasor is:

fn(t) = Fn cos(nω1t + φn) (9.84)

one can write the time domain expression for the fundamental current as:

i1(t) = I cos(ω1t + φ1) (9.85)= 4.47 cos(100πt − 94.92) (9.86)

Using the trigonometric identity cos(x) = sin(x + 90) then we can write:

i1(t) = 4.47 sin(100πt − 4.92) (9.87)

Hence there is a phase shift of the fundamental from the input voltage of −4.92.Consequently, from (9.60) we can see that the DPF is:

DPF = cos φ1 = cos(−4.92) = 0.996 (9.88)

Remark 9.14 From a fundamental current view point the power factor of thesystem is very good. The presence of harmonics is the main contributor to poorpower factor.

The non-sinusoidal power factor is defined by (9.61). Therefore if we cancalculate the rms value of the non-sinusoidal current then we can calculate thenon-sinusoidal power factor. From Figure 9.15 one can see that the harmonicsamplitudes and rms values are as shown in Table 9.2.

Using (9.21) we can now calculated the THD for the input current waveform.Calculating the distorted current using (9.18) we get:

Idis =

√√√√ 13∑n=1

I2sn = 3.1076 (9.89)

as −b1.


Harmonic Amplitude RMS value1 4.6775 3.30543 3.6788 2.60135 2.1911 1.54937 0.87625 0.61969 0.30301 0.214311 0.29773 0.210513 0.18 0.1273

Table 9.2: Current harmonic amplitudes.

Therefore the input current THD is:

THD = 100 × Idis

Is1

= 100 × 3.10763.3054

= 94% (9.90)

Remark 9.15 The value in (9.90) shows that the harmonic distortion of theinput current is quite high.

We can now also calculate the non-sinusoidal power factor using (9.59):

PF =Is1

Iscos φ1

=3.3054

3.1076 + 3.3054× 0.996

= 0.513 (9.91)

Remark 9.16 From (9.91) one can see that the power factor is very low. Com-pare this to the DPF which is 0.996. Therefore the presence of the harmonicsin the input current waveform is a major contributor to the poor power factorof this circuit.

Remark 9.17 Single phase full wave rectifiers such as depicted in Figure 9.12are present in large numbers on the power supply grid (e.g. in computer powersupplies). Therefore the cumulative affect of this could result in a very pooroverall power factor. Techniques for improving the power factor of this rectifiersare now being used.

9.5.1 Unity Power Factor Single Phase Rectifier

The requirement for unity power factor (which implies low harmonic content) forsingle phase rectifiers connected to the grid has spurred research into techniquesto modify the standard single phase full wave rectifier.

One of the standard techniques to filter supply current waveforms is to usepassive filters at the input of rectifier. These passive filters usually consisted ofcombinations of L or LC components. An example of a circuit with this typeof filtering is shown in Figure 9.17 [4]. This particular circuit has filters at theac input and the dc output. The input filter is a classic ‘T’ low pass filter.


This filter basically filters out the higher order harmonics in the input current.The filter in the dc link needs a little explanation. Clearly it is also a low passfilter, and appears to have the classic π structure. The choice of the size ofthe components is important from another point of view. The capacitor Cd1 ischosen to be small so that there is considerable ripple in the vd1 voltage. Thiscauses the current to flow in smoother fashion from the supply via the diodes.The extra ripple in vd1 is then filtered via the low pass filter formed by Ld andCd. The Cd capacitor is much larger than Cd1.

+

Lf 1

vs

+

-

is

vd

Rload

Cd

id

+ +v

d1C

d1C

f

Lf 2

Ld

Figure 9.17: Single phase rectifier with input and dc link filters.

Remark 9.18 The passive circuits have a limited capacity to smooth the inputcurrent. The filtering achieved is capable of improving the power factor theacceptable levels. However there are some shortcomings:

1. The output voltage is lowered due to the presence of the inductors.

2. There is an obvious disadvantage in the cost of the filters, size, losses anddependence of the output voltage on the load current drawn.

The limitations cited in Remark 9.18 have led to the investigation of activecurrent shaping techniques to improve the power factor of the rectifiers. Thesetechniques also have the advantage that they extend the range of operation ofthe rectifier – i.e. the input voltage can vary but the output voltage will stayconstant. For any current shaping circuit to be of practical use it has to havethe following attributes:

• The current shaping circuit should be of low cost and small size.

• It should enable the input power factor to be near unity.

• The circuit should be simple to control.

• It should allow the rectifier to provide the correct voltages under over-voltage as well as under-voltage conditions.

Given these specifications the obvious circuit to provide this functionality isthe boost converter. This circuit is the most suitable for the following reasons:


1. The circuit is capable of producing an higher voltage at the output thanat the input. Therefore as the input voltage falls the output voltage canbe kept constant.

2. If the converter is set-up to provide an output voltage, that is say 10%higher than the nominal peak input voltage, then the circuit can cope withover-voltages of up to 10% without altering the output voltage.

3. The boost converter configuration maintains a continuous current throughthe input inductor (if operating is continuous conduction mode). There-fore the current can be kept continuous through the diodes on the circuit.This intrinsically allows better input power factor to be achieved.

Remark 9.19 Note that the buck converter is in general not suitable for thisapplication because the input current is highly discontinuous. This is due to thefact that the switch in the circuit disconnects the output of the diodes in therectifier from the input to the converter during normal operation.

Figure 9.18 shows the basic structure of a single phase rectifier with a boostconverter for current shaping.

+

Ls Rs

vs

+

-

is

Rload

Cd

id

Boost converter

Ld

iL

ic

iload

vs v vd s( )

Figure 9.18: Circuit for the a single phase rectifier with current wave shapingboost converter.

As can be seen from Figure 9.18 the circuit is simply a conventional rectifierfollowed by a conventional non-isolated boost converter. The boost converteris usually controlled so that the output voltage is approximately 10% higherthan the nominal rated voltage of the rectifier. This allows the circuit to workcorrectly if the supply is up to 10% higher than the nominal voltage. Oneimplicitly gets a circuit that can operate with low voltages because of the boostconverter. How low the voltage can go depends on the design of the boostconverter and the load current and voltage required.

The key to the operation of the unity power factor rectifier is the control ofthe boost converter. Before considering the general principles of the control wefirstly need to clarify the requirements for the control. If we want unity power


factor, than we need a sinusoidal input current which is in phase with the inputvoltage and does not have any significant harmonics. The desired waveformsare shown in Figure 9.19(a) and (b). One can see that the waveforms in theboost converter section of the circuit are sinusoidal in nature.

vs

is

t

(a)

vs

iL

t

(b)

Figure 9.19: Waveforms for a single phase rectifier with active current waveshap-ing – (a) the input current and voltage; (b) the boost converter input voltageand inductor current.

Remark 9.20 Examination of the waveforms in Figure 9.19 indicate that therewill be a ripple voltage on the output filter capacitor (as there is in the conven-tional rectifier). The capacitor has to be designed to be large enough to keep thisripple below acceptable limits.

Ignoring power losses in the boost converter we can apply some basic analysisto the circuit of Figure 9.18 with the waveforms of Figure 9.19. Define Vs =√

2Vs, and Is =√

2Is – i.e. Vs and Is are the rms values of the voltage andthe current. Clearly the instantaneous power flowing into the circuit is (usingsin2 x = 1

2 (1 − cos 2x)):

pin(t) = Vs sinωtIs sin ωt = VsIs − VsIs cos 2ωt (9.92)

which is similar to (9.32), except that this was calculated for cos waveformswith a θ phase difference between them.


If we assume that the output capacitor is large then the voltage ripple acrossit will be minimal, and consequently the output power can be written as:

pd(t) = Vdid (9.93)

where Vd the average output voltage = vd.The current flowing into the load and the capacitor is:

id(t) = Iload + ic(t) (9.94)

Assuming that the switching frequency is very high then the inductor canbe negligibly small. This allows one to use the simplifying assumption that onan instantaneous basis that:

pin(t) = pd(t) (9.95)

and therefore we can write:

VsIs − VsIs cos 2ωt = Vdid(t) (9.96)

∴ id(t) = Iload + ic(t) =VsIs

Vd− VsIs

Vdcos 2ωt (9.97)

One can see from this expression that:

Id = Iload =VsIs

Vd(9.98)

ic(t) = −VsIs

Vdcos 2ωt = −Id cos 2ωt (9.99)

Even though the assumption was made that the voltage across the capacitor wasconstant, we can use (9.99) to get an approximate value of the voltage rippleacross the capacitor:

vd,ripple(t) ≈1

Cd

∫ic(t) dt = − Id

2ωCdsin 2ωt (9.100)

Remark 9.21 From (9.100) it can be seen that if Cd is made large then vd,ripple

can be arbitrarily small.

The key to the correct functioning of this circuit is the control. Two controlloops are required in order to achieve the required control – a voltage control loopso that the output voltage stays are the correct value despite load variations,and a current control loop to provide the input current waveshaping. These twoloops have to work cooperatively.

We have previously encountered both voltage and current control loops,arranged in a hierarchical or nested structure, in relation to switched modepower supply control. A similar arrangement is used here, the main differencebeing the desired reference value for the current.

Figure 9.20 shows a block diagram of the basic structure of the control forthe unity power factor single phase rectifier. This block diagram is almost thesame as that shown in Figure 6.25. The major difference is the inclusion ofthe multiplier of the error by the absolute value of the supply voltage, whichresults in a sinusoidal rectified inductor current reference waveform. This isthen fed to the current control algorithm. The current control algorithm can be


PIRegulator

Vd ,measured

Vd

*

e V Vd d

*

,measured

vs

iL,measued

iL

*

Currentmode

control

Switchcontrolsignal

Figure 9.20: Block diagram of the control system for a single phase rectifierwith active current waveshaping.

implemented in a variety of ways (see Section 6.3.3.3), but the most commontechnique is the “constant frequency with turn-on at clock time” controller.

With this control strategy the net result is that the sinusoidal referencecurrent amplitude is modulated by the output voltage error – the larger thevoltage error the larger the amplitude of the sinusoidal current pulse.

Some other points to note about this circuit:

1. A resistor in series with the Ld inductor is often used to limit the inrushcurrent at start-up. This resistor is usually shorted out by a SCR (largevoltage drop with this though), a relay or a MOSFET once the circuitstarts to operate normally.

2. A small filter capacitor is usually placed across the output of the diodebridge to prevent the switching noise from entering the grid supply.

3. The output filter capacitor only has to be about half the size of that in anuncontrolled rectifier, for the same ripple. Therefore the active rectifiercircuit saves on weight and space.

4. The energy efficiency of a typical active current controlled signal phaserectifier is 96%. An uncontrolled conventional rectifier has an efficiency ofapproximately 99%.

9.5.2 Effect of Current Harmonics on Line Voltages

We have seen in Section 9.5 that the single phase rectifier can produce manyharmonics in the current. In the subsequent analysis of the power factor of thecircuit it was assumed (for simplicity reasons) that the voltage was unaffectedby the presence of these harmonics. However, in a real network this is not thecase.

Consider the circuit shown in Figure 9.21. Here we can see a conventionalsingle phase rectifier connected to the grid supply via a source resistance andinductance. Note that the inductance is divided into two sections, the sectionbetween them being the so called “point of common coupling” (PCC). The PCCis the nearest point to the rectifier where other equipment can be connected tothe grid supply. Note that there is an additional inductance, representing theinductance of the grid supply, between the PCC and the grid supply voltagesource. It is the inductance of this impedance that causes the current harmonics


to affect the supply voltage seen by other devices connected to the grid supply.The voltage across other equipment at the PCC is:

+

Ls1 Rs

vs

is

vd

Rload

Cd

id

Ls2

Other equipmentconnected to the

supply

Point of common coupling (PCC)

+

-

vPCC

Figure 9.21: Single phase rectifier showing the point of common coupling.

vPCC = vs − Ls1dis1dt

(9.101)

where vs is assumed to be an ideal sinusoidal voltage source.The current is1 contains the harmonic currents of the single phase rectifier

(as well as the harmonics drawn by the other equipment). These harmonics willcause a voltage drop across the Ls1 inductance. This drop can be considerable,since the impedance of an inductor increases with increased frequency.

One can break the current into a sinusoidal component and the distortedcomponents as follows:

vPCC =(

vs − Ls1dis1dt

)− Ls1

∑h=1

dish

dt(9.102)

Clearly the fundamental component is:

vPCC1 = vs − Ls1dis1dt

(9.103)

and the distortion component is:

vPCCdis = −Ls1

∑h=1

dish

dt(9.104)

9.5.3 Voltage Doubler Single Phase Rectifiers

The circuit shown in Figure 9.22 is sometimes used in cost conscious commercialproducts to produce voltage doubling without the use of a transformer. Depend-ing on the position of the switch the rectified dc voltage is either approximatelythe peak of the sinusoidal input voltage, or alternatively it is twice this peakvoltage.


vd

C1

C2

D1

D2

Doublepos

vac

Figure 9.22: Single phase rectifier voltage doubler.

If the switch is closed then on a positive half cycle of the input voltagecurrent flows via D1, capacitor C1, and the switch back to the supply. On thenegative half cycle the current flow via the switch, capacitor C2 and diode D2

back to the supply. The result is that the two capacitors have the peak supplyvoltage across them, and their voltages sum. If the switch is open, then thecircuit behaves as conventional bridge rectifier.

9.5.4 The Effect of Single Phase Rectifiers on Three Phase,Four Wire Systems

In large commercial buildings the primary loads are of a single phase nature,even though the building as a whole is supplied with a three phase power system.These single phase loads are usually distributed as evenly as possible betweeneach of the three phases and the neutral of the system, as shown in Figure 9.23.If the loads on the system are linear loads then such a strategy will lead toa neutral current that is approximately zero. However, if the loads are largelysingle phase rectifiers, the non-linear nature of these loads can lead to substantialneutral currents.

Assume that the diode rectifiers in each of the phases are identical. Wecan therefore write the currents in the phases as a combination of the funda-mental and harmonics currents (which are the odd harmonics, since, as shownpreviously, the even harmonics are zero):

ia = ia1 +∞∑

h=2k+1

iah (9.105)

=√

2Is1 sin(ω1t − φ1) +∞∑

h=2k+1

√2Ish sin(ωht − φh) (9.106)

In a similar manner to (9.106) one can write the other currents in the phases


ia

ib

ic

ab

c

Single phase rectifierloads

in

n

Figure 9.23: Single phase rectifiers loads in a three phase, four wire distributionsystem.


(assuming they are of similar form):

ib =√

2Is1 sin(ω1t − φ1 − 120) +∞∑

h=2k+1

√2Ish sin(ωht − φh − 120h)

(9.107)

ic =√

2Is1 sin(ω1t − φ1 − 240) +∞∑

h=2k+1

√2Ish sin(ωht − φh − 240h)

(9.108)

Applying Kirchhoff’s current law to Figure 9.23 we can write:

in = ia + ib + ic (9.109)

If one substitutes (9.106), (9.107) and (9.108) into (9.109) then all the non-triplen and fundamental harmonics add to be zero. The triplen harmonics onthe other hand add to give:

in = 3∞∑

h=3(2k−1)

√2Ish sin(ωh − φh) (9.110)

which can be written in rms terms as:

In = 3

⎛⎝ ∞∑

h=3(2k−1)

I2sh

⎞⎠1/2

(9.111)

Therefore the third harmonics add together in the neutral, and the neutralcurrent therefore becomes:

In = 3Is3 (9.112)

The third harmonic current in the lines can be quite significant with single phaserectifier loads, and consequently the neutral current can be large. In fact underconditions of highly non-linear loads, the neutral current can be as much as√

3Iline. Therefore, the neutral should be a conductor that can at least carry asmuch as the lines.

9.6 Three Phase, Full Bridge Rectifiers

Whilst single phase rectifiers predominate in domestic and computer rectifi-cation applications, industrial rectification is carried mainly with three phaserectifiers. This is due to their lower voltage and current ripple, and their higherpower carrying capabilities. These devices naturally balance the loading on eachof the phases, and therefore do not require any planning action in this respect.Furthermore, no triplen harmonics can flow in these circuits since there is noneutral connection.

The fundamental circuit for the conventional six pulse three phase rectifieris shown in Figure 9.24.

In order to understand the operation of this device we shall firstly look at asimplified model of its operation. Assume that the load is not modelled as an

9.6 Three Phase, Full Bridge Rectifiers 341

a

b

c

Ls

Ls

Ls

D1

D3

D5

D4

D6

D2

+C

dR

load

id

vd

ia

ib

ic

n

+

+

+

Figure 9.24: Basic three phase, six pulse, full wave rectifier circuit.

Graph0

(V)

0.0

200.0

400.0

600.0

t(s)

0.0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09

(V)

-400.0

-200.0

0.0

200.0

400.0

(A)

-5.0

0.0

5.0

(A)

-5.0

0.0

5.0

(A)

-5.0

0.0

5.0

(V) : t(s)

output_voltage

(V) : t(s)

v(v_sin.phase_a)

v(v_sin.phase_b)

v(v_sin.phase_c)

(A) : t(s)

i(v_sin.phase_a)

(A) : t(s)

i(v_sin.phase_b)

(A) : t(s)

i(v_sin.phase_c)

Figure 9.25: Waveforms of a three phase rectifier with a constant current sourceload.


RC as in Figure 9.24, but as a constant current sink. This is an approximationto a highly inductive load. The plots of the phase currents and output voltagesof this converter are shown in Figure 9.25. As can be seen from this diagram,the output voltage consists of 6 segments per input voltage period. Thereforethis rectifier is often known as a six pulse rectifier.

Chapter 10

Introduction to OtherPower Electronic Devicesand Applications

10.1 Introduction

This chapter briefly introduces several other high power, power electronic switch-ing devices and applications that are industrially important. The presentationhere is brief and introductory in nature, and by no means comprehensive. Itis intended to introduce the student to other power electronic circuits, hith-erto not considered, and some of their applications. The applications chosenare, hopefully, those that are interesting to the readers. Thnose who wish toresearch into any of the circuits and applications presented are encouraged tofollow up the topics in the references.

The remainder of this chapter will consider the following:

• Inverters and applications

• Multilevel converters and applications

• Matrix converters

10.2 Inverters and Applications

In the previous chapter we briefly considered rectifiers. A rectifier is the namegiven to a power electronic device which accepts AC voltage at its input, and“rectifies” this to DC voltage at the output. The power flow is considered to befrom the AC to the DC side. The term rectifier refers to the operational functionof the power electronic hardware, but not the configuration of the hardware.This distinction is demonstrated by the cycloconverter. The cycloconverteruses power electronic hardware that is virtually the same as that of a phasecontrolled rectifier and generates AC output voltages from AC input voltages.Power can flow bidirectionally in these devices.

344 Introduction to Other Power Electronic Devices and Applications

P

P

Rectifier mode

Inverter mode

AC DCCONVERTER

Figure 10.1: Definition of rectifier and inverter modes of operation [4].

An inverter, is the dual of the rectifier, in that it accepts DC input andgenerates an AC output – i.e. power flow is from the DC to the AC side of thepower electronic device. As with the rectifier, this definition does not define thehardware configuration, since it is possible to have the same hardware acting asan inverter and rectifier.

The above is summarised in Figure 10.1. Consider, for example, the rectifierconsidered at the end of Chapter 9, i.e. Figure 9.24. In this circuit that mainelectronic components are diodes. Diodes can only conduct current in one di-rection. Therefore, if the output voltage is only allowed to be one polarity, thenpower cannot be transferred from the DC side to the AC side of the converter,as current cannot flow in the reverse direction through the diodes. It is this factthat defines this circuit to be a rectifier.

Converter 1 Converter 2

EnergyStorageElement

Input Output

Figure 10.2: Generic power processing block [4].

Many power electronic systems have the configuration shown in Figure 10.2.Converter 1 transforms the input to DC. There is a storage element that isable to accept the energy. Converter 2 then converters to DC to the desiredoutput. The energy storage element is typically a capacitor or inductor. Itspresence means that the instantaneous input power does not have to equal toinstantaneous output power, thereby providing a degree of decoupling of theinput from the output, and allowing a degree of independence in the controland operation of the two converters.

Figure 10.3 shows a less abstract version of Figure 10.2 for one form of an

10.2 Inverters and Applications 345

+Converter 1 Converter 2

DC link

ACMotor

Utility

ACAC

Figure 10.3: Block diagram of a generic AC drive system.

AC drive system. Notice that in this particular case to energy storage element isa capacitor. Both the input and the output is AC. Therefore, in this applicationthere is inherently an inversion process, since one way or another power mustgo from the DC to AC side.

In many actual implementations of Figure 10.3 Converter 1 is a rectifier, andConverter 2 is an inverter. This means that power can only flow from the utilityto the motor, and not in the reverse direction since the rectifier cannot transferpower back to the utility. Depending on the details of the implementation ofConverter 2, it is possible that it can act as a rectifier, and power can from themotor (which is now acting as a generator, the mode being called regeneration)back to the DC link. In this case the capacitor can accept the energy, butone must be careful to ensure that not too much energy is transferred, else thecapacitor will experience over-voltage and be destroyed.

If a motor is going to be regenerating for a significant percentage of timeduring operation, then both Converter 1 and Converter 2 need to be able toact as both a rectifier and an inverter. If this is the situation then regeneratedenergy can be transferred back to the utility supply, and the capacitor voltagecan be controlled to remain within bounds.

Remark 10.1 It is possible to further classify inverters based on the type oftechnology used to implement the inverter – forced commutated converters, res-onant link converters. We shall not look a these differences in detail here.

Figure 10.4 shows a specific implementation of an inverter. The main differ-ence between this and Figure 9.24 is that the diodes in the circuit are in parallelwith a switch. Most modern small to medium power inverters these days useIGBTs as the switch. The arrows on the switches in Figure 10.4 indicate thatthis is the direction that current can flow through the switch.

The presence of the parallel switches across the diodes makes a major dif-ference to the operation of this circuit. By appropriate switching of the sixswitches an AC voltage (in an average sense) can be synthesized on the threephase outputs of the inverter. The presence of the diodes, of course, meansthat the circuit can always operate as a rectifier. In fact, this very circuit is nowcoming into use as the rectifier front end to large drive systems. Its ability to al-low bidirectional power flow means that this rectifier allows a fully regenerativesystem.


+DC

Z

Z

Z

3 phase AC load

DC link

a

b

cn

R

R

g

Artificial ground

vag

vbg vcg

Figure 10.4: Specific implementation of an inverter.

10.2.1 Pulse Width Modulation

Thus far we have only considered one form of the hardware for an inverter.In order for an inverter to work, there has to be a strategy for controllingthe switches. In section 5.4.2 we considered how to generate a Pulse WidthModulation (PWM) strategy to produce a desired average output voltage. Thiswas based on the use of a triangular carrier wave intersecting with the desiredwaveform. The essentials of this technique are shown in Figure 5.11 on page 138.The same technique can be used for three phase systems.

If we consider just one leg of the three phase converter of Figure 10.4, thenthe technique outlined in section 5.4.2 can be applied directly. When the ref-erence waveform exceeds the triangluar waverform then the top switch in theleg is turned on, and the bottom leg off. When the reference waveform is lessthat the triangular waveform, then the bottom transistor is turned on and thebottom transistor is turned off. The waveforms produced when the centre of theDC link is used as the reference point for the voltage are shown in Figure 10.5.

Remark 10.2 Note that the fact that the load is referenced to the centre of theDC link allows true AC voltage and AC current to be applied to the load. Thisis similar to the situation in the three phase inverter.

In the case of a three phase inverter to see how the waveforms appear is alittle more complex, and not quite as obvious. As in the single leg case oneneeds to establish a reference point to define the voltages, and similarly themid point of the DC link is often chosen. Therefore, if the top switch of a legis closed (meaning that the bottom switch is open) then the voltage on thephase output terminal is 1

2VDC where VDC is the total voltage across the DClink. Similary if the bottom switch is closed (meaning that the top switch isopen), then the voltage on the phase output terminal is − 1

2VDC . Therefore, theoutput of a single leg has two values. Therefore with three legs we have 23 =8 possible unique output voltage combinations, corresponding the 8 differentpossible switching combinations.


+Z

e

DC link

Modulator

Reference waveform

+

Approximatefundamental

Carrier waveform

Figure 10.5: Single leg of inverter and the PWM waveforms.


A notation that we shall use is that the leg switching states are representedby a binary value – a ‘1’ denotes that the top switch of a leg is closed, and thebottom switch is open, and a ‘0’ denotes that the top switch is open and thebottom switch is closed. Therefore, the possible switching combinations, withthe phase leg voltages with respect to the mid link ground point (denoted as“g”), and the line-to-line voltages across a three phase load (such as that inFigure 10.4) are shown in Table 10.1.

Switch pattern abc vag vbg vcg vab vbc vca

0 0 0 − 12VDC − 1

2VDC − 12VDC 0 0 0

0 0 1 − 12VDC − 1

2VDC12VDC 0 −VDC VDC

0 1 0 − 12VDC

12VDC − 1

2VDC −VDC VDC 00 1 1 − 1

2VDC12VDC

12VDC −VDC 0 VDC

1 0 0 12VDC − 1

2VDC − 12VDC VDC 0 −VDC

1 0 1 12VDC − 1

2VDC12VDC VDC −VDC 0

1 1 0 12VDC

12VDC − 1

2VDC 0 VDC −VDC

1 1 1 12VDC

12VDC

12VDC 0 0 0

Table 10.1: Switching combinations and associated phase and line-to-line volt-ages.

Remark 10.3 Note from Table 10.1 that the line-to-line voltages always addtogether to be zero (similar to line-to-line voltages in a sinusoidal three phasesystem).

Remark 10.4 Note also from Table 10.1 that two of the switching states leadto zero line-to-line voltages. These two states correspond to all the top switcheson, or all the bottom switches on. These switching combinations lead to a shortcircuit across the three phases.

The phase voltages – i.e. van, vbn, vcn are also of interest. Let us considerswitching state 001 as an example. In this case we have:

vab = van − vbn = 0 (10.1)vbc = vbn − vcn = −VDC (10.2)vca = vcn − van = VDC (10.3)

One can immediately see from (10.1) that van = vbn. However, these equa-tions are not independent, and therefore one cannot solve for the phase voltages.

If one considers the three phase load to be a passive one of the form shownin Figure 10.4, then one can write, unisng Kirchoff’s voltage law, the followingexpressions:

va = iaZ + vn (10.4)vb = ibZ + vn (10.5)vc = icZ + vn (10.6)

Adding these equations together we can write:

vag + vbg + vcg = (ia + ib + ic)Z + 3vn (10.7)


Because the load is star connected then we know that:

ia + ib + ic = 0 (10.8)

and hence (10.7) becomes:

vag + vbg + vcg = 3vn (10.9)

∴ vn =13(vag + vbg + vcg) (10.10)

Using (10.10) one can therefore write the following expressions for the phase-to-neutral voltages:

van = vag − vn =23vag − 1

3vbg − 1

3vcg (10.11)

vbn = vbg − vn =23vbg − 1

3vag − 1

3vcg (10.12)

vcn = vcg − vn =23vcg − 1

3vag − 1

3vbg (10.13)

Using equations (10.11), (10.12) and (10.13) together with the values for thevoltages vag, vbg and vcg in Table 10.1 one can write all the values for the phasevoltages that can be produced by the inverter. These appear in Table 10.2.

Switch pattern abc vag vbg vcg van vbn vcn

0 0 0 − 12VDC − 1

2VDC − 12VDC 0 0 0

0 0 1 − 12VDC − 1

2VDC12VDC − 1

3VDC − 13VDC

23VDC

0 1 0 − 12VDC

12VDC − 1

2VDC − 13VDC

23VDC − 1

3VDC

0 1 1 − 12VDC

12VDC

12VDC − 2

3VDC13VDC

13VDC

1 0 0 12VDC − 1

2VDC − 12VDC

23VDC − 1

3VDC − 13VDC

1 0 1 12VDC − 1

2VDC12VDC

13VDC − 2

3VDC13VDC

1 1 0 12VDC

12VDC − 1

2VDC13VDC

13VDC − 2

3VDC

1 1 1 12VDC

12VDC

12VDC 0 0 0

Table 10.2: Switching combinations and associated phase and phase-to-neutralvoltages.

Remark 10.5 Adding together equations (10.11),(10.12) and (10.13) one gets:

van + vbn + vcn =23(vag + vbg + vcg) −

13(vag + vbg + vcg) −

13(vag + vbg + vcg)

(10.14)

∴ van + vbn + vcn = 0 (10.15)

Therefore the phase voltages always add to be zero, regardless of the appliedvoltages, when the three phase load is passive. It can be shown that this alsoapplies if there are three phase sinusoidal voltage sources in the load as well.

Remark 10.6 The neutral voltage of the three phase load moves around relativeto the ground at the mid point of the DC link. Consider the extreme cases ofswitching patterns 000 and 111. For 000, using (10.10) and substituting for thevoltages from Table 10.2 one can see that vn = − 1

2VDC . Similarly for the caseof 111 we get vn = 1

2VDC . Therefore the neutral voltage has moved around byVDC . These large voltage excursions in the neutral can cause bearing currentsto flow when electrical machines are the load on the inverter.


10.2.1.1 Space Vectors and PWM

If an electrical machine is used as the load on an inverter, then space vectorscan be used to represent the phase voltages. These pahse voltages are appearingacross the phases of the machine. Almost all AC machines are wound so thattheir windings are sinusoidally distributed in space. This fact allows a “spacevector” concept to be used to represent currents, fluxes, mmfs, and voltages inthe machine. Refer to [4, 20] for more detail.

In this concept, currents, voltages, fluxes and mmfs are considered to besinusoidally distributed in space. As an example, if one has a sinusoidally dis-tributed winding in an AC machine, and this winding is fed with a DC current,then the mmf is sinsusoidally distributed around the periphery of the AC ma-chine.

Remark 10.7 It can be shown that if we have three phase sinusoidally spatiallydistributed windings, fed with three phase temporal sinusoidal currents, thenone ends up with a spatially sinusoidally distributed resultant mmf that movesaround the machine at the electrical supply frequency. This can be representedas a single vector that is rotating with an angular velocity of ω (the electricalsupply frequency).

(100)

(110)(010)

(011)

(001) (101)

1V

2V3V

4V

5V 6V

(000)(111)

7V

8V

av

bv

cv

dcV

ABC

A B C

1

2

3

4

5

6

Figure 10.6: Switch positions and the resultant voltage space vectors.

The reason for introducing the space vector concept here is because it isconvenient to use this concept to represent the output voltages for an inverter.Figure 10.6 shows the space vector diagram for the various switch positionsfor the inverter. The length of the space vector corresponds to the maximum


phase-to-neutral voltage for each phase – i.e. 23VDC . Notice that there are six

active vectors that can be spaced around a machine every 60 electrical.

Remark 10.8 Although the space vector concept comes about because of thespatial properties of machine windings, it is often used in situations where thisdoes not exist. For example, in Figure 10.3 we have a passive load consisting ofimpedances, and we can use the space vector concept to represent the voltageson this circuit. I will not, in this brief introduction, go into detail as to why thiscan be done, suffice to say that it is due to the very close relationship betweenspace vectors and temporal phasors in circuits.

Space vectors can be used as a basis for a different type of PWM, calledSpace Vector PWM (SVPWM). The basis of this PWM strategy is the realisa-tion that three phase temporal sinusoidal voltages lead to a spatially rotatingvoltage vector in a three phase sinusoidally wound machine (as noted previ-ously). However, with an inverter we do not have infinitely variable voltagesthat we can apply to each phase, and therefore we can switch the inverter so thatat any instant of time we can, in an average sense, produce a desired voltagevector.

T

T/2 T/2

0

1

0

1

0

1

A

B

C

0 0

0 00 0

0 00 00 0

1 11 11 1

1

1

1

1

1 1

t0

t1

t0

t0

t0

t1

t2

t2

Figure 10.7: Switching waveforms for double edge pulse width modulation.

In order to develop a PWM strategy using space vectors let us define α as theduty cycle for a vector. Consider Figure 10.7 which shows the switching wave-forms to generate a particular voltage vector. One can see from this diagramthat the same switching pattern is generated symmetrically around the centre ofthe PWM period. By reading vertically one can determine the switching statesfor this switching sequence – they are 000, 100, 110, 111, 111, 110, 100, 000 –i.e. we are switching between vectors V8, V1, V2, V7, and then the reverse. Thevector nomenclature appears in Figure 10.6. As one can imagine this wouldlead to an average vector somewhere in between V1 and V2, the length of thevector being controlled by the duration of the zero vectors V7 and V8. The dutycycle for each of the vectors is simply the total time of the vector divided bythe control period time T . For example, the duty cycle for the V1 vector is:


α1 =2t1T

(10.16)

Similary one can defined the duty cycle for V2. Using this notation, if onlythis vector and the zero vector was switched during an interval of T then theaverage voltage vector magnitude produced over the interval is α1VDC volts.

Note 10.1 Space vectors are defined (for reasons that I shall not elaborate onhere) as 2

3 the amplitude of the resultant vector in the machine. For a threephase machine this means that the maximum voltage vector magnitude is thesame as the peak voltage that occurs across the phases. It is this correspondenceof the voltage vectors with the phase voltages that is one of the main reasons forusing this convention.

Remark 10.9 A further comment on note 10.1 – one can resolve the spacevector onto three axes 120 apart and get the instantaneous value of the voltageon the respective three phase axes. The same logic applies to the current vector.

d

q

1

Desired voltagevector

V1

d

q

V2

21

t

22

t

60

Figure 10.8: Switching time determination.

One of the very convenient features of vectors is that one can take orthogonalcomponents of them – i.e. one can not only resolve the vectors onto the 120

axes but one can also resolve them onto 90 axes.Consider the situation depicted in Figure 10.8. This shows a desired voltage

vector. Note that we have not considered what limits there are on the lengthof the voltage vector that can be produced by this system. We do know thatthe limit if the voltage vector lies on one of the natural vectors that can beproduced by the inverter is 2

3VDC .One can consider the vector in Figure 10.8 is a normalised vector (i.e. divided

by 23VDC), and hence αd and αq are the normalised orthogonal projections onto


Condition for sector Firing order t0 t1 t2

Sector 1 αd > 0; αq ≥ 0; αq <√

3αd V8V1V2V7V7V2V1V8T4 (1 − αd − αq√

3) T

2 (αd − αq√3)

αqT√3

Sector 2 αq > 0; αq ≥√

3 |αd| V8V3V2V7V7V2V3V8T4 (1 − 2αq√

3) T

2 (αq√

3− αd) T

2 (αd +αq√

3)

Sector 3 αd < 0; αq ≥ 0; αq <√

3 |αd| V8V3V4V7V7V4V3V8T4 (1 + αd − αq√

3)

αqT√3

−T2 (αd +

αq√3)

Sector 4 αd < 0; αq < 0; αq >√

3αd V8V5V4V7V7V4V5V8T4 (1 + αd +

αq√3) −αqT√

3T2 (−αd +

αq√3)

Sector 5 αq < 0; |αq| ≥√

3 |αd| V8V5V6V7V7V6V5V8T4 (1 +

2αd√3

) −T2 (αd +

αq√3) T

2 (αd − αq√3)

Sector 6 αd > 0; αq < 0; |αq| <√

3αd V8V1V6V7V7V6V1V8T4 (1 − αd +

αq√3) T

2 (αd +αq√

3) −αqT√

3

Table 10.3: PWM firing times for various sectors

a set of orthogonal dq axes. If we apply vector V1 for 2t1 seconds, and V2 for 2t2seconds then the desired normalised vector, in an average sense, is obtained.

It is possible to show, from the geometry of this situation, that for a given setof normalised orthongal vectors αd and αq the switching times for the vectorsin sector 1 of the PWM star are:

t1 =T

2(αd − αq√

3) (10.17)

t2 =αqT√

3(10.18)

t0 =T

4(1 − αd − αq√

3) (10.19)

where the various t values are defined in Figure 10.7. If a similar analysis iscarried out for all the sectors then one can get a complete set of switching timesas shown in Table 10.3.

Another important aspect that was eluded to earlier was that there is limitingof the resultant space vectors. For example, one cannot ask for αd = 1 andαq = 1, since this would be asking for a resultant space vector that is larger thanthat which can be obtained given the vectors that the inverter can produce. Ifone applies the expressions from Table 10.3 to such a situation then this problemmanifests itself by the condition [21]:

2t1T

+2t2T

> 1 (10.20)

or:αd +

αq√3

> 1 (10.21)

in the case of sector 1 limiting. Clearly (10.20) means that the total switchingtime of the active vectors exceeds the total control period.

It can be shown that the limitations imposed by the available firing timesresult in a hexagon limit. This is shown in Figure 10.9. If a desired vectorexceeds the limit hexagon, then it has to be limited to the hexagon [21].

If the times are to be scaled so that they add to give one, then we require:

γ

(2t1T

+2t2T

)= 1 (10.22)

or:γ =

1αd + αq√

3

(10.23)


(100)

(110)(010)

(011)

(001) (101)

(000)(111)

2

3 1

6

5

4

Limit hexagon

Limit circle

V1

V2V

3

V4

V5 V

6

V7

V8

Figure 10.9: Voltage limit hexagon.

Remark 10.10 Note that the use of the γ on both the total times means thatthe angle of the resultant vector is preserved.

The new limited firing times for sector 1 are now:

2t1lim = 2t1γ (10.24)2t2lim = 2t2γ (10.25)

The 1/γ values for all the sectors are summarised in Table 10.4.

Remark 10.11 Space vector based PWM is particular amenable to implemen-tation in digital form. This can be contrasted with carrier wave based PWM,which was originally devised for analogue implementation. Of particular impor-tance is that this technique does not involve the solution of any transcendentalequations, and it does not involve the use of any trigonometric functions.

Sector 1/γ

1 αd + αq√3

2 2αq√3

3 αq√3− αd

4 −(αd + αq√3)

5 − 2αq√3

6 αd − αq√3

Table 10.4: Voltage limit γ’s


Remark 10.12 Another interesting feature of space vector PWM is that themaximum amplitude of the fundamental that can be produced by the techniqueis larger, by approximately 15%, than that produced by carrier based sinusoidalPWM. A similar effect can be obtained in sinusoidaly PWM by putting a thirdharmonic in the reference waveform.

10.2.2 Dead-time Issues

An important practical issue that arises with “totem pole” inverter legs is theproblem of “shoot through”. This term refers to the phenomena of both the topand bottom device being momentarily on when there is a switching transitionfrom the top to the bottom device, or vice-versa.

Remark 10.13 The “shoot through” problem also exists in low power digitalcircuits. One may recall from Chapter 1 that CMOS and TTL both suffer from“shoot through”. In the case of digital systems the shoot through is a very shortperiod of time, and the power levels involved are low. Consequently the problemcan be tolerated. However, in high power inverter systems the devices will failif “shoot through” occurs.

Shoot through is overcome by making sure that the outgoing device is turnedoff before the incoming device turns on. This is achieved in practice by manip-ulating the device signals that turn the devices on and off.

ThreePhase

Input/Output

DCBus

Input/Output

+

-

Phase ALeg

Phase BLeg

Phase CLeg

Initial current

Final current

iai

ibi

iaf

ib

f

Figure 10.10: Inverter showing the initial and final current flow after a leg isfired.

The turn off of a power device is not instantaneous due to the phenomenaof charge storage in the devices. In order to give the device time to turn offbefore turning on the other device in the a small delay (typically of the orderof 3 to 4µsecs for todays IGBT devices) is allowed between the turning off ofone device and the truning on of the other. This delay results in a differentvoltage being applied to the machine compared to that being demanded by thecontrol. This is due to the fact that the dead-time delay results in a shift of theswitching edges.

The dead-time error problem is a little more complicated than I have out-lined above. The presence of the dead-time switching delay is actually variable


Leg Bcurrents

Leg Acurrents

Leg Bswitching

Leg Aswitching

Top

Top

Top

Top

Bot

Bot

Bot

Bot

On

On

On

On

Off

Off

Off

Off

ibi

iai

i ib b

f i

i ia af i

0

0

0

0

Dead - time Td

Dead - time Td

Desired switching pointand actual switching point

Desired switching point

Actual switching point

Figure 10.11: Example of dead-time induced switching error in an inverter.


depending on the direction of the current through the inverter leg. The follow-ing discussion is with reference to Figures 10.10 and 10.11. Figure 10.10 showstwo legs of an IGBT based inverter, with the current flowing out of leg A andinto leg B. Figure 10.11 shows the effects of the current direction on the actualtime of switching. As can be seen when current flows out of a leg (i.e. leg A) theactual time of switching is the desired time of switching. Therefore the dead-time of the inverter does not cause a problem. However, when current is flowinginto a leg (i.e. leg B) then the switching time is delayed by the dead-time.

Therefore, if one wishes to compensate for the dead-time so that correctswitching always occurs, one should sense the current direction and compensatethe switching time as appropriate. However, because the compensation of theswitching time has to occur in the control interval before the interval it is goingto be applied, then there is the possibility that the current direction may beincorrect. This situation only occurs around the times that the fundamentalcurrent is about to change direction. The result of incorrect compensation isthat the cross-over of the current through zero may be considerably distorted –even more than if compensation is not being applied. This issue has not beenresolved.

10.2.3 Some Inverter Applications

In this subsection we shall consider some of the applications for inverters. Thepresentation is by no means exhaustive, and the more common applications willbe highlighted.

10.2.3.1 Variable Speed Drives

One of the most common applications of inverters are in AC variable speeddrives. These drives are most commonly based on the use of induction machines.

Figure 10.3 shows the generic layout of an AC drive. As mentioned in sec-tion 10.1 Converter 1 in this figure is often a uncontrolled three phase rectifier(although if the supply is single phase then one could have a single phase recti-fier). Converter 2 is a conventional inverter, much as shown in Figure 10.4. Atlow powers and voltages the power devices in the inverter can be MOSFETs.At small to medium powers, the IGBT has become the device of choice. Therange of operation of the IGBT is extending all the time in terms of the currentsand voltages that can be handled. At the time of writing these notes IGBTsare available with maximum voltages of 6kV, and current capabilities in thethousand of amps range.

Variable speed AC drives are becoming ubiquitous devices these days. Theycan be found in anything from domestic air conditioners, washing machines andmicrowave ovens, right through to large drives in power station bag houses androlling mills. If better power sources are found, then AC drives will become veryprevalent in vehicular transportation. They are currently widespread in traintransportation.

The main driving factors towards the increasing use of inverters are:

1. The simultaneous arrival of low cost high performance microprocessors,as well as reliable, robust and reasonable cost power electronic devices inthe since the mid 1990s.


2. The refinement of the control algorithms for AC machines allowing highperformance from AC drives.

3. A community demand for more efficient use of energy.

Let us briefly consider a few of the applications mentioned above. It is notuncommon to hear in advertisements for air conditioners that they are inverterair conditioners. The inverter in these air conditioners are being used to drivethe compressor in a variable speed mode. Normally an air conditioner is drivenin an on-off mode, controlled by a thermostat. The reason for going to a variablespeed mode is that the compressor is much more efficient in this mode. When acompressor starts for the next 30 to 60 seconds it is not really pumping any heat,but simply compressing the refrigerant. If the compressor is being started andstopped on a regular basis this non-productive time will be a significant part ofthe total operating time of the compressor. Under variable speed operation thethermostat simply controls the speed of the compressor, but it does not stop.Therefore the refrigerant does not have to be re-compressed, since it does notdecompress whilst the compressor is running, albeit more slowly. Inverter airconditioners can be up to 30% more efficient as compared to the traditional on-off air conditioner (depending on operating cycle of the on-off air conditioner).

Another domestic applicance that now has an inverter in it is the microwaveoven. The inverter is used to supply variable voltage to the magnetron, andtherefore get true variable power instead of pulsed on-off 100% power as in aconventional oven. This is main motivated by better cooking performance at lowpower levels. In actual fact the so-called inverter circuit in a microwave oven ismore like a flyback switch mode power supply circuit. The switch mode supplycan be operated at high frequency, and therefore allow a smaller high frequencytransformer to be used. In addition, the output voltage and/or current can becontrolled allowing completely variable, constant power from the magnetron.

10.2.3.2 Grid Connected Applications

As the power electronic devices improve in voltage rating, grid connected ap-plications of inverters are becoming more common. The classic example of theuse of an inverter in a grid connected application is interfacing photo-voltaicsto the grid.

In a photo-voltaic interface, the solar cells are producing DC voltage whicheither has to be converted into AC to feed the utility grid, or converted to AC tosupply domestic AC appliances. Both of these are classic inverter applications.In some situations the output of the solar cells will firstly be fed to a bank ofbatteries for storage. It is then the DC in the batteries that is converted to AC.In other situations, the DC from the solar cells may be fed directly into the gridwithout the intermediate batteries (see Figure 10.12). This is the situation thatis common for non-remote properties that are connected to the main utility gridsupply. The inverter is its associate controller can either deliver power to thegrid, or take power from the grid, depending on the insolation falling on thesolar cells. In the case of remote properties, there in many cases will not be autility supply, and the inverter would be powering the household appliances.

A more industrial application of inverters is the static var compensator(SVC). A compensator is a device that can be connected to the power sys-tem to provide voltage support for the supply, especially at the end of long


Inverter

DC AC

Utilitysupply

Controller

Photo-voltaicsolar cells

Domesticload

Figure 10.12: Generic non-battery based photo-voltaic supply system.

Statcom

Static Synchronous SeriesCompensator (SSSC)

Unified Power Flow Controller (UPFC) Back-to-Back Statcom

Figure 10.13: Some grid connected FACTS units offered by Siemens.


transmission lines. This is achieved by the compensator being a variable ca-pacitor. Traditionally this was achieved by using a synchronous machine, andvarying the excitation to vary the apparent capacitive load represented by themachine. Later banks of switchable capacitors were used, the switching beingachieved by thyristors. More recently a traditional inverter has been used. Thiscircuit has the significant advantages over the previous techniques – injects lessharmonics into the supply, very rapid bumpless changes can be achieved, cancompensator for general power factor (i.e. can perform an active filter func-tion). Figure 10.13 shows some variants of the static compensator (STATCOM)offered by the Siemens company. Some of these devices do more than simplestatic var compensation, and are capable of real poer flow control as well asreactive power flow control. AC transmission systems that include these powerelectronic devices are known as Flexible AC Transmission Systems (FACTS).

10.3 Multilevel Converters and Applications

To be completed.

10.4 Matrix Converters

To be completed.

Part IV

Appendices

Appendix A

List of Course Materials

The supplementary course materials for the course for 2003, which are issuedas separate documents, are:

1. The course handout (slightly varied version included in notes).

2. The course schedule (included in notes).

3. A Saber tutorial sheet (included in notes).

4. Assignment/Laboratory 1 (included in notes).

5. Assignment/Laboratory 2 (included in notes).

6. Exam 2000 (with solutions).



These materials are handed out in class. They are also available from thefollowing website:

http://www.eecs.newcastle.edu.au/users/staff/reb

364 List of Course Materials

Appendix B

Course Outline

B.1 Text

These notes written by the Lecturer. Further information and clarification ofissues presented in the course can be found in the references listed in the Bibli-ography at the end of these notes.

B.2 Introduction

This subject covers a wide variety of issues related to switching in electronic sys-tems. The issues range from switching in digital systems to switching in switchmode power supplies and high power converters. The emphasis throughout thecourse will be on practical design related issues.

The switching in digital systems will consider issues such as: logic familiesand their interfacing, signal propagation in digital systems, transmission linesand digital systems, cross talk mechanisms, printed circuit board issues, inter-board cabling and measurement techniques.

The switch mode power supply section of the course will consider the stan-dard buck and boost switch mode configurations, and various combinations ofthese types. The presentation will necessarily be brief, but where possible rel-evant practical issues will be highlighted. Practical design issues will also beconsidered.1

The final section of the course is on high power line commutated convertersand hard switched inverters. This section will begin with an introduction to thesemiconductor devices used at these power levels, since these dictate the types ofapplications for this equipment. The basic operation principles of single phaseand three phase converters will be presented. There will be a brief introductionto the concepts power factor and harmonic control in rectifier circuits. Someother power electronic devices and their applications will be introduced.

1Due to time considerations, the chapter on the practical design of switch mode powersupplies will not be part of the course.

366 Course Outline

B.3 Course Objectives

This course has the following objectives:

1. To give the student a basic understanding of digital logic families andinterfacing between different logic families.

2. To demonstrate the importance of switching edge times on the design ofdigital systems.

3. Students should understand the various digital line termination techniques,and how to apply them in practical design.

4. To give an understanding of the various cross talk mechanisms, how toidentify them, and how to minimise them in practice.

5. Establish the basic principles behind good ground plane design for printedcircuit boards.

6. Understand the non-ideal behaviour of passive components when used inhigh speed digital systems, and how design must be changed to accountfor this behaviour.

7. Establish the parameters of the non-ideal behaviour of wiring interconnectand how design must be compensated to account for this.

8. Give a basic understanding of the fundamental switch mode converters.

9. Investigate the comparative performance of different switch mode topolo-gies.

10. Very basic understanding of the control strategies for switch mode powersupplies.

11. Introduction of the semiconductor components used in high powered linecommutated converters and hard switched inverters.

12. Basic analysis of the converters.

13. Consideration of power supply quality issues in rectifier circuits.

Assessment

The subject will have two assignment/labs worth a total of 40% of the final mark.There is a mid semester quiz worth 10%. The examination at the end of thesemester contributes the remaining 50% to the final mark. The assignments areintended to be done individually, although discussion of concepts and approacheswith colleagues is permissible. Assignments that are copied will be given zero.

B.4 Plagiarism 367

B.4 Plagiarism

A student plagiarises if he or she gives the impression that the ideas, words orwork of another person are the ideas, words or work of the student2.

Plagiarism includes:

• copying any material from books, journals study notes or tapes, the web,the work of other students, or any other source without indicating thisby quotation marks or by indentation, italics or spacing and without ac-knowledging that source by footnote or citation;

• rephrasing ideas from books, journals, study notes or tapes, the web, thework of other students, or any other source without acknowledging thesource of those ideas by footnotes or citations; or

• unauthorised collaboration with other students that goes beyond the dis-cussion of general strategies or other general advice.

Plagiarism is not only related to written works, but also to material such asdata, images, music, formulae, websites and computer programs.

Aiding another student to plagiarise is also a violation of the PlagiarismPolicy and may invoke a penalty.

For further information on the University policy on plagiarism, please re-fer to http://www.newcastle.edu.au/policy/academic/general/academic-integrity policy new.html

B.5 Special Consideration

A candidate who claims that – study during the year or preparation for anexamination; or study during the year or preparation for an examination; orattendance at or performance in an examination has been affected by illness,disability or other serious cause, may report the circumstances in writing, sup-ported by medical or other appropriate evidence to program co-ordinator andrequest that they be taken into account in the assessment of the examinationresults of that candidate. Such request shall be made on the prescribed form.

For further information on the University policy on Special Consideration/SpecialExaminations and Appeals, please refer tohttp://www.newcastle.edu.au/policy/academic/adm prog/exams.htm

B.6 Changing Your Enrolment

HECS Census Dates (last dates to withdraw without financial or academicpenalty) are for Semester 1 – March 31, and for Semester 2 – August 31. Ifyou don’t want to continue with the course then make sure you withdraw priorto these dates. To change your enrolment online, please refer tohttp://www.newcastle.edu.au/study/enrolment/change-enrol.html

2“Plagiarised” from the official University of Newcastle policy on plagiarism.

368 Course Outline

B.7 Support Services

The Faculty Student Services Office is located on the entry level of buildingEF. If you have issues with enrolment then they can provide valuable advice.For other issues there is a Faculty “Omsbudsmen” who can provide assistance.His name is Dr Karl Bretreger located in room EA122. Other support servicesare offered by the The Dean of Students, Professor Anne Graham, located onLevel 3 of the Student Services building. For more detail on the student supportservices offerd in the University Student Support Unit, refer to:http://www.newcastle.edu.au/intranet/student/support-services/index.html

Appendix C

Course Schedule

Week Dates Event Lecture Material

119/7–23/7L: 19/7L:21/7

Properties of digtal logic –CMOS, TTL. Interfacingof logic families, fanout,logic levels. Introductionto digtal switching.

226/7–30/8L:26/7L:28/7

Handout Sabertutorial exercise

Digital knee frequency,transmission lines, kindsof reactance,capacitivecross coupling, induc-tive coupling, inductivecrosstalk, dv

dt and didt

effects, ground bounce,measurement issues.

32/8–6/8L:2/8L:4/8

Brief review of second or-der circuits and trans-mission lines, point topoint wiring and trans-mission lines in difitalsystems, reflections, ter-mination techniques, dis-tributed cross coupling,skin and proximity effects.

49/8–13/8L:9/8L:11/8

Assign 1/Lab 1out

Diode terminations,uniformly loaded lines,printed circuit board de-sign, multi-layer boards,decoupoing issues, whatis a good capacitor?, vias,zoning issues.

516/8–20/8L:16/8L:18/8

Fundamental switch modetopologies – buck, boost,Cuk

.

continued next page

370 Course Schedule

continued from previous pageWeek Dates Event Lecture Material

623/8–27/8L:23/8L:25/8

Full bridge converters,analysis of basic convertertopologies.

7 30/8–3/9 No lectures thisweek!

Directed reading on con-verter topology analysis.Comparison of topologies.

6/9–10/9L:6/9 (Nolecture!)L:8/9

12 hr Quiz

Switch mode power sup-plies, isolated convertertopologies.

13/9–17/9L:13/9L:15/9

Introduction to controltechniques for switchingpower supplies.

1020/9–24/10L:20/9L:22/9

Assign 1 inAssign 2 out

Introduction to highpower switching devices.

27/9–8/10 Mid-semesterbreak

No lectures

1111/10–15/9L:11/10L:13/10

Review of Fourier analy-sis, generalised power fac-tor

1218/10–22/10L:18/10L:20/10

Basic rectifier cir-cuits,Single phase unitypower factor rectifiers

1325/10–29/10L:25/10L:27/10

Three phase rectifiers, re-view of course

1/11-5/11StuvacAssign 2 in No lectures

8/11–26/11

Exam period

Appendix D

Introductory Exercise usingSaber Simulator

D.1 Introduction

Saber1 is a software simulation program. Its main attribute is that it allowsthe simulation of mixed mode systems – i.e. one can have continuous timeanalogue circuitry, digital circuits, continuous and discrete time transfer func-tions, magnetic systems (such as electrical machines and magnetic actuators),mechanical systems, and hydraulic systems all in the same simulation. This isunusual since most simulation packages cannot readily handle this mix of sys-tems. They tend to be more specialised – i.e. only for electronic circuits, onlyfor power systems, digital simulation packages etc.

Simulation packages are very useful for the simulation of electronic systems,since the models of electronic components behave nearly the same as the actualcomponent. In some circumstances simulation is almost mandatory, since apoor design can result in immediate catastrophic failure of the real circuit. Anexample where this is often true is in the area of power electronics.

The Saber simulator consists of four major components:

• SaberSketch: This provides a means to graphically enter a schematic tobe simulated.

• SaberGuide: To some degree this component is hidden, since it providesthe connection between SaberSketch and the Saber Simulator.

• Simulator: This module is the actual simulation engine. It is activatedvia SaberGuide.

• SaberScope: This is the back end postprocessing section of the Sabersystem. SaberScope allows the user to process the files produce by theSaber simulator and produce new files of results, but more importantly itallows the user to generate graphs of the results.

In this introductory exercise we shall be using the Saber simulator for circuitsimulation. The circuit to be simulated is a very simple one, but it is able to

1Saber is a registered trademark for Avant!

372 Introductory Exercise using Saber Simulator

vS

vd

vL

vR

L

R

i

Saber groundnode

Figure D.1: Simple single phase, half wave rectifier, with an LR load.

demonstrate many of the features of the software. In order to minimise thesimulation times we shall be using idealised components from the Saber partslibrary. If one wanted to work out the power dissipation in semiconductorcomponents then the more realistic real component libraries would have to beused, but use of these makes the simulation times considerably longer.

The circuit to be simulated is shown in Figure D.1. It is a simple singlephase half wave rectifier circuit. The only complication is that it has a loadthat includes inductance.

D.2 Circuit Schematic Capture

The first step in the circuit simulation process is to capture the circuit schematic.This is achieved by using the SaberSketch section of the Saber suite. Figure D.2shows the initial screen that appears when SaberSketch is invoked (via the Startmenu).2

The sequence of steps to follow to set-up a design are as follows.

Create the design: This is achieved by selecting the File→New→Design pull-down menu. If we wanted to open an existing design then one would use

2The drawing area is shown in white in this figure. This has been done to prevent tonerwastage when this document is printed.

D.2 Circuit Schematic Capture 373

Partsmenu

Zoomingcontrols

Gridcontrol

Select todraw a line

Invoke SaberGuide

Figure D.2: Initial screen upon invoking SaberSketch.

Open→Design, and then navigate to the desired file. Often if SaberSketchstarts it will load the last design file automatically.

Place parts on the schematic: The next step is to place the desired com-ponents on the blank schematic. The is achieved using the Parts Gallerybutton. When clicked-on this opens up another window which allows oneto select the parts folder to be used. The folder that you will use for thisexercise is the Analogy Parts Library. If one double-left-clicks on this thenthe contents of the Available Categories window will change to a selectionof component categories. One can select a category, eventually endingup with a listing of individual parts in the Available Parts list scroll win-dow. An example of this window is shown in Figure D.3, which shows thecontent of the Inductors & Coupling component category.

To place a component in the schematic one selects a particular componentfrom the Available Parts window and then click-on Place. The componentwill then appear in the middle of the schematic window. An alternativeis to left-click-on the part and then go the to schematic window and clickthe middle mouse button (if there is one).3

One can also access the Parts Gallery via using the right mouse buttonselecting Get Parts→Parts Gallery, or from the Schematics main menu.

As a specific example, if we want to place a diode on the schematic

3Only works if a mouse driver that recognises the middle mouse button is installed.


Figure D.3: An example of a parts gallery screen.

then one navigates to the Analogy Parts Library→Electronic→SemiconductorDevices→Diodes category. From the Available Parts window select theDiode, Ideal (PWL) component and then press Place. If you look at theschematic you will find a green diode in the middle of it. The green colourindicates that the component is selected. If a component is selected thenit can be dragged around the schematic to position it where one likes bymoving the cursor pointer over it (the component then changes to red),pressing the left mouse button, and then dragging to the desired location.

Set a parts properties: Once a part is on the schematic then its propertiescan be set. This is carried out by double-left-clicking on the part (one canalso get the properties of the part by right clicking and then selecting theSymbol Properties on the drop-down menu). One can also obtain help ona part by selecting the Help drop-down menu from the properties screen.The Help explains the meaning and range of values for all the propertieslisted for the part.

The properties window contains three columns – Property Name, PropertyValue and a set of round buttons on the right that denote the visibility ofthe property on the schematic. The latter two of these can be altered bythe user. The Property Value fields can contain undef, or *req*. The undeffield usually means means that the value is undefined, but the part willexecute correctly with some underlying default value. However, in manycases this does not make sense. For example the resistor component hasundef for its value, and clearly one would wish to set the value of a resistorin a particular circuit. If an undef value has to be defined the simulatorwill let you know when you try to run the simulation. The *req* field

D.2 Circuit Schematic Capture 375

means that there are no default values defined, and it is mandatory todefine a value. The values of the components can be entered in two mainnumber formats. Saber uses a set of multiplier factors which are shownin Table D.1. One can of course use whole numbers, and also scientificnotation if desired – e.g. 25e-4 for 0.0025.

It should be noted that the ref property name contains a unique name forthe part on the schematic. Sometimes if a part is copied on the schematicthis name is not changed appropriately (this appears to be a bug in thesoftware). Therefore one gets duplicate part references, and consequentlythe simulation fails. One has to manually change the ref name if thisoccurs.4

The visibility field allows one to nominate whether the property value (thevisibility button is half on), or the property name and property value (thevisibility full on), are to be displayed on the schematic. If the button is“off” then nothing about that property is displayed on the schematic.

In a manner similar to the placement of the diode all the other componentsare placed on the schematic. The wires that join the components are drawnby moving the cursor over one of the component node points. The cursorwill change to a cross-hair and pressing and holding the left mouse buttonwill allow a wire to be drawn. There is a grid that wires and componentslie on, which makes drawing the lines very simple. If for some reason thecursor does not change (for examples one is drawing a line not connected toa component, then the wire drawing tool can be selected (see Figure D.2).A wire which does not terminate on a component node can be terminatedby double-left-clicking at the point where one wishes to stop the wire.

Place a Saber ground node: A schematic must contain a ground referencedesignator for the simulator to be able to function. This symbol is calledGround (Saber Node 0) in the parts library. This ground symbol can belocated in a number of places in the parts library tree. The ground isconnected to the point in the schematic from which all the voltages in thedesign will be measured.

Wires: We have already mentioned how to draw wires on the schematic. Onecan also select a wire and delete it by pressing delete on the keyboard, orright clicking and selecting Delete Wire on the drop-down menu. One canalso alter the properties of a wire by right-clicking on the selected wireand selecting Attributes... on the drop-down menu (see Figure D.4 for anexample of the Attributes... window). For example, one can change thename of a wire in the Name field in the window, and then select whetherthis name should be displayed on the schematic (which is often very handyfor documentation reasons).

Repeat the above steps until the complete circuit shown in Figure D.1 hasbeen drawn. At this point we are now ready to start the simulation phase ofthe exercise.

4A part can be copied by selecting the component and then moving the cursor to theplace where one wishes to have the duplicate component, and then clicking the middle mousebutton.


Name Scientific Notation Saber shortcutfemto 10−15 fpico 10−12 pnano 10−9 nmicro 10−6 umilli 10−3 mkilo 103 kmega 106 meg

Table D.1: Number magnitude specifiers in Saber

D.3 Executing the Transient Analysis

In order to carry out the simulation of a design one now has to invoke thesimulator. This is achieved by pressing the SaberGuide button (see Figure D.2).One then gets the screen shown in Figure D.5. Note the new toolbar at the topof the screen. This toolbar allows one to control the Saber simulator from theSaberSketch window.

The main tool used in SaberGuide is the DC/Transient button shown inFigure D.5. If one clicks on this button then the window shown in Figure D.6appears. The parameters circled should be filled out so that the end time andtime step of the simulation are set-up, and the simulator will automatically openSaberScope upon the completion of the simulation. One can see that there area number of other tabs on the window. In more sophisticated simulations someof these may have to be used. The only other one that we shall look at in thissimulation is the Input Output tab, which is shown in Figure D.7. The circledquantities have been altered from the default values. These alterations cause tosimulator to save all the signals in the design, and all types of variables (acrossvariables (i.e. voltages) and through variables (i.e. currents)).

Remark D.1 One can also select specific signals for the simulator to save. Thisis essential in large simulations otherwise the output files produced by the simu-lator are huge. The signals can be selected using the Browse Design... selectionfrom the Input Output→Signal List→Select sub-menu. Note that the simulatorhas to be running to carry out this function, therefore it is necessary to start asimulation and stop it (using the Stop button), and then reenter this menu tocarry out this function.

Once all this information has been filled out then one simply clicks OK at thebottom of the window and the simulation will begin. It firstly netlists the design,and if this is successfully completed it will work out the dc starting condition,and then finally start the transient analysis. A rotating icon in the top rightcorner of the Saber window indicates that the simulator is running. When itfinishes, which is very fast in the case of this simulation, the simulator willautomatically open up SaberScope to allow the results of the simulation to bepost-processed.

D.4 Plotting and Processing Results 377

Figure D.4: The wire attributes window.

D.4 Plotting and Processing Results

If SaberScope has not been set to automatically open then it can be openedmanually via the Results→View Plotfiles in Scope... menu item.

If SaberScope opens automatically it loads the plot file just generated by thesimulator (because of the setting made in the DC/Transient screen), and thendisplays the plot file opened in the Signal Manager window, and the signals inthis plot file in a second window named after the plot file. The SaberScopeopening window is shown in Figure D.8.

Notice in the Diode LR cct.tr signal window that some of the signals havea “+” next to them. This means that if one double-left-clicks on them thenanother more detailed signal list will expand from this root. One can then selectone of these signals to plot, and then left-click the Plot button. Figure D.9 showsthe inductor component expanded, and the i(m) signal plotted.

Remark D.2 From Figure D.9 one can see the advantage of naming signalswith meaningful names, as opposed to the default names given to the signals bySaber. The default names in the signal list window do not make much sense.When one is scanning through the signal list for complex designs, it is mucheasier to find the signals/components of interest if the names make sense.

If one wishes to plot a number of variables, then left-click the desired sig-nals holding down the Ctrl key on the keyboard, and then left-click Plot. Theselected signals will all be plotted on separate axes. One can also superimposeseveral plots on the one set of axes. This can be achieved in two different ways,


DC and transientanalysis button

Figure D.5: An example of SaberSketch with the Saber guide toolbar activated.

dependent on whether one has already plotted the signals on separate axes. Ifone wishes to plot two signals on the same axis then select one of the signalsand plot it, and then select the other, and go the the plot window and press thecentre mouse button over the graph upon which one wishes the second signalto be plotted.

The other way of plotting two or more signals on the same axis, is to firstlyplot the signals on separate axes, and then use the Stack Region feature. Thisis activate by selecting one of the signals to be “stacked” on the same axis (thisis achieved by placing the mouse cursor over the signal name to the right ofthe plot – the plot will go red, and then left-click), and then right-click and gothe drop-down sub-menu Stack Region. At the bottom of this flyout one cansee a number of Analog signals listed (the number dependent on the numberof signals plotted on the graph window), with Analog 0 being the one at thebottom of the graph window. Select the analog signal number that correspondsto the axis that one wishes to plot onto.

If one plots a signal and wants to delete it, then select the signal in the graphwindow, and then right click to get the drop-down menu and select the DeleteSignal option.

D.4.1 Manipulating Results

One of the very powerful features of the SaberScope system is its ability toperform calculations on the results of the simulation, and also to take accurate


Changed fields

Figure D.6: An example dc/transient simulation set-up window.

measurements on the waveforms produced.Let us firstly consider the calculation capability. The waveform calculator

allows one to subtract, add, multiply, divide, and perform a number of othermanipulations on signals. The calculator is activated by pushing the “Calcula-tor” button at the bottom of the screen. The signals that one wishes to carryout the calculations on are selected by left-clicking them in the signal window,and then middle clicking in the area just below the toolbar in the calculator.The signal name should appear in this window and the scrolling window imme-diately below it. The calculator works using reverse polish notation (like a HPcalculator), therefore before selecting an operation we need to select the twosignals to operate on.

In the example shown in Figure D.10, we have selected the inductor voltage(vl) and current (i), and then selected the multiply function of the calculator (*)– i.e. we are working out the instantaneous power flow into the inductor. The


Changedvariables

Figure D.7: The input-output table of the dc/transient analysis window.

result then appears in the top window of the calculator. We can then plot thisresult by left clicking the small graph icon at the extreme left of the calculatortoolbar.

In order to look at a waveform in more detail one can expand the horizontalor vertical axis by simply selecting the axis by left-clicking, and then holdingdown the button to extend a yellow bar along the region of the axis that onewishes to expand. One can do this more precisely by right-clicking on the axisof interest and then using the drop-down menu to carry out a more precisenumerical expansion of the axis (or alternatively go back to the original axisscaling).

In addition to expanding the axes using the mouse cursor, one can alsozoom in on the waveforms by simply clicking the mouse over the section of thewaveform of interest, and then dragging out a square marque over the area.This area will then be zoomed on the plot.


Figure D.8: The initial SaberScope window.

All plotted curves have properties that can be altered. This is achieved byselecting the plot of interest, and then right-clicking and selecting Attributes....The contents of the resultant window are self explanatory.

The other major facility that is of use for processing plots is the measurementtool. This is activate by left clicking the “Caliper” button at the bottom of theSaberScope screen. This tool allows one to measure the precise absolute values ofthe quantities on the screen, rise time of steps etc. There are too many featuresto document here, so it is suggested that you have a look at the features, andtry them to see what happens.

D.4.2 Fourier Analysis

The Fourier Analysis facility allows one to get frequency response plots for dataproduced by the simulator. A Fourier Analysis can only be performed after thesimulator has run, and therefore falls into the post-processing category.

In order to perform a Fourier Analysis one must firstly return to the Saber-Guide window (don’t close the SaberScope window, simply iconise it to keepit out of the way). The following steps are carried out to perform a FourierAnalysis on a periodic waveform.

1. Select the Analyses→Fourier→Fourier... menu.

2. The left window in Figure D.11 will show up. I have filled in some valuesfor this window. The Fundamental Frequency of the output waveforms isknown as it was set by the frequency of the sine wave source in the circuit.The 80 millisecond time next to the Period End dialogue indicates that weare to analyse the period of the output ending at 80 milliseconds. Finallythe Number of Harmonics stipulates the maximum number of harmonicsthat that analysis will calculate.


Figure D.9: A signal plotted in SaberScope.

3. Another tab in the Fourier window is the Input Output tab. Its contentsappear as the right window in Figure D.11. In this case I have set theSignal List to be /... which means all signals, and the Include Signal Typesis set to all, meaning that through and across variables are to be included.

4. Finally we left click OK or Apply and the Fourier analysis is carried outon the signals selected.

Remark D.3 If one is analysing a non-periodic waveform or a pulse then theFast Fourier Transform option should be used.

In order to plot the results of the Fourier analysis go back to SaberScopeand via the Signal Manager window open a file dialogue. One should see a newfile with a fou.ai pl extension. Click on this file and click on Open. Anothersignal list box should open with the signals listed for which frequency data isavailable. These signals can then be plotted in a fashion similar to the timedomain signals.

D.5 A Practice Exercise

In order to test your understanding of the above concepts it is suggested thatyou carry out the following on the circuit of Figure D.1. I suggest that you don’tblindly carry out the simulation, but try and understand what you are seeing inthe results. For a simple circuit, it has surprising results, and you might learnsomething!

1. Execute the simulation and plot graphs of vs, vR, vL and i.

D.5 A Practice Exercise 383

Figure D.10: An example of a waveform calculation in SaberScope.

2. Measure the average and rms load current from the plots.

3. Measure the average voltage across the inductor, and try and explain theresult.

4. Measure the voltage across the diode. What is the maximum reversevoltage it is subject to?

5. Plot graphs of the power dissipated in the load and the energy stored inthe inductor. Measure the average power dissipation.

6. Measure the ac source power, and compare this value with the value dis-sipated in the load resistor. Why is there a discrepancy?

Figure D.11: Fourier analysis dialogues in Saber.


7. Perform a frequency analysis of the rectifier output voltage and current.Why is the spectrum of the current different from that of the voltage?

8. Replace the load resistor with a 300 volt dc source. Plot vS , i and vL. Notethat current only flows for part of the half cycle of the voltage supply. Notewhere the peak current occurs.

9. Measure the average and rms values of the load current and voltage. Alsomeasure the average power transferred to the load. Note that the averageload power is now the product of the average current and average loadvoltage.

10. Perform a frequency analysis of the load current and voltage, and comparethe results with the resistive load case.

If the above exercise is carried out successfully then you should have a goodpreliminary working knowledge of the operation of the Saber simulation system.There are many other aspects of the system that we have not considered – youwill need to know these for more sophisticated simulations.

Acknowledgment

This tutorial is partially based on a Saber tutorial written by Dr. B.J. Cook ofthe Department of Electrical and Computer Engineering, University of Newcas-tle, Australia.

Appendix E

Assignment 1

Introduction

This is a combined theoretical assignment and practical laboratory.

This assignment/laboratory is a major assessment item for the course(worth 20%), and an appropriate time should be set aside for it.PLEASE start the assignment well ahead of the due date.

In planning the time, one needs to take into consideration the time consumingnature of simulation studies, and the availability of the laboratory equipment.

The assignment section mainly involves carrying out simulations of variousPCB terminations in the Saber simulation package. Saber is available in thePC laboratory on the top floor of building EE (i.e. EE107/108). Studentscan also install and run the software at home. In order to run the softwarereasonably one will need the following:

• At least 128Mb ram (this is the absolute mininum and the software willonly just run with this) – the more the better as Saber is very resourcehungry.

• At least 400 MB of disk space for the Saber installation. You will alsoneed approximatley 500MB of free space for swap on the disk.

• Windows NT 4.0, Windows 2000, or Windows XP (I have not attemptedto run the software on the Win95, Win98, Win Millenium systems. Isuspect that it will not work).

• An internet connect via modem or ADSL so that the licence server can becontacted to allow the software to run. Note that one must be connectedto the internet for the duration of the simulation session.

• The details of how to set up the environment variables so that the licencingwill work. These instructions should be included with the software.

If you don’t know how to use this package there is a demonstration exer-cise in the course notes appendix which you can do at your own leisure. This

386 Assignment 1

exercise will introduce you to the features of the Saber package needed for theassignment.

The laboratory section of the assignment is designed so that you can confirmthe results of the simulations using a special PCB that has appropriate tracesand terminations placed on it. There are only two sets of equipment availablefor these labs1, therefore the laboratory work will be carried out in an openlaboratory manner. This means that you can come in to the laboratory, at aconvenient time, and when the lab is open, and do the lab. It is quite OK forseveral students to do the lab together, but the interpretation of the resultsshould be carried out individually.

The equipment is very expensive, so please be careful during yourexperiments. Be particularly careful with the CRO probes, they arenot very robust!

Collaboration Policy

This assignment is meant to be an individual assignment. However, it is accept-able for students to discuss the assignment in order to understand what is goingon. However, each student should produce their own individual report with thesimulation and experimental results, with their own interpretation of the effectsthey observe.

I draw your attention to the copy of the institutional plagiarism policy in-cluded in the course handout.

E.1 How to Answer the Questions

In the questions below you are requested to carry out a number of simulationsand experiments. Associated with these are a number of explicit requests forexplanations of the results. Please follow the following guidelines:

• Could you please put a heading on these titled “Explanation for Q??.??”,highlighted, so that it is easy to located in the document.

• Could you please keep the answers short and to the point.

• Only include relevant plots.

If the above is followed then this assignment should not be too arduous.Don’t get carried away with doing hours and hours of simulation – the simula-tions required for the assignment should not take inordinate amounts of time tocomplete.

E.2 Software Tools to Aid Report Production

Most students will be generating their results in electronic format. There are anumber of techniques to include the diagrams for the simulations in your report.Saber itself has the ability to generate Postscript, jpeg etc. files. However, in

1The limiting factor is the expensive cathode ray oscilloscopes and signal generators re-quired.

E.2 Software Tools to Aid Report Production 387

the past its capabilities in relation to this have not always generated the resultsone would desire (I have not checked the very latest version). Often the filesproduced, especially Postscript files, are huge and very difficult to manage in aword processing program.

In order to aid the inclusion of diagrams students can download some soft-ware from my anonynous FTP server, at the following address in a Web browser:

ftp://eecsbobb.newcastle.edu.au

This is implicitly an anonymous ftp connection. If one connects using an FTPprogram, then the login requirements are (your input is boldfaced):

username: anonymouspassword: put in your email address

Once logged on, navigate to the Useful files directory. There are a numberof files here, such as MWSnap, which is a very nice freeware screen captureprogram2, IrfanView (a freeware viewer that also allows conversion of files togreyscale), Emacs (a public domain editor with LATEX aware mode), Miktex3

(a public domain version of the LATEX documentation system), Jpeg2ps (publicdomain converter for Jpeg files to Postscript), and several text editors.

SaberScope produces by default colour plots. However, most students willbe printing out their reports on black and white printers, therefore it may beadvantageous to have the plots generated as black and white. This can be doneby accessing the Graph→Color Map→Mono menu item. The actual lines of theplot will be converted to solid, dashed, dotted etc. lines. One can also rightclick select a plot and change these line styles as desired.

Question 1

Consider a fibre glass PCB that has a track width of 0.01 inch (which is a fairlytypical). The permittivity of the FR4 board material is εr = 4.5. The boardFR4 material is 0.063 inch thick (i.e. 1.6mm). The copper on the board is1oz per inch2, or 30µm thick. From these specifications calculate the L0 andC0 per cm parameters for the line (hint the expressions in the Useful FormulaeAppendix in the notes are useful for this, and pay attention to the limitationson physical dimensions for these expressions so that the right on is used).

The track is sitting on a ground plane PCB – this means that one canconsider that the ground return path has negligible inductance compared tothe track. Given these parameters construct a transmission line of length 30cmusing the Saber simulator. The line is being driven by a voltage source thathas a rise time of 800psec and a ∆V of 3 volts. Carry out the following virtualexperiments on this model of the transmission line:

a. Generate the time domain plot for the voltages on the line at the source,load end several intermediate points along the line with the line terminated

2This program allows one to capture any area of the screen and then save it to disk in avariety of different bit map file formats.

3This document and the Elec3230 notes have been written in LATEX.

388 Assignment 1

as an open circuit, short circuit (use a small resistance value for this ≈0.01Ω) and with its characteristic impedance. Explain the waveforms thatyou observe.

b. Change the termination approach to a source termination (as opposed toa load end termination) and plot the same results. Explain what you seeand what are the implications.

c. Allow another track to branch off the transmission line from the middlepoint. Initially make the two branch tracks the same length. Terminateboth tracks at the end with the characteristic impedance and generateplots for the same points as in item a. Try different length branches forthe tracks. Explain what you see from heuristic and theoretical viewpoints.How would you fix any problems observed?

d. Investigate the effects of a mid track capacitive load of 10pf on the per-formance of the transmission line with a load characteristic impedancetermination. Explain your observations.

e. Design a RC load termination and simulate under the same input wave-form conditions it to prove that it works correctly.

Hints

• Make sure that you choose the appropriate time scale for the plots yougenerate. For example, for a transmission line of the type specified abovethe propagation delay is of the order of 2nsec. Therefore, depending onthe question, time scales of 6 or 7 nsec in some instances, and between 12and 15 nsec in others are appropriate.

• The transmission line model should be constructed with the LC elementsrepresenting 1cm lengths of the line. This ensures that the model of theline is an adequate representation of the distributed nature of the line,whilst not over modelling the line and slowing the simulation, and gener-ating huge output files.

Question 2

Consider the situation of two printed circuit board tracks on a PCB with thesame parameters as in Question 1. These tracks are located 0.02 inch (or0.508mm) apart, so there is mutual capacitance and inductance between them.One of the tracks is being driven with the same input signal as in Question 1,with the driver modelled as a voltage source with 31Ω of output impedance(i.e. similar to a TTL or CMOS output impedance). It is terminated with itscharacteristic impedance. The other line is initially terminated at the near (i.e.the end near the source of the driving line) and far ends with its characteristicimpedance.

Set up a Saber simulation to model this. Assume that the mutual capac-itance is 0.1pF/cm, and the mutual inductance is 1nH/cm. For the followingsimulation results try and use theory to explain the results where possible.

Carry out the following virtual experiments:


a. Initially set the mutual capacitance to zero and consider what happenson the receiving PCB track at the terminations and mid points along theline.

b. Repeat the above with the mutual inductance equal to zero and the ca-pacitance equal to 0.1pF/cm.

c. Now carry out the same tests with the mutual inductance and capacitanceboth present. Which of the two effects is dominant in the response?

d. The situation thus-far is artificial in that the receiving line is terminatedat both ends with the line characteristic impedance. Now replace the lefthand termination with a short circuit and then repeat item a. Explain theresults.

Laboratory

The laboratory experiments will be carried out using a PCB with a groundplane, traces, and terminations place on it. The layout of the board is shownin Figure E.1. You will note that the board uses BNC connectors to connect tothe CRO. These connectors connect to the measurement points using the “homebrew” probe technique discussed in class.

The objective of the lab is for you to see that the effects discussed in class,and seen in the simulations, actually do occur in a real PCB trace. In addition,comparison of the simulation and experimental results will allow an assessmentto be made as to the usefulness of simulation in understanding the issues in thisarea.

The laboratory equipment is located at the rear of the communications lab-oratory (EE104) on the top floor of building EE.

Laboratory Equipment

The following equipment should be available on the lab bench for you to carryout the experimental studies:

• Switching Electronics Laboratory PCB (see Figure E.1 for layout).

• Agilent 81110A 165/330MHz Pulse/Pattern Generator, OR, Philips PM57761Hz–100MHz 1nsec risetime Pulse Generator, OR any other signal gener-ator capable of producing a pulse rise time of 1nsec or less. Most of thestandard signal generators are not capable of doing this.

• HP 54542A 2Gs/sec 500MHz CRO, OR, Agilent 2Gs/sec 500MHz CRO,OR other 500MHz 2Gs/sec CROs with file storage and mathematicalprocessing facilities. The oscilloscopes should have conventional 500MHzprobes. The later Agilent CROs are the easiest CROs to use.

• Three working 50Ω coaxial cables with standard size BNC connectors onboth ends.4

You will also need a 1.44MB floppy disk to store the plots from the CRO.4Note that sometimes the coaxial cables have faulty soldred connections, so check that

them by looking that the input signal.

390 Assignment 1

Figure E.1: Test Printed Circuit Board.


Using the Equipment

The Agilent signal generator and the two cathode ray oscilloscopes (CROs)mentioned in the equipment list above are complex pieces of equipment. Fora person who has previously used a CRO (as most students doing this labshould have), using the CROs should not be a big problems. With a littleexperimentation and button pushing one can even work out how to use the moreadvanced features such as risetime measurement, and using waveform markers.Make sure that you set the CRO inputs to be 50Ω input impedance (there is alsoa 1MΩ input impedance option).

The Agilent pulse generator is a complex piece of equipment. Fortunatelyit is fairly easy to operate, even without a manual. One should ensure that therise time of the signals is set to 800psec (there is also a 1.6nsec option), and theoutput levels need to be set – the maximum output level is 4V. In addition theoutputs are current limited, so this level must be set to a level that allows theoutput to go to 4V with a 50Ω load. You should set the generator to make, say,a 100µsec pulse at a frequency of say 2000Hz. If you are using another signalgenerator, then make sure that the rise time is set to be 1nsec or less. Thefrequency is not critical, but the pulse width must be long enough to allow theline to settle to steady state before another switching edge.

You will need to save your results for the report. On the HP oscilloscopethis can be done using the following sequence, which must be done before yougenerate your waveforms:5

• Press “Shift disk” – the Shift button is the blue one.

• The storage options will then come up on the screen. Select “Store imageenable”.

• On the next set of menus select the TIF storage format.

• Set auto-increment for the file name.

The auto-increment feature for the file name means that the default file namewill have a number added to it for each stored screen. If this is not selectedthen the initial file will be overwritten.

To save a screen to the floppy disk, Press “Stop” to freeze the screen, andthen “Print”. A message should appear saying that the data is being saved toa file.

One other task that you have to do is to integrate a waveform. This functioncan be accessed from the “Math/FFT” button on the front panel of the HPCRO.

If you are using another CRO then consult the manual to see how to carryout the equivalent operations.

Preliminary Work

There is a little preliminary work to be done before doing the actual experiments.Several resistors are shown in Figure E.1. Determine the values of the resistors.In order to do this one must know what the resistors are to do:

5Make sure that you have a floppy in the drive before doing any of this.

392 Assignment 1

• The first track has resistors RS1 and RT1 . These resistors have to beselected to make the trace look like 50Ω from the signal generator coaxialcable point of view, and the characteristic impedance of the line lookingfrom the trace side.

• The RT2 resistor is to match the 50Ω signal cable to the trace. There is norequirement for matching from the trace back to the coaxial signal cable.

The Experiments

The experiments to be conducted on the PCB will mirror the simulation studiescarried out in Questions 1 and 2.

Carry out the following:

1. For the trace at the top of the PCB (i.e. the source terminated trace)generate a plot for the source end, mid-point and end of line waveforms.

2. For Experiment d generate the end of line plot using the standard CROprobe for the oscilloscope that it being used. There is a connection loop atthe load end of the line to allow this measurement. Explain the differentresult from that obtained using the inbuilt “home brew” probe. A

3. For the second set of traces from the top of the board (i.e. the two tracesthat are very close together) plot the voltages across the non-driven lineat the mid point and the end termination. Explain what you see andcompare the results to those obtained for the equivalent situation in thesimulation of Question 2. Were the parameters estimated in Question 2close to the correct values.

4. The next experiment involves a trace with a branch off it – i.e. the thirdtrace from the top of the board. Plot the waveforms on the originatingtrace prior to the branch, and at the end termination, and explain whatyou see. How well do the experimental results correlate to the simulationresults.

5. The fourth trace from the top of the board has a 10pf capacitor on it tosimulate the input capacitance of a logic gate. Plot the waveforms beforethe capacitor, and at the end termination and explain the observations.How well do they conform to the same situation when simulated.

6. Using the set of resistor to the left hand side of the board (capacitivelycoupled resistor circuit) and plot the coupling voltage waveforms. Workout what the coupling current and mutual capacitance values are.

7. Using the right most resistor circuit (inductively coupled resistor circuit),plot the coupling voltage. Calculate what the mutual inductance is be-tween the two components is (account for the capacitance coupling thatwill also be present in this case).

Appendix F

Assignment 2

F.1 Introduction

This assignment/lab is on switching regulators. We shall consider the followingswitch mode converter structures:

• The buck converter.

• The boost converter.

• The isolated forward converter.

This assignment is a major assessment item, so allocate enoughtime to do it. The buck and boost converter sections will earn 86% of themarks, and the section on the forward converter only 16%. Therefore, if youare pushed for time, then concentrate your efforts on the first two sections.

In order to carry out the experiment one needs to understand the circuitryof the experimental system. The power side circuit of the experimental kit isshown in Figure F.1. You will notice that the circuit switching elements areall BJTs, and not MOSFETs. This is due to the vintage of the experimentalkit (which was developed many years ago by a student project). You will alsonotice that there are several passive components, as well as four high speeddiodes, included in the kit.

In addition to the power side of the kit there is also control circuitry. Thisis based on the National Semiconductor LM3524 switching regulator integratedcircuit. For completeness the data sheet for an updated version of this IC(LM3524D) is included at the end of this lab sheet. The control circuitry in-cluded in the experimental kit is shown in Figure F.2. The oscillator allowscontrol of both the ton and toff times.

Remark F.1 You should note that the transformer used in the kit is a stan-dard pulse transformer and has four windings. Only three of the windings areavailable to the user. The fourth winding is terminated with a resistor so thatany oscillations that occur due to the interaction of the leakage inductance andthe winding capacitance will be damped out (i.e. one can get underdamped LCoscillations due to this interaction). If you are not using a winding you shouldalso terminate that winding with a resistor (don’t make it too small or too big –

394 Assignment 2

1k

22. k

1kBC337

BC33746V

100 1N4448

0 01. F

BC327

BC337

BC337

BC337

1k

1k 22022. k

2k

220

+12V

1

1 2

8mH1F

100V

22. F 1

1

k

W

1

1

k

W

0V

Figure F.1: Power circuit of switch experimental box.

5k10k

560 2.2k

0 0047. F

01. F3 1000 F 16V

10V

0V

OSC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

10kFB (feedback)

4.7k22k

PWM

10k 1k

50k

0 001. F

+ + +

0 0047. F

4.7k

2.2k

3.3k

1nF

5k

9V LM3524

1N9141N914

1N914

Figure F.2: PWM control circuit for laboratory module.

F.2 Equipment Required 395

several kΩ should be OK). The presence of the unused windings (even correctlyterminated ones) leads to a distortion of the waveforms across the switchingtransistor when the transistor is turned off.

Remark F.2 Most of the output transistors are current overload protected.However, please don’t test this, as I don’t know how good the current protec-tion is.

Remark F.3 The output transformer is not a power transformer, therefore ithas a low power output capability of approximately 200mW (according to the lab-oratory manual written by the designer of the module). Consequently be carefulthat you do not overload it.

Remark F.4 For many of the plots suggested below it may make sense to plotthe switching waveform to the transistor at the same time. This allows one tocorrelate the waveform with the switching signals.

F.2 Equipment Required

a. Switch mode power supply experimental kit.

b. Cathode ray oscilloscope (CRO), preferably with an ability to save thescreen plots to a floppy disk. You do not need to have the very high speedoscilloscopes since this application is not very demanding from a frequencypoint of view.

c. Current probe – only modest currents will be measured so this does notneed to be a high current probe.

d. Standard CRO voltage probes.

e. 12V power supply.

f. Miscellaneous resistors which can be used for different loads.

F.3 The Experiments

F.3.1 The Buck Converter

The first section of this experiment involves setting up a Saber simulation of abuck converter with open loop control – i.e. the switch of the converter is drivenfrom an oscillator. The circuit to be simulated is shown in Figure F.3.

a. Calculate the output ripple as a function of the frequency of the switching(with the component values shown). Assume that the nominal DC outputvoltage is 5V.

b. Determine the output load value for which the inductor current will be-come discontinuous.

c. Simulate the circuit of Figure F.3 so that the output ripple is 50mV. Youcan determine the appropriate frequency from the expression derived inItem a.

396 Assignment 2

v_oswitch_output_voltage

v_dc 10

BITSTREAM

prbit_l4

pwld

100e-6

50e-3

40000

sw1_l4

pwld sw1_

l4

100

BITSTREAM

prbit_l4

Figure F.3: Buck converter – Saber circuit.

d. Simulate the transient performance of the circuit in open loop with a stepchange in the load resistance.

e. Increase the load value in the simulation and verify that the inductorcurrent becomes discontinuous at the value calculated in Item b

f. Place a closed loop PWM controller around the circuit of Figure F.3. Thecontroller should have the general form shown in Figure F.4. You canuse the ideal operational amplifier components from the Saber simulatorlibrary. Simulate the circuit with the control around it (you will haveto determine the feedback gain to get the best performance without thesystem becoming unstable). Again simulate a step change in the load onthe circuit performance (i.e.1kΩ to 500Ω).

g. Set up the open loop circuit of Figure F.3 on the experimental module.1

Plot the current through the switch and through the inductor. Plot theoutput voltage ripple. Comment on the comparison of these plots withthose obtained in the simulations. Find the value of load resistance re-quired to get discontinuity in the inductor current, and compare with thetheoretical value.2

h. Finally close the loop around the buck converter. The output voltage ofthe output is fixed by the resistance setting in the control circuit shownin Figure F.2. Experiment with step changes in the load resistance andconsider the transient response of the output.3

F.3.2 Boost converter

Remark F.5 The output voltage of the experimental boost converterhas to be controlled to be under 46V to prevent the Zener diode across

1You do not have an ideal switch in the module, so you will have to choose a transistorswitch. Consult Figure F.1 to determine which switch to use.

2You may have to connect an external resistor not included on the module to achieve this.3You should be able to trigger the CRO on the output transient if you use AC coupling.

The load changes can be effected by plugging and unplugging a resistor.

F.3 The Experiments 397

+

-+

-

R1

R2

Vref

Vtri

Vo

Error amplifier

PWM generation

Switchinterface

Toswitch

(Voltage reference) (Triangular waveform)

verr

Figure F.4: Conceptual PWM control circuit for the buck converter.

v_o

v_dc 10

BITSTREAM

prbit_l4

100e-6 40000

sw1_

l4

100

BITSTREAM

prbit_l4

50e-3

sw1_

l4

pwld

Figure F.5: Saber model of the boost converter.

398 Assignment 2

the output transistor (as shown in Figure F.1) from distorting theoutput waveform.

a. Calculate the output voltage versus duty cycle for the circuit of Figure F.5with: (i) continuous inductor current, and (ii) a discontinuous inductorcurrent. The load is a 1000Ω resistor and a 30V output voltage. Calculatethe output ripple.

b. Simulate the circuit of Figure F.5 and confirm the calculations of Item (a).

c. Place a feedback controller, based on that of Figure F.4, around the circuitof Figure F.5 and simulate the stability of the resultant configuration.Apply step changes in the load resistance and plot the resultant outputtransient performance. Comment on the stability of circuit, and suggesthow it may be improved.

d. Set up the boost converter circuit of Figure F.5 on the experimental mod-ule. Apply a duty cycle so that a 30V output voltage is generated. Makesure that you start with a small duty cycle so that you do not generatea voltage that is too high for the transistor. Plot the current throughthe inductor. Experiment with changes in the duty cycle and look at theinductor current – is there any non-linearity in it and if so why?

e. Change the load resistance in the experimental circuit of Item (d) so thatthe current in the inductor becomes discontinuous. Use the value calcu-lated in Item (a) as a starting point. Plot the current in the system asthat current becomes discontinuous. Generate plots that demonstrate thevoltage gain of the converter under discontinuous current operation.

F.3.3 Forward converter

Remark F.6 Note that this section is only worth 16% of the mark, so if youare pressed for time then concentrate on the previous two converters.

The magnetising inductance of the transformer in the experimental moduleis 0.00638H unsaturated. Saturation begins at 0.18Amp to 0.2Amp, so keep theprimary current below this value.

a. Calculate the duty cycle boundaries for the isolated forward convertercircuit shown in Figure F.6 assuming that N1 : N2 = 1 : 1 and N1 :N3 = 1 : 2, and alternatively N1 : N2 = 1 : 2 and N1 : N3 = 1 : 1.Comment on the effect of the various turns ratios on the performance ofthe circuit. Calculate the voltage gain of the converter with continuousand discontinuous output filter current and arbitrary turns ratios.

b. Set up the circuit of Figure F.6 in Saber and plot the output voltage, thevoltage across the switch, the voltage across the energy feedback winding,the current through the energy feedback winding, and the current throughthe filter inductor for the various winding configurations. Alter the dutycycle so that the filter inductor current becomes discontinuous and checkthe value against the values from the expressions calculate in Item a.

F.3 The Experiments 399

VoC

L

vL

+ -

iL

D1

D2

N2 R

L

D3

N1

N3

SW

Vd

Figure F.6: Practical isolated forward converter circuit.

c. Include a small leakage inductance in the Saber model of Item b andplot the output voltage across the switch. Compare to the situation whenthere is no leakage. Add a snubber circuit and redo this.

d. Set up the circuit of Figure F.6 on the experimental module. Plot the sameresults as for Item b, and explain any discrepancies between the simulationand experimental results. Is there any sign of leakage inductance effectsin this circuit? Apply a snubber to the switching transistor and replot theoutput voltage across the transistor.

400 Assignment 2

Appendix G

Review of Second OrderCircuits

This appendix will give a brief review of second order circuits. This is includedas second order series and parallel circuit inevitably come into high speed dig-ital systems due to the presence of inductance and capacitance in the variouscircuits.

G.1 Series RLC Circuits

Consider a circuit of the form shown in Figure G.1. Carrying out standard loopanalysis we can write the following differential equation for this circuit:

Rdi

dt+ L

d2i

dt2+

i

C=

dv

dt(G.1)

Taking the Laplace Transform of (G.1) we can write the following transferfunction for the current: transfer function

i(s)vin(s)

=sC

LCs2 + RCs + 1(G.2)

and therefore the transfer function for the voltage across the capacitor is:

vo(s)vin(s)

=1

LCs2 + RCs + 1(G.3)

One can see that the poles of (G.3) are: poles

s = − R

2L±√

R2

4L2− 1

LC(G.4)

which can be written as:s = −α ±

√α2 − ω2

o (G.5)

402 Review of Second Order Circuits

i

R

vin C

L

+

-

vout

Figure G.1: Series RLC circuit

where:

α =R

2L(G.6)

ωo =1√LC

(G.7)

One can get a better impression of the position of the poles if they are plottedon the complex plane. This is shown in Figure G.2. Note that this diagram isonly showing one of the two conjugate poles.

We can define several other terms from this diagram. The natural resonantfrequency , ωd, is the frequency of oscillation of the natural response (i.e. sourcenatural resonant

frequency free response) of the circuit when there is resistance present. This is differentfrom the resonant frequency , ωo, which is the resonant frequency of a losslessresonant frequencyseries RLC circuit.1 Another variable of interest is the damping factor . Thedamping factorformal definitions are:

ωd =√

ω2o − α2 (natural resonant frequency) (G.8)

ξ = cos θ =α

ωo(damping factor) (G.9)

From Figure G.2 one can see that if the poles are off the real axis of the com-plex plane then there is a projection of the complex vector onto the imaginaryaxis. This means that there is an oscillatory mode in the response of the circuit.If the angle θ is zero, then the two poles are coincident. This condition corre-sponds to critical damping .2 Because there is not projection onto the imaginarycritical damping

1The resonant frequency is the frequency at which a driven series RLC circuit will exhibitis minimum impedance.

2Critical damping gives the fastest response without overshoot.

G.1 Series RLC Circuits 403

o

o

d

Im

Re

Figure G.2: Series RLC circuit pole positions.

axis there is no oscillatory or over shoot behaviour in the response. From theviewpoint of the equations critical damping corresponds to the condition:

ωd =√

ω2o − α2 = 0 (G.10)

Therefore critical damping means that:

α = ωo

R

2L=

1√LC

∴ R = 2

√L

C(G.11)

For the case where:α > ωo (G.12)

we have two real poles generated. One the these poles will move towards theleft on the real axis and the other to the right. The system response is now veryslow, and it is said to be overdamped . There are no oscillations. overdamped

Another important property of a series RLC circuit is its impedance. Rear-ranging (G.2) we can write the impedance transfer function:

Z(s) =vo(s)i(s)

=LCs2 + RCs + 1

Cs(G.13)

If we let s = jω (i.e. the resonant frequency), and substitute this into (G.13)we get:

Z(s) = R +1

jωC− ωL

j

= R + j

[ω2LC − 1

ωC

](G.14)


Clearly the magnitude of this expression has a minimum value when the imag-inary term is zero. Therefore:

ω2LC − 1 = 0 ⇒ ω =1√LC

= ωo (G.15)

The minimum impedance is R under this condition. As noted earlier, this occursat the resonant frequency (ωo), and not the natural resonant frequency (ωd).

G.1.1 Quality Factor

Another important measure of resonant second order circuits is the quality factor– Q. When a circuit is being driven in resonance this is defined as:

Q 2πTotal energy stored in the circuit

Energy dissipated per period(G.16)

In the case of the series RLC circuit consider it to be driven with i(t) =Im cos ωot. The expression for the instantaneous energy stored in the inductoris:

eL(t) =12Li2 =

12LI2

m cos2 ωot (G.17)

Similarly the energy stored in the capacitor is:

eC(t) =12Cv2 =

12

I2m

ω2oC

sin2 ωot =I2mL

2sin2 ωot (G.18)

Therefore the total energy is:

eL(t) + eC(t) =12LI2

m(cos2 ωot + sin2 ωot) =12LI2

m (G.19)

which is obviously a constant.The average power dissipation in a resistor with a sinusoidal input is:

PR =12I2mR (G.20)

and hence the energy dissipated over a period To is:

PRT =12I2mRTo =

12fo

I2mR (G.21)

Using (G.19) and (G.21) in (G.16) one can write:

Q = 2π12LI2

m1

2foI2mR

= 2πfoL

R

= ωoL

R

∴ Q =1R

√L

Cusing ωo =

1√LC

(G.22)

If Q = 0.5 then:

R =1Q

√L

C= 2

√L

C(G.23)

which is the same expression for the resistance when the circuit is criticallydamped.

G.1 Series RLC Circuits 405

G.1.2 Time Domain Response

Let us now consider the time domain solution of (G.3). In this we shall beassuming that for t < 0 then vin(t) = V0, and at t ≥ 0 vin(t) = 0 – i.e. thevoltage drops to zero. Therefore the circuit becomes a source free circuit with aninitial voltage on the capacitor of V0 volts. Therefore we only need to considerthe natural response of the circuit. This situation will also give us a lot ofinformation about the case when there is a positive step in the voltage.

Examination of (G.1) suggests that a possible candidate solution is:

v0(t) = A1es1t + A2e

s2t (G.24)

where:s1,2 = −α ± jωd (G.25)

Expanding the exponential terms in this equation we can write:

v0(t) = e−αt [B1 cos ωdt + B2 sinωdt] (G.26)

where:

B1 = A1 + A2

B2 = j(A1 − A2)

In order that we can determine the B1 and B2 coefficients we apply someboundary conditions:

v0(0) = V0 (G.27)dv0(0)

dt= 0 (G.28)

Applying the first of these conditions to (G.26) we can write:

B1 = V0 (G.29)

Taking the derivative of (G.26) we get:

dv0

dt= e−αt [(B2ωd − αB1) cos ωdt − (B1ωd + αB2) sin ωdt] (G.30)

Applying (G.28) to this expression gives:

αB1 = B2ωd ⇒ B2 =αV0

ωd(G.31)

and hence the voltage equation becomes:

v0(t) = V0e−αt

[cos ωdt +

α

ωdsinωdt

](G.32)

and the derivative of this is:

dv0(t)dt

= −V0

[(ωd +

α2

ωd

)sin ωdt

](G.33)


From (G.8), (G.7), (G.6) and (G.22) we can derive the following expressions:

ωd =

√1

LC− R2

4L2

=√

1LC

− 14LCQ2

=1√LC

√1 − 1

4Q2(G.34)

We shall assume that Q > 0.5, which means that the circuit is underdampedand ωd > 0.

If we want to find the point of the first maximum swing in the time response(i.e. the first maximum in the oscillatory response), then we know this mustoccur when ωdt = π. Therefore:

tfm =π

ωd

⇒ tfm =π√

LC√1 − 1

4Q2

(G.35)

We also also write:

v0(tfm) = −V0eαtfm since ωdtfm = π

∴ v0(tfm) = −V0e− R

2L

⎡⎣ π

√LC√

1− 14Q2

⎤⎦

= −V0e

[−π√

4Q2−1

](G.36)

Figure G.3 shows that time plot for a series RLC circuit. In this particularcase the circuit Q is 6.3.

From (G.36) we can drawn the conclusion that:

Vovershoot/Vstep = e

[−π√

4Q2−1

](G.37)

G.2 Parallel RLC Circuits

This section carries out a similar analysis for a parallel circuit RLC as wascarried out above for the series RLC circuit. To a large extent the results forthis circuit configuration are a dual of those above, therefore some of the analysishere will be brief.

The following discussion will be with reference to Figure G.4. If one appliesnodal analysis to this figure one can write the following differential equation forthe circuit:

d2vin

dt2+

1RC

dvin

dt+

vin

LC=

1C

diindt

(G.38)

If we take the Laplace transform of this and rearrange we can get the followingtransfer function:transfer function

G.2 Parallel RLC Circuits 407

0 0.5 1 1.5 2 2.5 3 3.5 4-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

v t V efm

Q0 0

4 12

( )

eR

Lt

LNM

OQP2

tLC

Q

fm

11

4 2

Time (secs)t

Vol

tage

volt

sv

Figure G.3: Time response of a series RLC circuit with Q = 6.3.

vin

iin

R L C

Figure G.4: Parallel RLC circuit.


iin(s)vin(s)

=C(s2 + 1

RC s + 1LC )

s(G.39)

The impedance transfer function can be simply written from a rearrangementimpedance transferfunction of (G.39 as:

Z(s) =vin(s)iin(s)

=s

C(s2 + 1RC s + 1

LC )(G.40)

As in the series RLC circuit case we can now find the poles of this transferpolesfunction, which have a similar form to those for the series RLC circuit:

s = −α ±√

α2 − ω2o (G.41)

where:

α =1

2RC(G.42)

ωo =1√LC

(G.43)

As with the series RLC circuit we can define:

ωd =√

ω2o − α2 (G.44)

Critical damping is defined similarly to that for series RLC circuits in thatCritical dampingωd = 0. This leads to:

α = ωo

∴ 12RC

=1√LC

⇒ R =12

√1

LC(G.45)

The impedance of the circuit at resonance, as with the series RLC circuit,is of interest. Substituting s = jω into (G.40) and simplifying and taking themagnitude we can write:

|Z(s)| =ω√

ω2

R2 +(

1L − Cω2

) (G.46)

If ω = ωo = 1/√

LC then:|Z(s)| = R (G.47)

which can be shown to be the maximum impedance of the circuit.

G.2.1 Quality Factor

This will not be evaluated in the same detail as was carried out in the series RLCcircuit section since the development is so close. However, the key expressionswill be presented. It is assumed that the input voltage has the form:

vin = Vm cos ωot (G.48)

G.2 Parallel RLC Circuits 409

Therefore the current into the inductor is:

i =1L

∫ t

0

vindτ

=1L

∫ t

0

Vm cos ωotdτ

∴ i =Vm

Lωosin ωot (G.49)

The energy stored in the inductor is therefore:

eL(t) =12Li2

=12V 2

mC sin2 ωot (G.50)

Similarly the energy stored in the inductor is:

eC(t) =12Cv2

in

=12CV 2

m cos2 ωot (G.51)

The total stored energy is:

eT (t) = eL(t) + eC(t)

=12V 2

mC(sin2 ωot + cos2 ωot)

=12V 2

mC (G.52)

The energy dissipated in the resistor is:

eR(t) = PRTo =V 2

mTo

2R

=V 2

m

2foR(G.53)

Applying the definition of quality factor (G.16) we can write:

Q = 2π12V 2

mCV 2

m

2foR

= 2πfoRC = ωoRC

= R

√C

L(G.54)


Appendix H

Review of TransmissionLines

This appendix carries out a brief review of classical transmission line theory.Much of the work in the appendix is based on [22].

A transmission is distinguished from a traditional lumped circuit network inthat it is a transmission medium that is long enough that the currents and volt-ages at various points in the line cannot be considered to be the same value atany point in time. Therefore the line length is at least of the order of the wave-length of the signal being propagated down the line. Since an ideal transmissionline is considered to be uniform, then the distributed nature of the currents andvoltages (in respect of distance down the line) lead us to the conclusion thatthe line can be considered to be an infinite number of infinitesimal elementsdistributed along the line, each set of elements reacting to the local voltage andcurrents at any point of time.

Remark H.1 Any propagation line really is a transmission line. However, ifthe wavelength is long compared to the physical length of the propagation linethen the simplification can be made that at every point the same current voltageequations apply. This results in significant simplifications in the equations oneuses to analyse the line. This is the basis of conventional lumped model circuittheory.

Consider a transmission line consisting of two parallel wires of radius a andlet the distance between the axes of the wires be denoted by b. The followingtransmission line equations, which are based on a circuits view of the transmis-sion line, are valid under the following assumptions:

1. The separation distance b between the two wires and, therefore also theradius a of the wires is small in comparison with the space scale length ofvariations of the voltage and current as well as the associated electric andmagnetic fields.

2. The transmission line is uniform – i.e. every section of it is the same asevery other section.

412 Review of Transmission Lines

3. In general the currents in the two wires at a cutting point across the wirescan obey the following law:

I1 = IB + IU (H.1)I2 = −IB + IU (H.2)

where:

IB =I1 − I2

2

IU =I1 + I2

2

Notice that the currents consist of two components – the IB componentsare equal and opposite in the two wires. The IU components though are inthe same direction in the two wires. This is the situation that occurs in anunbalanced transmission line and has to be treated using electromagnetictheory. It shall be assumed in this analysis that the line is balanced andthe IU component is negligible.

Remark H.2 Assumption 1 implies that:

a < b λ (H.3)

where λ as the wavelength of the electromagnetic wave in the medium sur-rounding the transmission line.

Remark H.3 Assumption 2 means that the line has to be considered to infinitelength. Clearly a finite length line does not satisfy this requirement. However, inmost practical cases the end effects associated with finite length lines are smallenough to justify their omission.

Remark H.4 Assumption 3 states that the circuit approach to the analysis ofthe transmission lines can be carried out if the line is balanced. Imbalance anoccur is a line due to things like unsymmetrical placement of the two lines withrespect to other lines or the earth; unsymmetrical placement of a load on theline, or excitation on an unsymmetrical fashion.

Now that we have outlined the assumptions we are now in a position to beginthe modelling of the transmission line. The following parameters are shown inFigure H.1. Let use define:

L inductance per unit length of line (H/m)

C capacitance per unit length of line (F/m)

R series resistance per unit length of line (Ω/m)

G shunt conductance per unit length of line (mho/m)

These parameters, for a particular configuration, can be deduced from fieldtheory, or alternatively measured. For the moment we shall assume that wehave these values by some means.

413

2a

2a

b

x x x

L xR x

C x G x

I x t( , )

V x t( , ) V x x t( , )

I x x t( , ) A

Figure H.1: Two wire transmission line and a single element model.


H.1 Basic Equations

Now let use consider the elemental section of transmission line shown in Fig-ure H.1. At some particular time we have the following values:

V (x, t); I(x, t) voltage and current at position x

V (x + ∆x, t); I(x + ∆x, t) voltage and current at position x + ∆x

Given the above definitions for the parameters of the system, then the pa-rameters for a length of line ∆x is clearly ∆x times the value per unit length.

To develop the circuit equations for the circuit element we resort to ourold favourites – Kirchhoff’s voltage law and Kirchhoff’s current law. ApplyingKirchhoff’s voltage law first we can write:

−V (x, t) + L∆x∂

∂tI(x, t) + R∆xI(x, t) + V (x + ∆x, t) = 0 (H.4)

Dividing this expression by ∆x we can write:

V (x + ∆x, t) − V (x, t)∆x

+ L∂

∂tI(x, t) + RI(x, t) = 0 (H.5)

Let us consider this expression as we take the limit as ∆x → 0. We can see thatthe first term of (H.5) is the definition of a derivative, hence we can write theequation as:

∂

∂xV (x, t) = −

[L

∂

∂tI(x, t) + RI(x, t)

](H.6)

Remark H.5 One can see that (H.6) simply says that the rate of change ofvoltage along a differential length of line is simply the inductive voltage drop onthe line section plus the resistive voltage drop in the section.

In a similar fashion to the voltage equation we can write a second equationusing Kirchhoff’s current law applied to node A in Figure H.1:

−I(x, t) + C∆x∂

∂tV (x + ∆x, t) + G∆xV (x + ∆x, t) + I(x + ∆x, t) = 0 (H.7)

As with the voltage equation we divide this equation by ∆x which allowsone to write:

I(x + ∆x, t) − I(x, t)∆x

+ C∂

∂tV (x + ∆x, t) + GV (x + ∆x, t) = 0 (H.8)

which can be written as follows if ∆x → 0:

∂

∂xI(x, t) = −

[C

∂

∂tV (x, t) + GV (x, t)

](H.9)

Remark H.6 Equation (H.9) simply says that the change in the current acrossan element of the line is due to the shunt elements of the line bleeding off current.

H.2 Solution of Transmission Line Equations for the Lossless Case 415

Since the transmission line is by assumption (definition) the same every-where, then (H.6) and (H.9) are applicable at every point along the transmissionline at any time t.

Equations (H.6) and (H.9) constitute a pair of first order coupled partial dif-ferential equations. One can combine (H.6) and (H.9) into a single second orderpartial differential equation in voltage or current depending on the substitutionsone carries out. For example, if one carries out a partial differentiation of (H.6)with respect to x then one can write:

∂2

∂x2V (x, t) = −

[L

∂2

∂x∂tI(x, t) + R

∂

∂xI(x, t)

](H.10)

Substituting for (∂/∂x)I(x, t) using (H.9) and manipulating gives:

∂2

∂x2V (x, t) = LC

∂2

∂t2V (x, t) + (LG + CR)

∂

∂tV (x, t) + RGV (x, t) (H.11)

Similarly, taking the partial derivative of (H.9) with respect to x gives:

∂2

∂x2I(x, t) = −

[C

∂2

∂t∂xV (x, t) + G

∂

∂xV (x, t)

](H.12)

Substituting for (∂/∂x)V (x, t) using (H.6) and manipulating the result gives:

∂2

∂x2I(x, t) = LC

∂2

∂t2I(x, t) + (RC + GL)

∂

∂tI(x, t) + GRI(x, t) (H.13)

Summary H.1 We can summarise the fundamental differential equations fora transmission line as:

∂

∂xV (x, t) = −

[L

∂


](H.14)

∂

∂xI(x, t) = −

[C

∂

∂tV (x, t) + GV (x, t)

](H.15)

∂2

∂x2V (x, t) = LC

∂2

∂t2V (x, t) + (LG + CR)

∂

∂tV (x, t) + RGV (x, t) (H.16)

∂2

∂x2I(x, t) = LC

∂2

∂t2I(x, t) + (RC + GL)

∂

∂tI(x, t) + GRI(x, t) (H.17)

Remark H.7 Because of the partial differential nature of (H.16) and (H.17) itis difficult to solve them in general.

Note H.1 The voltage difference V (x, t) at some particular point on the line(i.e. a particular x) and at a particular time (i.e. a particular t) is the voltagedifference between the two wires at that particular point. It is not the voltagedifference to some single reference point.

H.2 Solution of Transmission Line Equations forthe Lossless Case

Whilst the general solution of the transmission line equations are difficult, aspecific solution can be more easily found for the case where the line is lossless


– i.e. R = G = 0. If we apply this condition to (H.14) and (H.15) we can writethe following for the first order equations: first order equa-

tions∂

∂xV (x, t) = −L

∂

∂tI(x, t) (H.18)

∂

∂tI(x, t) = −C

∂

∂tV (x, t) (H.19)

and similarly for the second order equations we can write:second order equa-tions

∂2

∂x2V (x, t) =

1v2

∂2

∂t2V (x, t) (H.20)

∂2

∂x2I(x, t) =

1v2

∂2

∂t2I(x, t) (H.21)

where:

v =1√LC

(H.22)

The symbol v is used in (H.22) because it turns out that this is the transmissionvelocity of waveforms down the transmission line. One can verify at this stagethat it has the dimensions of velocity.

In order to proceed any further with the solutions to the equations we in-troduce the following non-obvious change of variables:

ξ = x − vtη = x + vt

(H.23)

Note H.2 The above change of variable implies that the original variables arerelated as follows to the new variables:

x = ξ+η2

t = η−ξ2v

(H.24)

Therefore the original V (x, t) and I(x, t) functions can be written as V (ξ, η) andI(ξ, η).

Using the content of Note H.2 we can develop the following relationships forthe differential of V in terms of the old and changed variables:

dV =∂V

∂xdx +

∂V

∂tdt =

∂V

∂ξdξ +

∂V

∂ηdη (H.25)

dξ = dx − vdt; dη = dx + vdt (H.26)

Substituting (H.26) into (H.25) and equating the dx and dt coefficients forthe right and left sides gives one:

∂V

∂x=

∂V

∂ξ+

∂V

∂ηor

∂

∂x=

∂

∂ξ+

∂

∂η(H.27)

1v

∂V

∂t= −∂V

∂ξ+

∂V

∂ηor

1v

= − ∂

∂ξ+

∂

∂η(H.28)


These two expressions can be manipulated to give:

∂

∂x+

1v

∂

∂t= 2

∂

∂η;

∂

∂x− 1

v

∂

∂t= 2

∂

∂ξ(H.29)

Considering (H.20) and (H.29) one can see the (H.20) can be written as:(∂

∂x+

1v

∂

∂t

)(∂

∂x− 1

v

∂

∂t

)= 0 (H.30)

which using (H.29) can be written as:

∂2

∂ξ∂ηV = 0 (H.31)

Equation (H.31) is now a very simple equation to solve. One merely has tointegrate the equation twice, once for the ξ variable and once for the η variable.These integrations can be written as follows:∫

∂

∂ξ

(∂V

∂η

)dξ = f ′

2(η) + c′v (H.32)

where the “′” denotes the derivative with respect to the functions variable.Therefore after the first integration we are left with:

∂V

∂η= f ′

2(η) + c′v (H.33)

We now carry out the second integration with respect to η to find the solutionto the voltage equation: voltage equation

V (x, t) =∫

∂V

∂ηdη =

∫(f ′

2(η) + c′v)dη

= f1(ξ) + f2(η) + cv

= f1(x − vt) + f2(x + vt) + cv (H.34)

Note H.3 The c′v after integration is also a function of η. Therefore this isrolled into the function f2(η) upon the η integration step. The cv constant inthe final expression is simply a constant and is independent of either ξ or η.This has to be the case as it disappears after the two partial differentiations.

Remark H.8 The integrations to end up with (H.34) can be carried out in anyorder – i.e. one could integrate with respect to η first followed by ξ and the resultwill be the same.

One can easily prove that (H.34) is a solution to the original differentialequation by carrying out the appropriate derivatives. This is most easily carriedout by using the following general identity. Let γ(x1, x2) be an arbitrary functionof two variables, and f(γ) be an arbitrary function of γ, then by the chain ruleof differentiation:

∂

∂x1f(γ) =

(∂f

∂γ

)(∂γ

∂x1

)(H.35)


Applying this identity to the derivative of the left hand side of (H.20) we get:

∂2

∂x2V (x, t) =

∂

∂x2(f1(ξ) + f2(η))

=∂2

∂ξ2f1

[∂ξ

∂x

]2

+∂2

∂η2f2

[∂η

∂x

]2

=∂2

∂ξ2f1 +

∂2

∂η2f2 (H.36)

Now applying the same identity to the right side of (H.20) we can write:

∂2

∂t2V (x, t) =

∂

∂t2(f1(ξ) + f2(η))

=∂2

∂ξ2f1

(∂ξ

∂t

)2

+∂2

∂η2f2

(∂η

∂t

)2

= v2

(∂2

∂ξ2f1 +

∂2

∂η2f2

)(H.37)

If one compares (H.36) and (H.37) one can see that (H.20) holds as required forthe solution.

In a similar manner to the solution of the voltage equation one can alsoderive the solution for the current equation in the line:current equation

I(x, t) = g1(x − vt) + g2(x + vt) + ci (H.38)

where g1 and g2 are arbitrary functions and ci is a constant independent of xand t.

Remark H.9 The assertion was made earlier that v = 1/√

LC was the velocityof a waveform down the transmission line. One can see from (H.34) and (H.38)that they contain two functions, one of x − vt and the other x + vt. In bothequations the first function is moving to the right with a velocity of v and thesecond function is moving to the left with velocity v. If is assumed the bothfunctions originate at x = 0 at t = 0.

Remark H.10 One can see from (H.34) and (H.38) that the f and g functions(regardless of the direction of propagation) do not contain any attenuation term.Therefore the waveforms are propagated without any losses and will propagateforever down an infinite transmission line. This is a fact that follows from notincluding any losses in the line.

Remark H.11 Another interesting point about the solutions is that they do notcontain any frequency dependent terms. Therefore the transmission line has aninfinite frequency response. One can propagate a signal of any frequency downthe line without any losses.

We note from (H.18) and (H.19) that there is a relationship between thevoltage and the current at a particular point in the line. For example consider(H.19), rewritten here for convenience:

∂

∂tI(x, t) = −C

∂

∂tV (x, t) (H.39)


Evaluating the right hand side of this equation we get:

−C∂

∂tV (x, t) = −C

∂

∂t(f1(x − vt) + f2(xvt))

= Cv∂f1

∂ξ− Cv

∂f2

∂η(H.40)

Therefore we have:∂

∂tI(x, t) = Cv

∂f1

∂ξ− Cv

∂f2

∂η(H.41)

We can now integrate this expression with respect to x to get an expression forI(x, t):

I(x, t) =∫ (

Cv∂f1

∂ξ− Cv

∂f2

∂η

)dx (H.42)

Using (H.35) on (H.34) one can see that:

∂

∂xV (x, t) =

∂

∂x(f1(x − vt) + f2(x + vt) + cv)

=∂f1

∂(x − vt)∂(x − vt)

∂x+

∂f2

∂(x + vt)∂(x + vt)

∂x

=∂f1

∂ξ+

∂f2

∂η(H.43)

Comparing the derivative in (H.43) with (H.42) one can see that:

∂f1(ξ)∂x

=∂f1

∂ξ(H.44)

and:∂f2(η)

∂x=

∂f2

∂η(H.45)

therefore: ∫∂f1

∂ξdx = f1(ξ) + m(t) and (H.46)∫

∂f2

∂ηdx = f2(η) + n(t) (H.47)

This means that I(x, t) can be written as:

I(x, t) = Cvf1(x − vt) − Cvf2(x + vt) + f3(t) (H.48)

where f3(t) is a function from the integration process.We can now differentiate (H.48) to get an expression that can be used with

(H.18) as follows:

−L∂

∂tI(x, t) = LCv2 ∂f1

∂ξ+ LCv2 ∂f2

∂η− L

d

dtf3(t)

=∂f1

∂ξ+

∂f2

∂η− L

d

dtf3(t) (H.49)


since LC = 1/v2.This expression should be the same as (H.43) because of (H.18), therefore

the function of integration f3(t) must be zero or a constant since it disappearswhen a derivative is taken with respect to x. We shall denote this constant asci and hence we can write the expression for the current in terms of the voltagefunctions as follows:

I(x, t) = Cvf1(x − vt) − Cvf2(xvt) + ci (H.50)

Remark H.12 A comparison of (H.50) with (H.38) leads one to the followingequalities:

g1(x − vt) = Cvf1(x − vt) (H.51)g2(x + vt) = −Cvf2(x + vt) (H.52)

Remark H.13 The previous remark leads us to the following conclusion – theterm Cv is equal to 1/R0, where R0 the characteristic impedance of thecharacteristic

impedance transmission line. This can be deduced from the fact that the current is relatedto the voltage functions via a real constant Cv. Therefore this constant musthave the dimensions of resistance (which can be verified via a formal dimensionanalysis). If one expands this definition of characteristic impedance using thedefinition of v, then the expression for it is:

R0 =

√L

C(H.53)

Using (H.53) one can write the expression for I(x, t) as:

I(x, t) =1

R0f1(x − vt) − 1

R0f2(x + vt) + ci (H.54)

Remark H.14 The constants cv and ci that appear in the (H.34) and (H.38)do not have any relationship between them defined by the original differentialequations of the system. There values are completely specified by the boundaryconditions of the transmission line – i.e. by the source impedance and the loadimpedance. They are DC values for the voltage (cv) and current (ci) flowing inthe transmission line under DC conditions. It is easily shown that the value ofcv can be determined independently of the value of ci.

H.2.1 Semi-infinite Transmission Line

Thus far we have considered the transmission line to extend for an infinitedistance in either direction from some initial starting point denoted as x =0. However, most real transmission lines start at a source and go in a singledirection from there. Under these conditions we cannot have a voltage or currentwaveform travelling in the negative direction,1 therefore the voltage and currentwaveforms are (assuming no DC component):

V (x, t) = f1(x − vt) (H.55)

I(x, t) =f1(x − vt)

R0(H.56)

1Because the line in infinite in the positive direction then no negative wave can be gener-ated.


Example H.1 Consider the situation shown in Figure H.2. We have a voltagesource that puts a pulse onto the line at time t = 0. The voltage source has aninternal impedance of RgΩ. We shall work out the values of the functions forthe voltages and currents down the line. The generator function can be writtenas:

Vg(t) =

0 ∀t < 01 ∀t ≥ 0 (H.57)

Therefore:

V (0, t) =Vg(t)R0

Rg + R0= f1(−vt) (H.58)

I(0, t) =Vg(t)

Rg + R0=

f1(−vt)R0

(H.59)

One can manipulate these expressions so that the f1 expressions can be morereadily interpreted with respect to the generator function voltage. For example,after 10 seconds say, the waveform will have travelled 10v in the positive xdirection. Therefore, position 10v on the x axis corresponds to t = 0 in the timeaxis of the voltage generator. Similarly the position 9v corresponds to the t = 1position in the time axis of the voltage generator. Therefore one can see thatthe time axis effectively runs in the negative x direction on the transmissionline voltage versus distance/current plot. Therefore the x axis waveform can becorrelated to the time axis input waveform by realising that:

t =x

v(H.60)

is the time required for a waveform to travel the distance x. Therefore Vg(t−x/v)is equivalent to f1(x − vt) for all t and x.

Using this knowledge and the above equations one can write:

V (x, t) = f1(x − vt) =R0

Rg + R0Vg

(t − x

v

)(H.61)

I(x, t) =f1(x − vt)

R0=

1Rg + R0

Vg

(t − x

v

)(H.62)

Figure H.3 shows the plots for the time domain and distance domain at sometime t1. Notice that the plots effectively run in opposite directions to each other –i.e. the time domain plot evolves to the right in the figure, which corresponds tomoving to the left in the distance plot. The crossed arrows shown correspondingpoints on the two plots. Also note the f1(x− vt) has its own origin at the pointof the dotted line and this origin moves with the waveform when plotted on thex axis.

H.2.2 Finite Transmission Line and Reflection Coefficient

Consider a finite transmission line starting at x = 0 and extending to x = l. Atthe point x = 0 there is a source generating a voltage and current into the line,and at l there is a load resistor RL.


Transmission line

Rg

R0

Vg To

Figure H.2: Semi-infinite transmission line with source

tt1

0

V tg( )

f x vt1( )

x

f1

0( )

vt1vt

1

Time domain plot

Distance domain plot

Figure H.3: Plot of pulse in the time and distance domains


We have noted that at every cut plane in the line the voltage and the currentare related as:

V (x, t)I(x, t)

= R0 (H.63)

The obvious question then arises – what happens at the RL termination? Thekey to answering this question is to realise that Kirchhoff’s circuit equations,which hold all the way along the transmission line also have to hold at the RL

termination.Before discussing the conditions at the termination in detail, let us introduce

a little extra notation. We shall denote V+ and I+ to be the voltage and currentwaveforms that move in the positive x direction as they reach the termination.Similarly, we denote V− and I− as the voltage and current waveforms travellingin the −x direction at the termination.

As the voltage and current waveforms approach the termination then ingeneral:

V+

I+= R0 = VL

IL= RL (H.64)

This inequality implies that Kirchhoff’s circuit equations don’t hold. To see this,assume that the voltage VL = V+. This would mean that IL = V+/RL = V+/R0.Therefore, the current at the node required for the resistor does not equal thecurrent flowing at that point in the transmission line. Kirchhoff’s current lawis not obeyed. Even though this is a slightly artificial example, it neverthelessshows the basic problem.

Of course Kirchhoff’s laws must be satisfied at the load resistor. In order forthem the hold the V + waveform is considered to reflect from the terminationand generate a waveform that moves in the −x direction. Similarly for thecurrent waveform. Therefore:

V+ + V− = VL (H.65)

I+ + I− = IL orV+

R0− V−

R0=

VL

RL(H.66)

One can see from these equations that the voltage and current equations nowmake sense.

Let us define the reflection coefficient as: reflection coeffi-cient

ρ =V−V+

= −I−I+

(H.67)

Substituting (H.65) and (H.66) into (H.67) one can write:

V+

R0− V−

R0=

V+ + V−RL

∴ V+

(1

R0− 1

RL

)= V−

(1

R0+

1RL

)

⇒ ρ =V−V+

=(

RL − R0

RL + R0

)(H.68)

Remark H.15 If RL = R0 then ρ = 0 which means that there is no reflection.If RL = 0 then ρ = −1 which means that the whole of the incident voltagewaveform is reflected. Therefore V+ + V− = V+ + ρV+ = 0V .


Remark H.16 If RL > R0 then 0 < ρ ≤ 1, which implies that the incidentand reflected voltage waveforms have the same polarity. Therefore at the loadtermination these voltages add together to produce a higher voltage than theincident voltage on its own. If RL = ∞ then ρ = 1

Remark H.17 As defined in (H.67) the reflection coefficient is a real value.In the case of reactive terminations the situation is much more complex.

H.3 Reflection Diagrams

Let us consider the situation shown in Figure H.4. We are interested in how theDC conditions are established in the transmission line after the switch is closedat t = 0. This situation is of particular interest when one is dealing with digitalpulses, since this situation obviously mirrors the switching of a digital signal ona transmission line.

V0

V0

Rg

RL

x 0 x l

Switch closed attime t=0

Rg

R v0,

R0

I1

V1

Figure H.4: DC voltage transient on a transmission line

When the switch is closed, after a very long time – in fact an infinite timeif the line is considered to be lossless, the current and the voltage will settle toDC values. These values are given by:

Vf =RL

R0 + RLV0 (H.69)

If =V0

R0 + RL(H.70)

We shall assume that at t < 0 the current and voltage in the line is zero.As soon as the switch is closed a step waveform will begin to travel done thetransmission line (similar to the diagram in Figure H.3). We shall denote V+1

H.3 Reflection Diagrams 425

and I+1 as the forward travelling waveforms, therefore V+1 = R0I+1. From theequivalent circuit at the input one can deduce that:

V+1 =R0

Rg + R0V0 (H.71)

I+1 =V0

Rg + R0(H.72)

Considering the voltage waveform, it travels down the transmission line atthe velocity v, reaching the termination at T = l/v. At this point one may ormay not get a reflection, depending on the reflection coefficient, ρL. We shallassume the ρL = 0, therefore there is a reflection. The reflected voltage at theload resistance is:

V−1 = ρLV+1 (H.73)

which travels in the negative x direction with the same velocity v. Thereforefor any time from T < t < 2T there is a voltage discontinuity travelling towardthe generator – everywhere from the generator to the discontinuity the voltageis V+1 and from the discontinuity to the load the voltage is V+1 + V−1.

At time t = 2T the discontinuity will reach the generator. The generatoris assumed to be an ideal voltage source, with its internal impedance beingmodelled by the generator resistance Rg. Because a transmission line is a linearcircuit we can apply the principle of superposition to work out what happenswhen the reflected voltage meets the generator. We know if the reflected wave isnot there (i.e. V−1 = 0) the voltage on the transmission line at the generator isV+1 travelling in the positive direction (as was present at t = 0). If the voltagesource is not there (i.e. V0 = 0) then the reflected wave V−1 sees a resistance ofRg. If Rg = R0 then again we will have a reflected waveform with a reflectioncoefficient of:

ρg =Rg − R0

Rg + R0(H.74)

The new reflected wave will move in the positive direction and its value is:

V+2 = ρgV−1 (H.75)

We can now apply the superposition. The effective waveform that now propa-gates in the positive direction down the transmission line is:

V+1 + V−1 + V+2 = (1 + ρL + ρgρL)V+1 (H.76)

Therefore from the generator to the discontinuity we have the voltage of (H.76),and from the discontinuity to the load termination we have the (1 + ρL)V+1.

At time t = 3T the forward travelling waveform reaches the load terminationagain, and we again have a reflection based in the ρL reflection coefficient.Therefore the reflected waveform is:

V−2 = ρLV+2 (H.77)

and therefore from the load termination to the discontinuity we have a voltageof:

V+1 + V−1 + V+2 + V−2 = (1 + ρL + ρgρL + ρgρ2L)V+1 (H.78)


and from the discontinuity to the generator we have:

(1 + ρL + ρgρL)V+1 (H.79)

The whole process then repeats again at the generator, and so on forever inthe case of the lossless line.

A good way of visualising reflections and the consequent building of thevoltage waveforms is via a reflection diagram, as shown in Figure H.5. Thereflection diagramhorizontal axis is the distance along the transmission line, and the vertical axisis the time. The thick lines represent the waveforms travelling down the line,with the arrows indicating the direction of the wave. The annotation on eachof the directed arcs denotes the magnitude of the reflected waveform.

The reflection diagram can be used to obtain either:

• The voltage distribution along the line at a particular time, or

• The time dependence of the voltage at a particular point on the transmis-sion line.

x 0 x l

Voltage

V+1

V+1 L

V+1 L g

V+1 2

L g

V+12L

2 g

V+1 3

L 2g

T

2T

3T

4T

5T

6T

g L

t0

l0

T1

T2

T3

T4

T5

t

0l1

Figure H.5: Voltage reflection diagram

Example H.2 Suppose that one wishes to know the voltage distribution alongthe line at time t0 shown on Figure H.5. Following the dashed line in this figureone can see that at this time the voltage discontinuity is at position at l0. Tofind the total voltage at this time we add up the incremental voltages for all thereflected waveforms on the line to the desired time. In the case of this specificexample that voltage is:

V (x, t0) = V+1(1 + ρL + ρLρg + ρ2Lρg + ρ2

Lρ2g) for 0 ≤ x ≤ l0 (H.80)

H.4 Time Harmonic Solutions for Lossy Lines 427

and because the waveform has not reached the section from l0 < x ≤ l then:

V (x, t0) = V+1(1 + ρL + ρLρg + ρ2Lρg) for l0 < x ≤ l (H.81)

Suppose, on the other hand, we want to obtain the time dependence of thevoltage at a specific point on the transmission line. Consider the dotted line inFigure H.5. As one proceeds vertically upwards along this dotted line it crossesthe oblique wave propagation lines. Therefore at time T1 the voltage on theline at position l1 is V+1, at T2 the voltage is V+1(1 + ρL), at T3 the voltage isV+1(1 + ρL + ρLρg) and so on. Therefore one is able to plot the voltage on thetransmission line at a particular point against time.

H.4 Time Harmonic Solutions for Lossy Lines

Up to this point we have been considering arbitrary functions propagating downlossless lines. However, it is beneficial to consider the propagation of time har-monic waveforms (such as sine and co-sinusoidal waveforms) down transmissionlines. For example, it is possible to evaluate the impedance of the line, and togenerate frequency response characteristics for lossless lines with these forms ofwaves.

Let us represent the voltage distribution along a line as:

V (x, t) = V (x) cos(ωt + θV ) (H.82)

= −→V (x)ejωt where−→V (x) = V (x)ejθV (H.83)

where θV is in general a function of x, the distance down the transmission line,and ω = 2πf = 2π/T where T the period of the waveform.

This means that at a particular positions down the line the waveform isvarying in magnitude as a co-sinusoidal wave. Note that V (x) is a function ofx, the detail of which depends on the line parameters.

Similarly:

I(x, t) = −→I (x)ejωt where−→I (x) = I(x)ejθI (H.84)

Remark H.18 One can see that−→V (x) and

−→I (x) are phasors in the traditional

circuit sense. The and the ejωt are implied in phasors.

Now let use consider the general differential equations that govern the sys-tem, repeated here for convenience:

∂

∂xV (x, t) = −

[L

∂


](H.85)

∂

∂xI(x, t) = −

[C

∂

∂tV (x, t) + GV (x, t)

](H.86)

Substituting (H.83) and (H.84) into these expressions we can write:

∂

∂xV (x, t) = −L

∂

∂tjω−→I (x)ejωt − R

[−→I (x)ejωt

]= −Ljω−→I (x)ejωt − R

[−→I (x)ejωt

]= −jωL

−→I (x) − R

−→I (x) (making the implicit)

= −(R + jωL)−→I (x) (H.87)


Similarly we can write the following expression for the current equation:

∂

∂x

−→I (x) = −(G + jωC)

−→V (x) (H.88)

These expressions can be written as:

∂

∂x

−→V (x) = −z

−→I (x) (H.89)

∂

∂x

−→I (x) = −y

−→V (x) (H.90)

where:

z = R + jωL (the series impedance) (H.91)y = G + jωC (the shunt admittance) (H.92)

The second order equations are:

∂2

∂x2V (x, t) = −

[L

∂2

∂x∂tI(x, t) + R

∂

∂xI(x, t)

](H.93)

∂2

∂x2I(x, t) = −

[C

∂2

∂x∂tV (x, t) + G

∂

∂xV (x, t)

](H.94)

Let’s consider the first of these expressions. We can immediately say from(H.90) that:

R∂

∂xI(x, t) = −Ry

−→V (x) (H.95)

Now consider the first partial derivative in the first equation:

∂2

∂x∂t

−→I (x) =

∂

∂t(−y

−→V (x)) = −jωy

−→V (x) (H.96)

remembering to put in the ejωt term into the phasor before doing the derivative.Similarly, we can write:

∂2

∂x∂t

−→V (x) = −jωz

−→I (x) (H.97)

Returning to (H.93) and substituting in the above two expressions we canwrite:

∂2

∂x2

−→V (x) = −

[−jωLy

−→V (x) − Ry

−→V (x)

]= (R + jωL)y

−→V (x)

= zy−→V (x) (H.98)

Similarly, for (H.94) we can write:

∂2

∂x2

−→I (x) = −

[−jωCz

−→I (x) − Gz

−→I (x)

]= (G + jω)z

−→I (x)

= zy−→I (x) (H.99)


The parameter γ2 = zy where zy = (R + jωL)(G + jωC).Summary H.2 In summary, the first and second order equations for the timeharmonic waveform case are:

∂

∂x

−→V (x) = −z

−→I (x) (H.100)

∂

∂x

−→I (x) = −y

−→V (x) (H.101)

∂2

∂x2

−→V (x) = γ2−→V (x) (H.102)

∂2

∂x2

−→I (x) = γ2−→I (x) (H.103)

where:

z = R + jωL

y = G + jωC

γ =√

(R + jωL)(G + jωC) =√

zy (H.104)

Remark H.19 Equations (H.102) and (H.103) are simple second order ho-mogeneous differential equations. Much of the complexity has effectively beeneliminated by the use of the phasor description for the signals.

H.4.1 Solutions for Voltage and Currents

The solutions to (H.102) and (H.103) can be seen from inspection to be of thegeneral form:

−→V (x) =

−→V 1e

−γx +−→V 2e

γx (H.105)−→I (x) =

−→I 1e

−γx +−→I 2e

γx (H.106)

where−→V 1,

−→V 2,

−→I 1, and

−→I 2 are constants that depend on the terminal condi-

tions. Note that the first part of the right hand side of these two equationscorrespond, and similarly for the second components of both equations. Eachof the components in each equation are independently solutions to the originaldifferential equations.

Remark H.20 Note that−→V 1,

−→I 1 etc. are phasors. This can easily be seen by

considering the case of x = 0 in (H.105):−→V (x) =

−→V 1 +

−→V 2 (H.107)

Both sides of the equation have to be phasors.

Now let us consider the first expressions on the right hand side of (H.105)and (H.106), and substitute them into (H.100):

∂

∂x

−→V (x) = −γ

−→V 1e

−γx

−z−→I (x) = −z

−→I 1e

−γx

∴ −γ−→V 1e

−γx = −z−→I 1e

−γx (H.108)


Rearranging we can write:

−→V 1−→I 1

=z

y=

√R + jωL

G + jωC= Z0 (H.109)

Similarly for the second components of these equations we can write thefollowing: −→

V 2−→I 2

= −Z0 (H.110)

where the negative sign results from the current and voltage conventions.

Remark H.21 The two components in (H.105) and (H.106) correspond to theforward moving (i.e. positive x direction) and backward moving waves on theline. We had a similar situation when we considered the solution to the trans-mission line equations for arbitrary waveforms.

The relationships (H.109) and (H.110) allow us the write (H.106) in termsof voltages and the characteristic impedance:

−→I (x) =

−→V 1

Z0e−γx −

−→V 2

Z0eγx (H.111)

H.4.2 Semi-infinite Transmission Line

Thus-far we have been considering the solution of the time harmonic equationsfor the infinite transmission line (i.e. infinite in both directions from the signalinjection point). We shall now consider the solution of the equations for a linethat starts at x = 0 and extends infinitely in the positive x direction. As weshall see this simplifies the general solutions (H.105) and (H.106).

Firstly let us consider the constant γ. This is defined as (repeated here forconvenience):

γ =√

(R + jωL)(G + jωC)

=√

(RG − ω2LC) + jω(CR + LG) =√

a + jb (H.112)

Because γ is complex then we can define:

γ2 = (α + jβ)2 = a + jb (H.113)

Expanding the α, β expression and equating real and imaginary parts we canwrite:

(α2 − β2) = (RG − ω2LC) (H.114)2αβ = ω(CR + LG) (H.115)

One can solve these expressions simultaneously to get rather complicated andmessy expressions for α and β. From these expressions it is possible to deducethat α ≥ 0 and β ≥ 0 for all physically realisable transmission line componentvalues.

For the following sections we only need to consider that:

γ = α + jβ (H.116)


Let us consider the implications of a line extending from x = 0 to x = −∞on (H.105):

−→V (∞) =

−→V 1e

γ∞ +−→V 2e

−γ∞ (H.117)

Clearly for this equation to have physical meaning then−→V 1 = 0. This term of

the equation relates to the section of the line that goes in the positive x directionin the infinite transmission line situation.

Similarly, for a line extending from x = 0 to x = ∞ we have:

−→V (∞) =

−→V 1e

−γ∞ +−→V 2e

γ∞ (H.118)

and therefore−→V 2 = 0 for a physically meaningful solution.

Let us from this point only consider the situation of the line from x = 0 tox = ∞. The voltage equation for this line can be written as:

−→V (x) =

−→V 1e

−γx =−→V 1e

−(α+jβ)x (H.119)

Because−→V (x) is a phasor we can reintroduce the ejωt term and take the

real part of the resultant expression (this returns the equation to a time domainexpression):

−→V (x) =

−→V 1e

−γx

=−→V 1e

−αxe−jβx

= V1ejθV1 e−αxe−jβx (H.120)

where θV1 is an arbitrary phase shift in the−→V 1 phasor. It is not the phase shift

θV introduced in (H.83), which is used to represent the total phase shift in thevoltage expression.

Considering the original definition in (H.83) we can now write:

−→V (x) = V (x)ejθV = V1e

−αxej(θV1−βx) (H.121)

and therefore we can see by inspection that:

V (x) = V1e−αx voltage amplitude (H.122)

θV = (θV1 − βx) voltage phase (H.123)

Remark H.22 Equation (H.122) shows that the voltage is attenuated as it trav-els down a lossy transmission line.

Equation (H.123) shows that the phase is proportional to the distance downthe line. This means that there is a modulated co-sinusoidal variation of the am-plitude down the line. It also means that in the time domain that the waveformat some point x has a phase displacement of βx compared to the time waveformat location x = 0.

If we now reintroduce the ejωt and take the Real part so we get:

V (x, t) = V1e−αxej(θV1−βx)

∴ V (x, t) = (V1eαx) cos(ωt + θV1 − βx) (H.124)


Remark H.23 Equation (H.124) shows that γ = α + jβ defines completelythe propagation of sinusoidal time harmonic waveforms down the line. For thisreason γ is called the propagation constant. propagation con-

stantRemark H.24 We know that the co-sinusoidal input waveform is propagatingdown the transmission line with a velocity v. From a time domain point of viewwe know that the waveform will have the same value when:

cos(ωt + θV1) = cos(ωt + θV1 + n2π) (H.125)⇒ ωt = ωt + n2π (H.126)

∴ t = t +n2π

ω; n = 0, 1, 2, 3 · · · (H.127)

i.e. the time changes by 2π/ω for the same value of different points down thetransmission line. Therefore this time will clearly relate to the wavelength of thewaveform on the line.

Remark H.25 In time 2π/ω the waveform will have moved 2πv/ω down thetransmission line. Therefore this distance must define the wavelength of thewavelengthwave on the transmission line.

An alternative expression can be derived by realising that at some particulartime t that there will be multiple points down the transmission line with the samevalue. These points are clearly defined by the condition that:

cos(ωt + θV1 − βx) = cos(ωt + θV1 − βx + n2π) (H.128)

where λ denotes the wavelength of the waveform on the line. For this conditionto hold we can see that equating the right and left sides:

βx = βx + n2π

∴ x = x +n2π

β(H.129)

where x is some arbitrary position down the transmission line, and n = 1, 2, 3, · · · .Equation (H.129) says that at positions n2π/β apart down the line the valuesof the waveform will be the same, therefore this is another expression for thewavelength of the signal on the line:

λ =2π

β(H.130)

We can equate this expression for the wavelength with that mentioned earlierin this remark to give:

2π

β=

2πv

ω

∴ v =ω

β(H.131)

The velocity v is also known as the phase velocity.phase velocity


H.4.3 Finite Length Transmission Lines

In this section we now consider a transmission line that is a finite length –i.e. it is a terminated line. As mentioned when we were considering the generalsolutions for the time harmonic equations, the coefficients in (H.105) and (H.106)are determined by the boundary conditions of the line. In the case of the semi-infinite line one has boundary conditions at the start of the line. In the case ofa finite length line there are boundary conditions at the start of the line as wellas at the end of the line.

If we consider−→V 0 and

−→I 0 to be the specified input voltage and current then

we can determine the constants as follows:

−→V (0) =

−→V 1 +

−→V 2 = V0 (H.132)

−→I (0) =

−→V 1

Z0−

−→V 2

Z0= I0 (H.133)

Solving simultaneously we can write:

−→V 1 =

12(V0 + I0Z0) (H.134)

−→V 2 =

12(V0 − I0Z0) (H.135)

∴ −→V (x) =

12(V0 + I0Z0)e−γx +

12(V0 − I0Z0)eγx (H.136)

Similarly:

−→I (x) =

12Z0

(V0 + I0Z0)e−γx − 12Z0

(V0 − I0Z0)eγx (H.137)

Equations (H.136) and (H.137) can be written more succinctly using therelations:

cosh y =ey + e−y

2(H.138)

sinh y =ey − e−y

2(H.139)

Therefore the equations for the waveform distribution down the transmissionline with source boundary conditions become:

−→V (x) = V0 cosh(γx) − I0Z0 sinh(γx) (H.140)−→I (x) = −V0

Z0sinh(γx) + I0 cosh(γx) (H.141)

An alternative formulation is to specify the boundary conditions at the loadend of the finite length line. Consider the transmission line to have a totallength of l, i.e. starting at x = 0 and ending at x = l. At x = l let the voltagebe

−→V L and the current be

−→I L. Substituting these boundary condition into


(H.105) and (H.111) one can write:−→V 1e

−γl +−→V 2e

γl = VL (H.142)−→V 1

Z0e−γl −

−→V 2

Z0eγl = IL (H.143)

Solving these simultaneously we can write the coefficients as:−→V 1 =

12(−→V L +

−→I LZ0)eγl (H.144)

−→V 2 =

12(−→V L −−→

I LZ0)e−γl (H.145)

We also know that−→V L =

−→I LZL, where ZL the terminating impedance.

Therefore we can write the coefficients as:

−→V 1 =

−→I L

2(ZL + Z0)eγl (H.146)

−→V 2 =

−→I L

2(ZL − Z0)e−γl (H.147)

which allow us to write the general voltage and current equations in a form thatcontain the terminating impedance of the line:

−→V (x) =

−→I L

2

[(ZL + Z0)eγ(l−x) + (ZL − Z0)e−γ(l−x)

](H.148)

−→I (x) =

−→I L

2Z0

[(ZL + Z0)eγ(l−x) − (ZL − Z0)e−γ(l−x)

](H.149)

Realising that (l−x) is the distance from the termination to the point of intereston the line, and again using the cosh and sinh relationships we can write:

−→V (x) =

−→I L [ZL cosh(γs) + Z0 sinh(γs)] (H.150)

−→I (x) =

−→I L

Z0[Z0 cosh(γs) + ZL sinh(γs)] (H.151)

where s = (l − x)

and l the total length of the line

H.4.4 Line Input Impedance

Consider the line in the previous section of length l and terminated with aload impedance of ZL. The circuit under consideration is shown in Figure H.6.Notice that we are assuming in this figure that the transmission line can berepresented as an equivalent input impedance.

From figure H.6 we can see that:

−→I 0 =

−→V s

Zs + Zin(H.152)

−→V 0 =

−→V sZin

Zs + Zin(H.153)


Zin

Zin Zs

Zs

rVs

rVs

ZL

x 0 x l

rI

L

rV

0

rV

0

rI

0

rI

0

+

-

+

-

Figure H.6: Terminated transmission line and the equivalent circuit

Therefore if we know Zin then we can work out the−→V 0 and

−→I 0 coefficients and

substitute them into (H.140) and (H.141) to get the complete solution for theline.

The general expression for the impedance for the line at any position x canbe found from the ratio of (H.150) and (H.151) to give:2

Z(x) =−→V (x)−→I (x)

=−→I L[ZL cosh(γs) + Z0 sinh(γs)]−→I L

Z0[ZL sinh(γs) + Z0 cosh(γs)]

= Z0

[ZL cosh(γs) + Z0 sinh(γs)ZL sinh(γs) + Z0 cosh(γs)

](H.154)

= Z0

[ZL + Z0 tanh(γs)Z0 + ZL tanh(γs)

](H.155)

where tanh(γs) =sinh(γs)cosh(γs)

The input impedance for a general terminated line can be written from(H.154) by realising that for the input impedance s = l (i.e. x = 0). Thereforethe expression is:

Zin = Z(0) = Z0

[ZL cosh(γl) + Z0 sinh(γl)ZL sinh(γl) + Z0 cosh(γl)

](H.156)

2Remember that s = l − x.


H.4.4.1 Lossless Line Input Impedance

Let us now consider the simplified situation of the lossless transmission line.Under this condition we have:

R = 0 G = 0 (H.157)

therefore we can write γ as follows:

γ =√

(jωL)(jωC) =√−ω2LC

∴ γ = jβ (and β = ω√

LC) (H.158)

In one uses this new definition of γ into the expressions for cosh(γl) andsinh(γl) we can write the following:

cosh(γl) = cos(βl) and sinh(γl) = j sin(βl) (H.159)

Making these substitutions into (H.156) we can get the input impedance for alossless line:3

Zin = Z0

[ZL cos(βl) + jZ0 sin(βl)jZL sin(βl) + Z0 cos(βl)

](H.160)

H.4.5 Transfer Function of a Lossless Transmission Line

Consider (H.140) with x = l. This gives us an expression for the load voltagein terms of the line input voltage

−→V 0:

−→V L =

−→V 0[cos(βl) − j

Z0

Zinsin(βl)] (H.161)

since−→I 0 =

−→V 0/Zin, and Zin is defined in (H.160).

From the equivalent circuit in (H.6) one can see that:

−→V 0 =

Zin−→V s

Zin + Zs(H.162)

and hence the basic transfer function can be written as:−→V L−→V 0

=(

Zin

Zs + Zin

)[cos(βl) − j

Z0

Zinsin(βl)

](H.163)

This basic equation can be further manipulated by including the definitionfor Zin. Considering the first term on the right hand side of (H.163) we canwrite:

Zin

Zs + Zin=

Z0[ZL cos(βl) + jZ0 sin(βl)][(ZsZ0 + Z0ZL) cos(βl) + j(Z2

0 + ZsZL) sin(βl)](H.164)

Now considering the second term in (H.163) we can write:

cos(βl) − jZ0

Zinsin(βl) =

ZL

ZL cos(βl) + jZ0 sin(βl)(H.165)

3Note that Z0 =√

LC

for a lossless line.


Combining these two terms we can write the transfer function as:

−→V L−→V s

=Z0ZL


(H.166)

Equation (H.166) can be used as a starting point for carrying out a frequencydomain analysis of a transmission line with a particular loading on it.

H.4.6 Thevenin Equivalent Circuit

One can use all the information we currently have to develop a Thevenin equiv-alent circuit of the transmission line. Figure H.7 shows the structure of theThevenin equivalent circuit.

Zeq

rVse

ZL

rI

L

rV

L

+

-

Figure H.7: Thevenin equivalent circuit of a transmission line

Let us begin with the equivalent impedance of the line looking from the loadend towards the source. In order to find this the normal technique is to shortcircuit the source voltage and then work out the impedance looking from theload. In this particular case we can use the results we have in (H.160) to do thisbecause of the symmetry on the system. We simply need to replace ZL with Zs

in the input impedance expression which gives:

Zeq = Z0

[Zs cos(βl) + jZ0 sin(βl)Z0 cos(βl) + jZs sin(βl)

](H.167)

To find the equivalent source voltage one has to work out the current flowingat the load point if the load is replaced with a short circuit. We can use (H.163)to express the load voltage for a general load ZL in the following expression for


the load current:

−→I L =

−→V L

ZL=

[Z0ZL

−→V s

(ZsZ0+Z0ZL) cos(βl)+j(Z20+ZsZL) sin(βl)

]ZL

=Z0

−→V s


(H.168)

If ZL = 0 then this expression can be simplified to:4

−→I L =

−→V s

Zs cos(βl) + jZ0 sin(βl)(H.169)

If one considers the equivalent circuit of Figure H.7 then the load current is:

−→I L =

−→V se

Zeq

=[Z0 cos(βl) + jZs sin(βl)]

−→V se

Z0[Zs cos(βl) + jZ0 sin(βl)](H.170)

The currents in the actual line and the equivalent circuit under the conditionof a short circuited load have to be the same, therefore equating (H.169) and(H.170) and then simplifying we can write:

−→V se =

Z0−→V s

Z0 cos(βl) + jZs sin(βl)(H.171)

4Note that with ZL = 0 then implicitly−→V L = 0.

Appendix I

Useful Formulae

I.1 Introduction

This appendix contains a number of formulae that are useful in the area oftransmission lines, especially when they occur in digital transmission systems.Most of the expressions here can be found scattered throughout the literature,but one reference that collects them together in one place is [1]. The expressionsin this reference are almost all in imperial units. We shall use MKS units inthis appendix where appropriate. In some cases imperial units will still be usedbecause these are the units that are used extensively in the literature.1

I.2 Useful Constants

Table I.1 shows some constant that are useful when carrying out calculationsinvolving electric and magnetic fields.

I.3 Formulae

I.3.1 AWG Related Conversions

Equations (I.1) and (I.2) allows the American Wire Gauge to be converted to awire diameter in metres and vice-versa.

AWG = −10 − 20 log(d

0.0254) (I.1)

d = 2.54 × 10−[AWG+1020 −2] m (I.2)

Equation (I.3) allows one to obtain the resistance of a round wire given itsdiameter (or AWG) and length in metres:

R =4ρl

πd2(1 + (T − 20)δρ) (I.3)

1For example, imperial units are used almost exclusively in PCB measurements, becausemuch of the sofrtware used in this industry has been written in the USA, or its target marketis in the USA.

440 Useful Formulae

Constant Value

Permittivity of free space (ε0) 8.854 × 10−12 Farad/mPermeability of free space (µ0) 4π × 10−7 Henry/mSpeed of light (c) 2.998 × 108metres/secBulk resistivity of copper (ρ) ab 1.724 × 10−8Ω − mBulk resistivity of copper (ρ) c 1.671 × 10−8Ω − mTemperature coefficient of copper resistivity (δρ) d 3.9 × 10−3/C

aThis value takes into account the changes in the resistivity due to the annealing processand the chemical imperfections caused by the manufacturing process for wires.

bThe resistivity can be thought of as the resistance of the 1m3 block of material.cThis ¡ is the conventional value for the resistivity of copper at 20.dThis quantity of defined as 1

ρdρdt

.

Table I.1: Useful constants

where T the temperature in C, l the length of the wire in metres, d the diameter of the wire in metres, ρ the resistivity in Ω-m, and δρ theresistivity temperature coefficient.

I.3.2 Copper Plate Weight Formulae

Printed circuit boards (PCBs) usually specify the thickness in terms of thecopper plate weight (CPW) value. This is the weight of 1in2 of the copperplating on the board in the imperial unit of ounces.

The expression to convert the CPW value into a plate thickness in inches is:

t = 0.00137 × CPW (inches) (I.4)

Clearly to convert this to a metric unit we need to multiply by the appropriateconversion factor. Since there are 25.4mm/in then the thickness in mm is tm =25.4t = 0.034798 × CPW, and in metres tm = 0.0254t = 0.000034798 × CPW,where tm denotes that the thickness in metric units.

One can clearly combine (I.4) with (I.3) to get the resistance of a PCB trace:

R =ρl

0.000034798(CPW)w(1 + (T − 20)δρ) (I.5)

where w the width of the PCB trace in metres.2

If we consider the resistance of a ground plane then the non-uniform dis-tribution of the current must be accounted for. One approximation to accountfor this is to consider two contact points to the ground plane. These contactpoints have a certain diameter which are denoted as d1 and d2 metres. Thesetwo contact points are l metres apart. An expression for the effective resistance

2Equation (I.5) assumes that the current is uniform across the cross-section of the trace.This assumption is good for normal PCB traces, but breaks down with wide structures suchas ground and power supply planes.

I.3 Formulae 441

between these two points on the plane is:

R =ρ

2πtm

[ln[

2l

d1

]+ ln

[2l

d2

]](1 + (T − 20)δρ) (I.6)

or R =ρ

0.000069596(CPW)π

[ln[

2l

d1

]+ ln

[2l

d2

]](1 + (T − 20)δρ) (I.7)

Note I.1 If the contact points are near the edge of the plane then the resistancevalue calculated by (I.6) can increase by a factor of two. If the contact point isnear a corner then it will increase by an even larger factor.

I.3.3 Parallel Plate Capacitance

w

l

h

Dielectric

Figure I.1: Parallel plate capacitor.

Figure I.1 shows a generic parallel plate capacitor. It is assumed that the ma-terial between the plates has a dielectric constant of ε = εrε0. The capacitanceof the system is:

C =εA

h=

εlw

hFarads (I.8)

I.3.4 Inductance of Circular Wire Loops

The expression for the inductance of a circular loop of wire is:

L = µ0a

[ln(

8a

R

)− 2

](I.9)

where:

a the loop radius

R the wire radius

Remark I.1 Note the weak dependence of the inductance with respect to thewire radius. This is a result of the ln function in (I.9). However, the inductanceof the loop is strongly dependent on the radius of the loop.

442 Useful Formulae

I.3.5 Inductance of Rectangular Loops

Similar to the previous expression we can define the inductance of a rectangularloop as:

L = 4 × 10−9

x ln

[2y

d

]+ y ln

[2x

d

](I.10)

where:

L the inductance in nH

x the length of the rectangular loop in cm

y the width of the rectangular loop in cm

d the diameter of the wire in cm

I.3.6 Mutual Inductance of Two Loops

The following expression calculates the mutual inductance of two circular loopsof wire. It should be noted that the loops must be well separated for thisexpression to be valid. Furthermore, is is assumed that the loops are flat,and their surface areas are parallel to each other for maximum coupling. Theexpression for the maximum mutual coupling is:

Lm =2A1A2

d3(I.11)

where:

d separation of the loops in cm

A1 the surface area of loop 1 in cm2

A2 the surface area of loop 2 in cm2

Equation (I.11) is valid for:

d >√

A1

d >√

A2

I.3.7 Mutual Inductance of Parallel Transmission Lines

The following expression gives the mutual inductance between two round orsquare parallel wires suspended above a ground plane. The units of the mutualinductance expression depend on the units of self inductance for one of the trans-mission lines (use an appropriate expression for this). The mutual inductanceexpression is:

Lm = L

[1

1 +[

sh

]2]

(I.12)

where:

s separation between wires in cm

h height of wire above the ground plane in cm

L the self inductance of one of the parallel wires

I.3 Formulae 443

I.3.8 General Transmission Line Expressions

This section contains some general expressions used for generic transmissionlines.

Characteristic Impedance

Z0 =√

L0

C0(I.13)

Propagation delay per cmD =

√L0C0 (I.14)

Propagation delay per cm given effective permittivity

D = 3.356 × 10−11√εreff (I.15)

Capacitance per cm

C0 =D

Z0(I.16)

Inductance per cmL0 = DZ0 (I.17)

where:

L0 inductance per cm

C0 capacitance per cm

D propagation delay per cm

εreff effective relative permittivity

I.3.9 Coaxial Transmission Line

d1d

2

Dielectric material with

relative permittivity of r

Figure I.2: Coaxial cable cross-section.

Figure I.2 shows the cross-section of a coaxial cable. The relevant transmis-sion line characteristic impedance expression is:

Z0 =60√εr

ln[d2

d1

](I.18)

444 Useful Formulae

The inductance and capacitance of the coaxial transmission line are respec-tively:

L = (2.002 × 10−9)x ln[d2

d1

](I.19)

C =(5.56 × 10−13)xεreff

ln[

d2d1

] (I.20)

where x the length of the cable in cm.

I.3.10 Single Wire Above a Ground Plane

d

h

Assume airdielectric

Figure I.3: Round wire suspended above a ground plane.

Figure I.3 shows the situation of a round wire suspended in air above aground plane. This is the situation that occurs in a wire wrap board layout.The relevant expressions for this are:

Z0 = 60 ln[4h

d

](I.21)

where:

d the diameter of the round wire in cm

h the height of the wire above the ground plane in cm

One of the advantages of wire wrap is that the propagation delay per cmis as fast as it can be – i.e. 3.336 × 10−11 sec/cm or 33.36 psec/cm. This isbecause it operates in an air dielectric.3

The total inductance of the wire trace can be found using (I.17) and multi-plying by the length of the trace:

L = (2.002 × 10−9)x ln[4h

d

](I.22)

3We are assuming in this that the ground plane is on top of the supporting PCB material.In many situations this may not be the case, and consequently the relative dielectric will begreater that 1 and the propagation velocity will be lower.

I.3 Formulae 445

where x the length of the wire trace in cm.Similarly the total capacitance of the wire can be calculated using (I.16) and

multiplying by the length:

C =(5.560 × 10−13)x

ln[

4hd

] (I.23)

where x the length of the wire trace in cm.

I.3.11 Twisted Pair Transmission Line

Twisted pair cables are used extensively for interconnection of systems. For ex-ample, the copper cabling from your house to the telephone exchange is twistedpair cable with a characteristic impedance of approximately 600Ω.

d

s

Insulation and dielectricmaterial

Surrounding dielectricis air

Figure I.4: Configuration of twisted pair transmission line.

Figure I.4 shows the configuration of the twisted pair conductors. The effec-tive permittivity of the conductors depends on the degree of twist of the cables,since this alters the amount of flux the flows through the insulation dielectricand air. Suffice to say, the effective dielectric constant will be greater than onefor insulated wire.

The relevant expressions of this transmission line are:

Z0 =120√

εreff

ln[2s

d

](I.24)

Propagation delay per cm:

D = 3.336 × 10−11√εreff (I.25)

Total inductance of the twisted pair transmission line can be calculated usingthe length of the line and (I.17) to give:

L = (4.003 × 10−9)x ln[2s

d

](I.26)

446 Useful Formulae

and similary the total capacitance for the transmission line is:

C =(2.78 × 10−13)xεr

ln[

2sd

] (I.27)

where x the length of the line in cm.

I.3.12 Microstrip Transmission Line

Microstrip transmission lines are equivalent to tracks laid out on a conventionalPCB, where the track is either on the top or the bottom layer of the board (asin a 4 layer PCB with the ground and positive supply planes in the middle ofthe board).

The following equations give approximate expressions for the characteristicimpedances of the microstrip [23]. A field solver is required to obtain moreaccurate results. It should be noted that the equations have limitations onthe relative dimensions of the strip lines so that reasonable accuracy can beobtained. The following discussion is with reference to Figure I.5.

w

h

t

Dielectric constant r

Figure I.5: Dimensions of a microstrip transmission line.

The following expressions are accurate for:

0.25 ≤w

h≤ 6

1 ≤εr ≤ 16

Z0 =√

µ0ε0εe

1Ca

(I.28)

Ca =

2πε0

ln( 8hw + w

4h ) when wh ≤ 1

ε0[

wh + 1.393 + 0.667 ln

(wh + 1.444

)]when w

h > 1(I.29)

εe =εr + 1

2+

εr − 12

(1 +

12h

w

)− 12

+ F − 0.217(εr − 1)t√wh

(I.30)

F =

0.02(εr − 1)(1 − w

h

)2 when wh < 1

0 when wh > 1

(I.31)

where:

εe the effective permittivity

I.3 Formulae 447

Equation (I.29) has a lower limit of 0.25 for the w/h ratio. An approximateexpression for the characteristic impedance that will give values for smaller w/hratios is:

Z0 =87√

εr + 1.41ln(

5.68h

0.8w + t

)(I.32)

which is valid when 0.1 < w/h < 2.0 and 1 < εr < 15.

I.3.13 Symmetric Stripline Transmission Line

w

h

t


Figure I.6: Dimensions of a symmetric stripline.

The following expression are for a stripline where the interior conductor isin the middle of the top and bottom planes, as shown in Figure I.6 [1]. Thefollowing expressions are accurate for:

t

h< 0.25

t

w< 0.11

For wh < 0.35 (i.e. a narrow line):

Z0sym =60√εr

ln4h

πK1(I.33)

K1 =(w

2

)[1 +

t

wπ

(1 + ln

4πw

t

)+ 0.255

(t

w

)2]

(I.34)

For wh > 0.35 (i.e. a wide line):

Z0sym =94.15

√εr

(w

h−t + K2π

) (I.35)

K2 =2

1 − th

ln(

11 − t

h

+ 1)−(

11 − t

h

− 1)

ln(

1(1 − t

h )2− 1

)(I.36)

I.3.14 Offset Stripline Transmission Line

Figure I.7 shows the dimensions of an offset transmission line [1]. The charac-teristic of this line is obtained from those of the symmetric line. It should be

448 Useful Formulae

wt


b

a

Figure I.7: Dimensions of the offset transmission line.

noted that these equations are an approximation, and a field solver should beused for more accurate results:

Z0offset = 2Z0sym(h1, w, t, εr)Z0sym(h2, w, t, εr)

Z0sym(h1, w, t, εr) + Z0sym(h2, w, t, εr)(I.37)

where:

h1 = 2a + t

h2 = 2b + t

Bibliography

[1] Howard W. Johnson and Martin Graham. High-Speed Digital Design – AHandbook of Black Magic. Prentice-Hall, 1993. ISBN 0-13-059973-5.

[2] Ferroxcube. Ferroxcube Selection Guide. Available: http://www.-ferroxcube.com.

[3] Ferroxcube. Ferroxcube Data Manual. Available: http://www.ferroxcube.-com.

[4] Ned Mohan, Tore M. Undeland, and William P. Robbins. Power Electronics– Converters, Applications and Design. John Wiley and Sons, 2nd edition,1995. ISBN: 0-471-58408-8.

[5] John F. Wakerly. Digital Design – Principles and Practices. Prentice-Hall,2nd edition, 1994. ISBN 0-13-395724-1.

[6] Neil H.E. Weste and Kamran Eshraghian. Principles of CMOS VLSI De-sign – A Systems Perspective. Addison-Wesley, 1985. ISBN 0-201-08222-5.

[7] Harold A. Wheeler. Formulas for the skin effect. Proceedings of the I.R.E.,pages 412–424, September 1942.

[8] H.B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addi-son Wesley, Reading, Mass., 1990.

[9] Stephen H. Hall, Garrett W. Hall, and James A. McCall. High-Speed DigitalSystem Design. Wiley Interscience, 2000. ISBN: 0471360902.

[10] T.C. Edwards. Foundation for Microstrip Circuit Design. John Wiley andSons, New York, New York, 1983.

[11] Muhammad H. Rashid. Power Electronics – Circuits, Devices and Appli-cations. Prentice-Hall, 2nd edition, 1993. ISBN: 0-13-334483-5.

[12] Abraham I. Pressman. Switching Power Supply Design. McGraw Hill, 2ndedition, 1998. ISBN: 0070522367.

[13] Ron Lenk. Practical Design of Power Supplies. IEEE Press/McGraw-Hill,1998. ISBN:0-7803-3458-2 or 0-07-134324-5.

[14] Texas Instruments. Modelling, analysis and compensation of the current-mode converter. Available from www.ti.com, Application Note U 97.

450 BIBLIOGRAPHY

[15] Gordon R. Slemon. Electric Machines and Drives. Addison-Wesley, 1992.ISBN: 0-201-57885-9.

[16] V. Gourishanker. Electro-mechanical Energy Conversion. InternationalTextbooks in Electrical Engineering. International Textbook Company,1965.

[17] Thomas H. Barton. Rectifiers, Cycloconverters and AC Controllers. OxfordUniversity Press, 1994.

[18] W. Shepherd and L.N. Hulley. Power Electronics and Motor Control. Cam-bridge University Press, 1987.

[19] Erwin Kreyszig. Advanced Engineering Mathematics. John Wiley and Sons,1972.

[20] Peter Vas. Vector Control of AC Machines. Number 22 in Monographs inElectrical and Electronic Engineering. Oxford University Press, New York,1990. ISBN 0-19-859370-8.

[21] R.E. Betz and B.J. Cook. A digital current controller for three phase voltagesource inverters. Technical Report EE9702, School of Electrical Engineeringand Computer Science, University of Newcastle, Australia, 1997. Availableat: http://www.eecs.newcastle.edu.au/users/staff/reb.

[22] S.R. Seshadri. Fundamentals of Transmission Lines and ElectromagneticFields. Addison-Wesley, 1971. ISBN: 0-201-06722-6.

[23] Robert Collins. Foundations of Microwave Engineering. McGraw-Hill, NewYork, 1992.

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