Suspended 60 GHz Phased Array Antenna With High Efficiency Kaveh Keshtkaran and Nima Ghalichechian Electroscience Laboratory Department of Electrical and Computer Engineering The Ohio State University, Columbus, OH, USA E-mail: [email protected], [email protected] Abstract—This paper presents 5×5 aperture coupled mi- crostrip patch phased array antenna with suspended radiating el- ements operating at 60 GHz. A novel microfabrication technique enables separation of radiating elements from a lossy substrate. It was found that suspended elements improve efficiency and scanning range without sacrificing gain of the array by decreasing trapped energy at air dielectric boundary (surface waves). The array has a bandwidth of 7.5 GHz (12.5%) and capable of scanning ±60 ◦ in both E and H planes. Total array efficiency is calculated to be >90%. Simulation results show 18.6 dB gain with -12 dB sidelobe level at boresight. Furthermore, array gain is 15 dB and 14.5 dB when scanning ±60 ◦ in E and H-planes, respectively. Keywords—Suspended, MEMS, Phased array, Large Scanning. I. I NTRODUCTION The 60 GHz band has received much attention due to the its unique properties such as high data rate transmission and 7.5 GHz bandwidth allocated by FCC, which offers important benefits for secure multi-gigabit communication. As a result of high absorption by oxygen molecules (O 2 ) at 60 GHz, large amount of wave energy dissipates in atmosphere which lower the detection range. This behavior make 60 GHz band attractive for secure short range communication such as wireless personal-area networks (WPANS)[1][2] as well as satellite cross-link communication. Microstrip antennas are commonly used for satellite, aircraft and defense applications due to the planar and lightweight structure [3]. However, when miniaturized on a substrate for millimeter wave application, they suffer from low efficiency due to excitation of higher-order-mode surface waves at the boundary of air dielectric as well as conductive and dielectric losses [4]. It is known that increasing dielectric thickness and permittivity cause excitation of higher-order-mode surface waves in the antenna substrate that increases coupling between array elements and reduces antenna efficiency [5][6]. In scan- ning arrays, as the scanning angle increases, large amount of energy is trapped at surface (blind spot) because of higher- order-mode surface waves excitation [5]. This non-radiating energy at the surface, reduces array’s overall efficiency. One way to reduce the surface waves and improve the efficiency is to implement air cavity in the substrate or Elec- tromagnetic Band-Gap (EBG) structures to lower the effective dielectric constant [7–9]. There has been intensive research regarding cavity fabrication to modify the gain and bandwidth. For example, Yeap el at. [10] showed that partial substrate removal in an LTCC substrate reduces the surface waves, dielectric loss and improves gain of the antenna. Although the effect of decreasing effective dielectric constant has been studied, little attention has been paid to fabricating new types of structures. This paper presents monolithic fabrication and simulation results for aperture coupled microstrip antenna (ACMPA) [11] with suspended patch. Relative dielectric con- stant of conventional substrates for high frequency applications are ranged between 2 to 12. In contrast, by suspending the patch antenna with aperture coupled feeding, effective dielectric constant of patch substrate is reduced to 1. This increases the efficiency of the antenna by reducing surface waves and dielectric loss. Furthermore, this antenna array is able to scan more efficiently than conventional patch array antennas. Unlike the previous work that implements suspended ACMPA on a single PCB-based antenna [12], this work enables monolithic fabrication of high efficiency phased array on a silicon or silica substrate. II. FABRICATION 5×5 ACMPA antenna array involves fabricating suspended patches over a fused silica substrate with low dielectric loss at millimeter wave band. For the array, 1.65×1.65 mm 2 suspended square patches are positioned 300 μm above the center of 1550×155 μm 2 slots on the ground plane. To start, ground plane with slots and feed lines with 700-μm- width are fabricated on the two sides of the 300-μm silica substrate(tanδ ’ 0.0002)[13]. A 300-μm-thick photoresist (SU-8) layer is spin coated on the wafer followed by UV exposure for transferring the mask pattern (circular posts) to the SU-8 layers. SU-8 is great choice for high frequency MEMS applications due to known electrical properties [14] as well as ability to form thick high resolution structures. Silicon dioxide layer film is deposited on the photoresist followed by gold deposition. The gold and dielectric layers are etched to form 1.65×1.65 mm 2 square patches and membranes. Wafer is immersed in developer solution to remove unexposed SU-8 regions and form posts to hold suspended patches. For testing purposes, a spacer with 0.65 mm thickness is used to place 978-1-5090-0267-2/16/$31.00 ©2016 IEEE 37