SUPELEC 07FINAL4 SENSE ANIMACIO - Supélec · Supelec, 19 April 2007. ... Demod Filtro Plataforma Hardware Communication Services ... Matched Filter 4 160MOPS 4-Finger RAKE Channel

Software RadioAntoni Gelonch

Mobile Communications Research Group (GRCM)Signal Theory and Communications Dept. Universitat Politècnica de Catalunya

Supelec, 19 April 2007

Software Defined Radio (SDR)SDR is a set of HW/SW technologies that should facilitate the use of system with reconfigurable architectures in the wireless networks.

Interest?SDR is an efficient way and a cheap solution to solve the problem to develop multimode, multiband and multifunction devices that can be adapted, updated and improved through software updates.

Software Radio – Functional Vision

Militar Escenario

Civil EscenarioNew Technologies for Radio Systems:Multiservice, multi-estandard, multi-band: reconfigurables?

User Needs•Multiples Locations•Multiples Environments•Multiples Radio Interfaces•InterNetworks Connectivity

Software Radio: is defined as a radio system where digitalization is made in the antenna and all the signal processing is done by means of software using reconfigurable high speed processors.

Different systems with performances defined by Software

Software Instalation andUpdate:

• in manufacture• by memory modules• via downstreaming

Software Radio – Concept

Antenna

Beam forming, Interference reduction, SDMA (Space Division Multiple Access), Diversity Inteligent Antennas, Arrays

RF Conversion FI Processing Base Band Bits Flow Source

RF/FI Filtering Power AmplifierRF to FI Conversion

Sampling. AD & DADigital Channel FilteringBase Band Conversion Frequency Synthesis Carrier Recovery

Modulation/DemodulationPre-distortionChannel EstimationEqualisationDecodificationSynchronization

Users MultiplexingEstimation and Quality Control Frame alignmentEncryption Signalling, Control, Management and Maintenance

Voice and Video Codecs, etc

Generic Transmitter/Receiver

SOFTWARE

Software Radio: is defined as a radio system where digitalization is made in the antenna and all the signal processing is done by means of software using reconfigurable high speed processors.


Antenna

Beam forming, Interference reduction, SDMA (Space Division Multiple Access), Diversity Inteligent Antennas, Arrays

RF Conversion FI Processing Base Band Bits Flow Source

RF/FI Filtering Power AmplifierRF to FI Conversion

Sampling. AD & DADigital Channel FilteringBase Band Conversion Frequency Synthesis Carrier Recovery

Modulation/DemodulationPre-distortionChannel EstimationEqualisationDecodificationSynchronization

Users MultiplexingEstimation and Quality Control Frame alignmentEncryption Signalling, Control, Management and Maintenance

Voice and Video Codecs, etc

Generic Transmitter/Receiver

Technology StatusConversion Digital to Analog point

Analogic Digital01001100110…

Computing DemandDepends on the signal bandwidth (information size) and the complexity of the operation performed inside each one of the processing segments: FI, base-band, data flow control and data source.

D=DFI+N*(Dbb+Dbs+Ds)+DoDFI: FI demand, Dbb: Base band demand,Dbs: Data Flow control demand, Ds: Source demand,Do: Additional demand for signalling to access to the radio networkN: number of simultaneous users

Segment Parameter Illustrative values Computing DemandWa 10 MHz

(oversamplig 2.5)FI

FI Filter 100 Ops/HzDFI=2500 MIPS*

Users N 30/cellWc 30 kHzBase BandDemodulator 50 Ops/Hz

Dbb=1.5 MIPS

Rb 32 kb/sBits FlowFEC, signalling 100 Ops/b/s

Dbs=3.2 MIPS

Source Codec CELP 1.6 MIPS/user Ds=1.6 MIPS/userSignalling SS7 2 MIPS/Base Station Do=2 MIPSAddition MIPS DSP D=142.6 MIPS* DFI not incluyed in D


•Digital to Analog Conversion

•Computing Management

SDR: Main Hardware Implications

SDR Platforms: Heterogeneous Distributed ComputingHardware Platform Composed of multiple processors (different) that provides the computational and communication requirements demanded by and SDR application

• Layered System• Multithread Processing

(Parallelism)• Modularity• Software-Hardware Mapping• Internal/external connectivity• Efficient Resource Management• Reconfiguration Management

Topics Addressed

SDR: Computing Management

Servicios de Comunicaciones

Robustez, Isocronismo, Multiples Servicios (Bandas, Modos), Bridging

AplicacionesRadio Codificación

DecodificaciónFuente

Serviciosy

Soporte deRed

INFOSECCodificación


Modem IFProcessing

RFChannelAccess

Formas de onda especificas

InfraestrucrturaReal -Time CORBA/IDL

Capa Tunel Capa JAVA Conflictos

Gestión Recursos MiddlewareArquitectura Abierta

Control Conjunto

Detección de Conflictos

Hardware FPGA

ADsy

DAsASICs

Multiples

Multiples OSNivel de Sistema Operativo

FiltroDemod

PlataformaHardware

Communication ServicesRobustness, Isochronisms, Multiples Services, Bridging, Applets/Scripts, Low-Cost Upgrades (Over-the-Air-Downloads)

Radio Applications Codificación


Servicesand

NetworkSupport

INFOSECSource Coding

Modem IFProcessing

RFChannelAccess

Specific Waveforms

Radio Infrastructure

Software Layer, Interface Radio JAVA Layer Conflicts

Resource Management MiddlewareOpen Architecture

Common Control

Conflicts Detection

Hardware FPGA

ADsandDAs

ASICsMultiples DSPs and GPPs

Multiples OSOperating System Level

FilterDemod

HardwarePlatform R

adio

Pla

tfor

m

Layered ApproachSDR: Computing Management

SDR Requirements (Management)Software Framework

Implementation of a Radio Application independently of hardware: Hardware Abstraction Layer (HAL).Define a Virtual Context not related to any particular hardware architecture.

Hide processor and platform heterogeneity to the radio application.

Run-Time and Development supportCapacity to load the required software on each processor.

Software scheduling, mapping, etc.

Software monitoring.

Specific Libraries for each hardware platform.


HAL

Hardware

OperatingSystem Services

OS API

Application

Different Layer ViewsOS Layer Stack

Platform 2.e.g. with API forcommunications

HW HW HW

Abstraction AbstractionAbstraction

Different Abstraction Depths

Application

P-HAL Layer Stack

P-HAL Abstraction Level

Platform 3.e.g. with OS

Platform 1.e.g. pure hardware

P-HAL ConceptSDR: Computing Management

Execution Approach DSP and FPGA offer a different execution paradigm

DSP: time-divisionFPGA: area-division Very different P-HAL Implementation

T1 T2 T3 T4 T5

P-HAL front-endP-HAL local

Dispatch kernelTasks P1

P-HAL localDispatch kernel

Tasks P2


Tasks P3


Tasks P4

DS

P4

DS

P3D

SP2

DS

P1

Local bus

I/O Interface

VME Interface

P-HAL front-endP-HAL local

Dispatch kernelTasks P1


Tasks P2


Tasks P3


Tasks P4

DS

P4

DS

P3D

SP2

DS

P1

Local bus

I/O Interface

VME Interface

Sequential Execution

DSP FPGA

Parallel Execution

T1 T2 T3

T4T5


APPLICATIONOBJECTS

VHDVHDCC

P-HALSolaris

P-HALLinux

P-HALDSP (P4291) P-HAL

FPGA (SHaRe)

P-HAL SOFTWARE LOAD LAYER

Development FlowDSP and FPGA have a different development flow. Drawback!!

Common Description Language


OUTPUT


DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS

InterpolatorDecimator

46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRC

ChannelEstimation92MOPSf < 1KHz

fs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

fs = 65MHz

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC

PhysicalChannelMapping

PhysicalChannelSegmen-

tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk

Segment.11.7MOPS0.2MOPS

0.384MBPS 1.15MBPS

10M

OPSMatched

Filter 4

MatchedFilter 4

DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC

ChannelEstimation92MOPS


DCH

f < 1KHz

fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3

fs = 65MHzfs = 65MHz

2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk


0.384MBPS0.384MBPS 1.15MBPS1.15MBPS

(480*16)kbps

105M

OPS

2nd

Insertionof DTX

Indication

2nd

Insertionof DTX

Indication

MatchedFilter 4MatchedFilter 44


Not neededNot needed

DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



10M

OPSMatched

Filter 4MatchedFilter 44


DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



DCH

f < 1KHz

fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



(480*16)kbps

105M

OPS

2nd

Insertionof DTX

Indication

2nd

Insertionof DTX

Indication


MatchedFilter 4MatchedFilter 44MatchedFilter 44MatchedFilter 4444

Not neededNot neededNot neededNot needed

DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRC


fs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

fs = 65MHz

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk


0.384MBPS 1.15MBPS

10M

OPSMatched

Filter 4

MatchedFilter 4

DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



DCH

f < 1KHz

fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



(480*16)kbps

105M

OPS

2nd

Insertionof DTX

Indication

2nd

Insertionof DTX

Indication




DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



10M

OPSMatched



DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



DCH

f < 1KHz

fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.4

x 40

00M

OPS

Max

imum

Sea

rch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



(480*16)kbps

105M

OPS

2nd

Insertionof DTX

Indication

2nd

Insertionof DTX

Indication




MFI-QSR

CHIPSYNC

OUTPUT


P5

P1 P2

P3

P8 P10

P4 P6

P7

P11

AD/DAConverter

DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRC


fs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.

4 x

4000

MO

PS

Max

imum

Sear

ch

Sync1Sync2Sync1

Sync1Sync4Sync3

fs = 65MHz

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk


0.384MBPS 1.15MBPS

10M

OPSMatched

Filter 4

MatchedFilter 4

DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



DCH

f < 1KHz

fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.

4 x

4000

MO

PS

Max

imum

Sear

ch

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.

4 x

4000

MO

PS

Max

imum

Sear

ch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



(480*16)kbps

105M

OPS

2nd

Insertionof DTX

Indication

2nd

Insertionof DTX

Indication




DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.

4 x

4000

MO

PS

Max

imum

Sear

ch

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.

4 x

4000

MO

PS

Max

imum

Sear

ch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



10M

OPSMatched



DDS

SamplingRate

SamplingRate

FrequencyAdjust

RaySearch

RaySearch

2450MOPS492MOPS

120MOPS

130MOPS

1MOPS


46 MOPS

492MOPS 2450MOPS

160MOPS

4-FingerRAKE MRCMRC



DCH

f < 1KHz

fs = 61.44MHzfs = 61.44MHz

fs = 15.36MHz fs = 3.84MHz

Chip Sync.

4 x

4000

MO

PS

Max

imum

Sear

ch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3

Chip Sync.

4 x

4000

MO

PS

Max

imum

Sear

ch

Sync1Sync2Sync1

Sync1Sync4Sync3

Sync1Sync2Sync1

Sync1Sync4Sync3


2nd

Inter-leaving

2nd

Inter-leaving

1st

Insertionof DTX

IndicationCRC



tation10MOPS

RadioFrame

Segmen-tation

63MOPS

1st

Inter-leaving

116MOPS

RateMatch-

ing

141MOPS

TurboDe-

coding

342MOPS

TrBkConcat./CodeBk



(480*16)kbps

105M

OPS

2nd

Insertionof DTX

Indication

2nd

Insertionof DTX

Indication




MFI-QSR

CHIPSYNC

TC

INTER-PROCESSORSSYNCHRONISATION

DATA ROUTING

Latency

MAPPING

Modularity: Object-Oriented ProgrammingAn application is made of several objects running independently on one or more processors.

Each object interfaces with other objects through FIFO-likeinterfaces.

Interfaces carry packets of data. Data represent samples of signals. The meaning of samples is contextual: waveform samples, symbols, bits, characters, etc.

An object only uses P-HAL API to access the external resources (parameters, etc.) or to use the physical interfaces.

A physical interface is defined including information like bits per sample, samples per second, logic format of data, etc.


Message-Passing-Oriented Architecture

Basic object processing loop:

for ever {packet=read(MY_INPUT);result=process_data(packet);write(MY_OUTPUT,result);

}

Loop is executed once for every data packet that arrives to the object.


When more than one platform with P-HAL compliant mechanisms are put together, a larger virtual platform is created.This virtual platform offers the same facilities than a bigger platform with its own P-HAL.

Virtual Layer P-HAL

Platform 2 Platform 3 Platform 4Platform 1Hardware Layer

Platform Software

Layer P-HAL KernelSync

BridgeStats

P-HAL Kernel

SWMap

SyncBridgeStats

Physical Interfaces

P-HAL KernelSync

BridgeStats

P-HAL KernelSync

BridgeStats

SDR: Computing ManagementJoining Multiple Platforms (BRIDGE)

BRIDGE RoutingThe architecture of connections between platforms is not necessarily the “full connectivity” one.Routing mechanisms for P-HAL packets are necessary within BRIDGE. For instance, packet from object in 3 to object in 1 routed by BRIDGE in 2:

Linux Box

FOR

CE 5V

microSPA

RC

II

PENTEK

4291Q

uad-C6701

SHaR

ev1.0

Octal-XC

4013

A/D

/A

VME bus

IP link

4

1

2 3 5


BRIDGE Routing EstablishmentFrom a topology file P-HAL generates the graph of connections. The graph for the previous example would be:

1

32

4

5

Network

Bus

BusBus

Dedicated

Dedicated

Routing graphs (or tables) are distributed to all P-HAL platforms.


Temporal control (SYNC)For the large virtual platform, distribution of adequate time references is necessary. Each platform has its own time counter (or RTC) that must be aligned with other time counters.The references can be obtained only through communications interfaces. That is, precision in synchronism is based on communications reliability.Synchronism is performed regularly to overcome the differences in the respective local oscillators.Time adjustment is crucial for the correct behaviour of the application but a relatively slight misalignment is not critical because of the execution time framework.


Execution Control (SYNC) Time is divided into time slots to control the temporal evolution of applications. PIPELINED execution.Every application object gets CPU time within every time slot to process data packets. P-HAL schedules the execution of the object. The instant within the slot where the object goes to execution is immaterial.


Execution Control (SYNC) SDR: Computing Management

P PPP

P

Object 1 Object 2

Object 3

Object 4 Object 5

Processor 1 ObjectsProcessor 2 Objects

Processor 1

Data TO1 to O2

1 2 1 2P PP

3 5 4P 5 4 3 5 4P 53 5 4P 5 4

21P P

P-HALProcess Schedule

1 Slot

Data Transfer

1 Slot

Processor 2

1 Slot

Data TO2 to O4

Data Transfer Data Transfer Data Transfer

Data Transfer

N N+1 N+2

P PPP

P

Object 1 Object 2

Object 3

Object 4 Object 5


Processor 1

Data TO1 to O2

1 2 1 2P PP

3 5 4P 5 4 3 5 4P 53 5 4P 5 4

21P P


1 Slot

Data Transfer

1 Slot

Processor 2

1 Slot

Data TO2 to O4


Data Transfer

P PPP

P

Object 1 Object 2

Object 3

Object 4 Object 5


Processor 1

Data TO1 to O2

1 2 1 2P PP

3 5 4P 5 4 3 5 4P 53 5 4P 5 4

21P P


1 Slot

Data Transfer

1 Slot

Processor 2

1 Slot

Data TO2 to O4


Data Transfer

N N+1 N+2

Synchronism procedure (SYNC)

TG1Time Reading

TG3

Time Reading

Time Setting

TP1

TP2

TG2

TR

SLAVE SYNC MASTER SYNC

Local Reference

Remote Reference

Time Reading

TGR1

TGR2

TS1

TGR3

∆TA

∆TE

TG1Time Reading

TG3

Time Reading

Time Setting

TP1

TP2

TG2

TR

SLAVE SYNC MASTER SYNC

Local Reference

Remote Reference

Time Reading

TGR1

TGR2

TS1

TGR3

∆TA

∆TE

∆TE

SLOT n+1SLOT n

SLOT n+1SLOT n

Platform 2

MASTER SYNC

SALVE SYNC

Platform 1

∆TE

SLOT n+1SLOT n

SLOT n+1SLOT n

Platform 2


Object execution sequence

Initialisation. No real-time required

Read ConfigurationSet-up CommunicationsSet-up Statistics

Register to P-HAL

INIT

Close Resources

STOP

analyse message if anydispatch task if anyreturnUnregistered P-HAL

RUN

START

EXIT

Tx

Status

Status

Hard real-time

Exit. No real-time required


The API adaptation to FPGA

OBJECT

P-HALINTERFACE

SWITCH(ROUTING TABLE)

DATA LOGICAL INTERFACES: FIFO-LIKE

PHYSICAL INTERFACES

P-HAL RAMADAPTATION

LOGICAL RAM INTERFACE

SBSRAMSDRAMSRAM

MEMORY POOL

ENABLE/DISABLE/RESETSTATUS MONITOR

P-HALCONTROL

PORT

CONTROL WORD (4 – 8 bits)

BIDIRECTIONAL SERIAL PORT FOR REQUESTS (IN/OUT)PHYSICAL

INTERFACE

TIMEREGISTER

TIME STAMPON-BOARD TIME INTERFACE


The API adaptation to FPGABIG FPGA

COMON P-HAL

OBJECT 1

OBJECT 2

SMALL FPGA

SINGLE P-HAL

OBJECT 2

SMALL FPGA

SINGLE P-HAL

OBJECT 1

A single FPGA can be shared by multiple objects if development tools can separate configuration for them.

Single-threaded FPGAs can easily exchange the running object but introduce more overhead..


P-HAL Included MechanismsReal-time seamless exchange of information from one P-HAL compliant platform to another (BRIDGE).

Isochronisms of data and processes running on different platforms (SYNC).

Platform-wide coordinated process control, scheduling, logging and error control (KERNEL).

Start/Stop object execution on a given process (KERNEL).

Real-time system monitoring, data and statistics capture and adaptation of processes by means configuration parameters (STATS).


P-HAL General ViewApplication Defined as a set of object tasks running concurrently and having FIFO-like interfaces.

Objects do not interact each other. Only P-HAL interface is viewed.

P-HAL offers the same view to the application independently of number and type of underlying platforms.


PlatformSoftware

Layer

Virtual Layer

P-HAL KernelSync

BridgeStats

P-HAL Kernel

SWMap

SyncBridgeStats

Overall P-HAL

Task 1Task 2

Task 3Task 4

Task 5Task 6

Real Application

Layer

AbstractApplication

Layer

ObjectTask 1

ObjectTask 2

ObjectTask 3

Physical Interfaces

P-HAL KernelSync

BridgeStats

P-HAL KernelSync

BridgeStats

ObjectTask 4

ObjectTask 6

ObjectTask 5


PlatformSoftware

Layer

Virtual Layer

P-HAL KernelSync

BridgeStats

P-HAL KernelSync

BridgeStats

P-HAL Kernel

SWMap

SyncBridgeStats

P-HAL Kernel

SWMap

SyncBridgeStats

Overall P-HAL

Task 1Task 2

Task 3Task 4

Task 5Task 6

Real Application

Layer

AbstractApplication

Layer

ObjectTask 1

ObjectTask 2

ObjectTask 3

Physical Interfaces

P-HAL KernelSync

BridgeStats

P-HAL KernelSync

BridgeStats

P-HAL KernelSync

BridgeStats

P-HAL KernelSync

BridgeStats

ObjectTask 4

ObjectTask 6

ObjectTask 5


The P-HAL APIControl functions:

InitPHAL StatusClosePHAL Relinquish

Communications functions:CreateFlow WriteFlowReadFlow GetFlowStatus DeleteFlow

Initialisation functions:ReadInitFile GetParameter

Event register functions:CreateLog WriteLog, WriteMsg, WriteVarCloseLog

Statistics functions:InitStatistics CreateStat SetStatValueGetStatValue DeleteStat

Other functions:GetTimeStamp UnrecoveryError

STOPRUNINIT


Execution and Control Plane separation (virtual) Radio algorithms does not know its environment.Software Blocks use P-HAL API to access to any offered functionality. Introduce overhead!

Object 1

Object 2

Object 3

Object 4 Object 5

Monitoring and Control Plane P-HAL componentExecution Plane P-HAL component

Resource

AlgorithmKernel

Object 1

Object 2

Object 3

Object 4 Object 5

Monitoring and Control Plane P-HAL componentExecution Plane P-HAL component

Resource

AlgorithmKernel


P-HAL OverheadDSP devices (C6701 DSP): Two types of overhead

Cycles consumed in accessing P-HAL kernel services(100 cycles) less than 0.1%

Cycles required by P-HAL kernel to switch from one object to another (scheduling) (200 cycles)

less than 0.2%

Scenario: 4 object tasks in one DSP requesting a mean of six services per time slot only 3.2% of DSP cycles for P-HAL

FPGA Devices (1 million gates): Overhead 0.5%


Temporal Issues: Overhead & Latency

0 200 400 600 800 1000 1200 1400 1600 1800 20000

10

20

30

40

50

60

70

80

90

100

Ove

rhea

d (%

)

Time Slot Length (µs)

5 Objects

10 Objects

15 Objects

20 ObjectsLatency (m

s)100

90

80

70

60

50

40

30

20

10

0200 400 600 800 1000 1200 1400 1600 1800 20000

50

45

40

35

30

25

20

15

10

5

0

20 Objects

15 Objects

10 Objects

5 Objects

Example from measurements on Pentek 4291 DSP platform


• Middleware hiding processing platforms heterogeneity.

• Systematics in developing Radio Modules: Object Oriented Approach

• Real-Time Computing Assumptions

• Facilitates Dynamic Reconfiguration

• Computing Management in SDR environments

SDR: Computing ManagementSummary:

SUPELEC 07FINAL4 SENSE ANIMACIO - Supélec · Supelec, 19 April 2007. ... Demod Filtro Plataforma Hardware Communication Services ... Matched Filter 4 160MOPS 4-Finger RAKE Channel

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