Subject File

7/31/2019 Subject File

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MITTED TO SUBMITTE

vneet Singh SukhmindeRoll no-EC

ECE-Y3


2/46

STAL DIRECTIOS AD DEFECTS

allography

graphy is the science of the arrangement of atoms in solids. The word "crystallography" derives from theystallon = cold drop / frozen drop, with its meaning extending to all solids with some degree of transpaho = write.

llographic Planes & Directions.

sary to be able to define planes and directions within crystalline solids. A labelling system that uses combinatio

r "indices" to define crystallographic directions and planes is used.

m is known as the Miller System. It has some similarities with conventional vector systems especially for simplFor more complex crystal structures (such as found in geology and magnetic/electronic devices) then the Millervery useful indeed.

llographic Directions.

lographic direction is basically a vector between two points in the crystal. Any direction can be defin a simple procedure.

dices form a notation system in crystallography for planes and directions in crystal lattices.

ular, a family of lattice planes is determined by three integers h, k, and , the Miller indices. They are

d each index denotes a plane orthogonal to a direction (h, k, ) in the basis of the reciprocal lattice vecton, negative integers are written with a bar, as in 3 for 3. The integers are usually written in lowest ter

atest common divisor should be 1. Miller index 100 represents a plane orthogonal to direction h; inds a plane orthogonal to direction k, and index 001 represents a plane orthogonal to .

dices were introduced in 1839 by the British mineralogist William Hallowes Miller. The method wly known as the Millerian system, and the indices as Millerian,] although this is now rare.

on

ordinates insquare brackets such as [100] denote a direction vector (in real space).

ordinates in angle brackets or chevrons such as denote a family of directions which are relatmmetry operations. In the cubic crystal system for example, would mean [100], [010], [001]

ative of an of those directions.


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is the opposite direction to [111].

es of Equivalent Directions.

o the symmetry of crystal structures the spacing and arrangement of atoms may be the same in several diren as equivalent directions. A group of equivalent directions is known as a family of directions. Families

n in angular brackets. These families of directions will become important when we consider slip directionsuced in more detail later, but this is just to reassure that this information is relevant.

Families of Equivalent Directions

es of crystal directions


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al defects

ne solids exhibit a periodic crystal structure. The positions of atoms or molecules occur on repeating fixed determined by the unit cell parameters. However, the arrangement of atom or molecules in most crystalliis not perfect. The regular patterns are interrupted by crystallographic defects. These defects are

defects

ects are defects that occur only at or around a single lattice point. They are not extended in space in anyn. Strict limits for how small a point defect is, are generally not defined explicitly, but typically these defe

t most a few extra or missing atoms. Larger defects in an ordered structure are usually considered dislocatir historical reasons, many point defects, especially in ionic crystals, are called centers: for example a vaca

ic solids is called a luminescence center, a color center, or F-center. These dislocations permit ionic transprystals leading to electrochemical reactions. These are frequently specified using KrgerVink Notation.

cancy defects are lattice sites which would be occupied in a perfect crystal, but are vacant. If a neighborin

ves to occupy the vacant site, the vacancy moves in the opposite direction to the site which used to be occthe moving atom. The stability of the surrounding crystal structure guarantees that the neighboring atoms

simply collapse around the vacancy. In some materials, neighboring atoms actually move away from a vcause they experience attraction from atoms in the surroundings. A vacancy (or pair of vacancies in an ionid) is sometimes called a Schottky defect.

erstitial defects are atoms that occupy a site in the crystal structure at which there is usually not an atom. Tgenerally high energy configurations. Small atoms in some crystals can occupy interstices without high eh as hydrogen in palladium.


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nearby pair of a vacancy and an interstitial is often called a Frenkel defect or Frenkel pair. This is caused

ion moves into an interstitial site and creates a vacancy.

purities occur because materials are never 100% pure. In the case of an impurity, the atom is often incorpoa regular atomic site in the crystal structure. This is neither a vacant site nor is the atom on an interstitial si

s called asubstitutionaldefect. The atom is not supposed to be anywhere in the crystal, and is thus an impere are two different types of substitutional defects. Isovalent substitution and aliovalent substitution. Isov

bstitution is where the ion that is substituting the original ion is of the same oxidation state as the ion it islacing. Aliovalent substitution is where the ion that is substituting the original ion is of a different oxidati

te as the ion it is replacing. Aliovalent substitutions change the overall charge within the ionic compound,ionic compound must be neutral. Therefore a charge compensation mechanism is required. Hence either

metals is partially or fully oxidised or reduced, or ion vacancies are created.

tisite defects[5][6] occur in an ordered alloy or compound when atoms of different type exchange positions.

ample, some alloys have a regular structure in which every other atom is a different species; for illustratioume that type A atoms sit on the corners of a cubic lattice, and type B atoms sit in the center of the cubes.

be has an A atom at its center, the atom is on a site usually occupied by a B atom, and is thus an antisite deis is neither a vacancy nor an interstitial, nor an impurity.

pological defects are regions in a crystal where the normal chemical bonding environment is topologicallyferent from the surroundings. For instance, in a perfect sheet of graphite (graphene) all atoms are in rings

ntaining six atoms. If the sheet contains regions where the number of atoms in a ring is different from six,total number of atoms remains the same, a topological defect has formed. An example is the Stone Wales

fect in nanotubes, which consists of two adjacent 5-membered and two 7-membered atom rings.

so amorphous solids may contain defects. These are naturally somewhat hard to define, but sometimes the

ure can be quite easily understood. For instance, in ideally bonded amorphous silica all Si atoms have 4 b

O atoms and all O atoms have 2 bonds to Si atom. Thus e.g. an O atom with only one Si bond (a danglingn be considered a defect in silica.[7]

mplexes can form between different kinds of point defects. For example, if a vacancy encounters an impu

two may bind together if the impurity is too large for the lattice. Interstitials can form 'split interstitial' ormbbell' structures where two atoms effectively share an atomic site, resulting in neither atom actually occ

site.

efectscts can be described by gauge theories.

slocations are linear defects around which some of the atoms of the crystal lattice are misaligned.[8]

two basic types of dislocations, the edge dislocation and thescrew dislocation. "Mixed" dislocations,g aspects of both types, are also common.


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locations are caused by the termination of a plane of atoms in the middle of a crystal. In such a case, theplanes are not straight, but instead bend around the edge of the terminating plane so that the crystal structu

ordered on either side. The analogy with a stack of paper is apt: if a half a piece of paper is inserted in a ste defect in the stack is only noticeable at the edge of the half sheet.

w dislocation is more difficult to visualise, but basically comprises a structure in which a helical path is trae linear defect (dislocation line) by the atomic planes of atoms in the crystal lattice.

ence of dislocation results in lattice strain (distortion). The direction and magnitude of such distortion isd in terms of a Burgers vector (b). For an edge type, b is perpendicular to the dislocation line, whereas in t

he screw type it is parallel. In metallic materials, b is aligned with close-packed crytallographic directionstude is equivalent to one interatomic spacing.

ons can move if the atoms from one of the surrounding planes break their bonds and rebond with the atom

nating edge.

resence of dislocations and their ability to readily move (and interact) under the influence of stresses induoads that leads to the characteristic malleability of metallic materials.

ons can be observed using transmission electron microscopy, field ion microscopy and atom probe techniq

el transient spectroscopy has been used for studying the electrical activity of dislocations in semiconductorlicon.

sclinations are line defects corresponding to "adding" or "subtracting" an angle around a line. Basically, th

ans that if you track the crystal orientation around the line defect, you get a rotation. Usually they play a ry in liquid crystals.

defects

ain boundaries occur where the crystallographic direction of the lattice abruptly changes. This usually occen two crystals begin growing separately and then meet.

tiphase boundaries occur in ordered alloys: in this case, the crystallographic direction remains the same, b

h side of the boundary has an opposite phase: For example, if the ordering is usually ABABABAB, an

iphase boundary takes the form of ABABBABA.

cking faults[8] occur in a number of crystal structures, but the common example is in close-packed structur

ce-centered cubic (fcc) structures differ from hexagonal close packed (hcp) structures only in stacking ordh structures have close packed atomic planes with sixfold symmetrythe atoms form equilateral triangle

hen stacking one of these layers on top of another, the atoms are not directly on top of one anotherthe fir

ers are identical for hcp and fcc, and labelled AB. If the third layer is placed so that its atoms are directlyse of the first layer, the stacking will be ABAthis is the hcp structure, and it continues ABABABAB.

wever, there is another possible location for the third layer, such that its atoms are not above the first layertead, it is the atoms in the fourth layer that are directly above the first layer. This produces the stacking

BCABCABC, and is actually a cubic arrangement of the atoms. A stacking fault is a one or two layer interr


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efects

ids are small regions where there are no atoms, and can be thought of as clusters of vacancies.

purities can cluster together to form small regions of a different phase. These are often called precipitates.


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1

MICROELECTRONICS

ASSIGNMENT

No.:1

Submitted To:

Mr. DIVNEET SINHG KAPOOR

Submitted By:

Tanveer gill

EC/09/9421

Group Y-3


9/46

2

A perfect crystal, with every atom of the same type in the correct

position, does not exist. All crystals have some defects. Defects

contribute to the mechanical properties of metals. In fact, using

the term defect is sort of a misnomer since these features are

commonly intentionally used to manipulate the mechanical

properties of a material. Adding alloying elements to a metal is

one way of introducing a crystal defect. Nevertheless, the term

defect will be used, just keep in mind that crystalline defects are

not always bad. There are basic classes of crystal defects:

Point defects :

which are places where an atom is missing or irregularly placed in

the lattice structure. Point defects include lattice vacancies, self-interstitial atoms, substitution impurity atoms, and interstitial

impurity atoms

Linear defects:

which are groups of atoms in irregular positions. Linear defects

are commonly called dislocations.

Planar defects:

which are interfaces between homogeneous regions of the

material. Planar defects include grain boundaries, stacking faults

and external surfaces.


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3

Point Defects

Point defects are where an atom is missing or is in an irregular place in the lattice

structure. Point defects include self interstitial atoms, interstitial impurity atoms,

substitutional atoms and vacancies. A self interstitial atom is an extra atom that

has crowded its way into an interstitial void in the crystal structure. Self

interstitial atoms occur only in low concentrations in metals because they distort

and highly stress the tightly packed lattice structure.

A substitutional impurity atom is an atom of a different type than the bulk

atoms, which has replaced one of the bulk atoms in the lattice. Substitutional

impurity atoms are usually close in size (within approximately 15%) to the bulk

atom. An example of substitutional impurity atoms is the zinc atoms in brass. In

brass, zinc atoms with a radius of 0.133 nm have replaced some of the copper

atoms, which have a radius of 0.128 nm.


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4

Interstitial impurity atoms are much smaller than the atoms in the bulk matrix.

Interstitial impurity atoms fit into the open space between the bulk atoms of the

lattice structure. An example of interstitial impurity atoms is the carbon atomsthat are added to iron to make steel. Carbon atoms, with a radius of 0.071 nm, fit

nicely in the open spaces between the larger (0.124 nm) iron atoms.

Vacancies are empty spaces where an atom should be, but is missing. They are

common, especially at high temperatures when atoms are frequently and

randomly change their positions leaving behind empty lattice sites. In most cases

diffusion (mass transport by atomic motion) can only occur because of vacancies.

Linear Defects - Dislocations

Dislocations are another type of defect in crystals. Dislocations are areas were the

atoms are out of position in the crystal structure. Dislocations are generated and

move when a stress is applied. The motion of dislocations allows slip plastic

deformation to occur.

Before the discovery of the dislocation by Taylor, Orowan and Polyani in 1934,

no one could figure out how the plastic deformation properties of a metal could

be greatly changed by solely by forming (without changing the chemical

composition). This became even bigger mystery when in the early 1900s

scientists estimated that metals undergo plastic deformation at forces much

smaller than the theoretical strength of the forces that are holding the metalatoms together. Many metallurgists remained skeptical of the dislocation theory

until the development of the transmission electron microscope in the late 1950s.

The TEM allowed experimental evidence to be collected that showed that the

strength and ductility of metals are controlled by dislocations.


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5

There are two basic types of dislocations, the edge dislocation and the screw

dislocation. Actually, edge and screw dislocations are just extreme forms of the

possible dislocation structures that can occur. Most dislocations are probably ahybrid of the edge and screw forms but this discussion will be limited to these

two types.

Bulk Defects

Bulk defects occur on a much bigger scale than the rest of the crystal defects discussed

in this section. However, for the sake of completeness and since they do affect the

movement of dislocations, a few of the more common bulk defects will be mentioned.

Voids are regions where there are a large number of atoms missing from the lattice. The

image to the right is a void in a piece of metal The image was acquired using a Scanning

Electron Microscope (SEM). Voids can occur for a number of reasons. When voids occur

due to air bubbles becoming trapped when a material solidifies, it is commonly called

porosity. When a void occurs due to the shrinkage of a material as it solidifies, it is called

cavitation.


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6

Another type of bulk defect occurs when impurity atoms cluster together to form small

regions of a different phase. The term phase refers to that region of space occupied by

a physically homogeneous material. These regions are often called precipitates. Phasesand precipitates will be discussed in more detail latter.


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SUBMITTED TO SUBMITTED BY

Mr. DivneetSingh Sukhminder Kaur

Roll no-EC/09/9418

Group-Y3


15/46

EPITAXY

Epitaxy refers to the deposition of a crystalline overlayer on a crystalline

substrate, where the overlayer is in registry with the substrate. In other words,there must be one or more preferred orientations of the overlayer with respect to

the substrate for this to be termed epitaxial growth. The overlayer is called anepitaxial film or epitaxial layer. The term epitaxycomes from the Greek roots epi,

meaning "above", and taxis, meaning "in ordered manner". It can be translated

"to arrange upon". For most technological applications, it is desired that the

deposited material form a crystalline overlayer that has one well-defined

orientation with respect to the substrate crystal structure (single-domain epitaxy).

Epitaxial films may be grown from gaseous or liquid precursors. Because the

substrate acts as a seed crystal, the deposited film may lock into one or morecrystallographic orientations with respect to the substrate crystal. If the overlayer

either forms a random orientation with respect to the substrate or does not forman ordered overlayer, this is termed non-epitaxial growth. If an epitaxial film is

deposited on a substrate of the same composition, the process is called

homoepitaxy; otherwise it is called heteroepitaxy.

Homoepitaxy is a kind of epitaxy performed with only one material. In

homoepitaxy, a crystalline film is grown on a substrate or film of the same

material. This technology is used to grow a film which is more pure than the

substrate and to fabricate layers having different doping levels. In academic

literature, homoepitaxy is often abbreviated to "homoepi".

Heteroepitaxy is a kind of epitaxy performed with materials that are different

from each other. In heteroepitaxy, a crystalline film grows on a crystalline

substrate or film of a different material. This technology is often used to grow

crystalline films of materials for which crystals cannot otherwise be obtained and

to fabricate integrated crystalline layers of different materials. Examplesinclude gallium nitride (GaN) on sapphire, aluminum gallium indium

phosphide (AlGaInP) on gallium arsenide (GaAs) or diamond or iridium [1].

Heterotopotaxy is a process similar to heteroepitaxy except for the fact that thin

film growth is not limited to two dimensional growths. Here the substrate is similar

only in structure to the thin film material.

Epitaxy is used in silicon-based manufacturing processes for BJTs and

modern CMOS, but it is particularly important for compound

semiconductors such as gallium arsenide. Manufacturing issues include controlof the amount and uniformity of the deposition's resistivity and thickness, the

cleanliness and purity of the surface and the chamber atmosphere, the

prevention of the typically much more highly doped substrate wafer's diffusion of

dopant to the new layers, imperfections of the growth process, and protecting thesurfaces during the manufacture and handling.


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EPITAXIAL DEFECTS

Defects in epitaxial films on Si(100)The electronic and mechanical properties of silicon depend to a high extend onthe defects present in the material. Photoluminescence and DLTS spectroscopy,as well as defect etching serve to analyze the density of extended structuraldefects and the density and electronic levels of point defects in the filmsdeposited by MBE and IAD.

Extended structural defectsPreferential wet chemical etching, using the etch solution proposed by Seccod'Aragona serves to determine the type and density of structural defects in thefilms. Defects in low temperature epitaxial films on Si(100) underwent an in-situannealing step for oxygen removal. The ex-situ pretreatment consists of a cuttingstep on semiconductor disc saw and a subsequent RCA cleaning [133] of thesamples. During the cutting, the wafer surface is covered with an adhesive tape,that is easily removed after UV-light exposure. The density of dislocations andstacking faults is below 1 x 103 cm 2, when epitaxial films are deposited onwafers without ex-situ pretreatment (WACKER SILTRONIC). Note that the valuesfor the as delivered (100)-oriented films only represent an upper limit for thedefect density due to the detection limit of the analysis method. On some wafers,

the extended defect density is estimated to be below 1 x 102 cm 2. Filmsdeposited on substrates that underwent the ex-situ pretreatment show highdislocation densities above 1 x 104 cm 2. The dislocations most likely originatefrom particles on the wafer surface that are not completely removed by thecleaning step. It is noted, that old wafers, though stored in original packaging,have a high density of defects visible on the surface (before and after deposition)after Secco etching. This is a result of contamination from the plastic coverage,aging over the years and emitting particles.

Substrate defect density (cm 2)

pretreatment dislocations stacking faults

cutting + RCA > 1 x 104 < 1 x 102no pretreatment < 1 x 103 < 1 x 102

Density of structural defects in films deposited on substrates with and without ex-situpretreatment


17/46

Optically active defects

The density of extended defects in the films is low and therefore, film propertiesare mainly dominated by the presence of point defects, such as interstitials,vacancies, impurities, and their complexes. Photoluminescence as well asDLTS allow for the characterization of thin films in respect to point defects actingas recombination centers or traps for carriers. The density of optically active pointdefects is determined using photoluminescence while DLTS analyzes electricallyactive point defects. Photoluminescence spectra reveal information aboutradiative recombination of excess carriers only. Non-radiative recombination,such as Auger recombination or SRH recombination via multi-phonon orcascading processes is not directly accessible by luminescence methods.However, if non-radiative recombination occurs, the number of excess carriers

recombining radiatively is reduced and lower defect and band to bandluminescence is observed. Therefore, the total luminescence intensity is asignature of the non-radiative recombination, and in particular the band to bandluminescence is a measure of the carrier lifetime. Deep level transientspectroscopy, on the other hand, is sensitive to the capture process of traps inthe depletion layer of pn-junctions or Schottky contacts. The DLTS signal isproportional to the number of traps, and from several DLTS measurements atdifferent repetition rates the energetic level of a trap can be deduced. Theinformation obtained by the combination of these two methods combined givesan insight in the energetic distribution and recombination activity of point defectsin the films.

Deep level defectsDefect-bands

The DLTS-spectra of low temperature epitaxial films typically consist of relativelybroad overlapping peaks for a film deposited at Tdep = 460fiC and rdep= 0.16um=min. The film has a low boron doping concentration of NA = 5 x 1015cm 3.The maxima of the DLTS spectra correspond to majority-carrier traps forthe chosen representation, i.e. in this case of a p-type film the peaks A, B, and C

represent hole-traps. Minority-carrier traps would appear as minima in thespectra. Each peak corresponds to a distinct defect level. Several spectrarecorded at different emission frequencies ep are used to determine the energeticlevels of the defects in the films by plotting the emission frequency versus theinverse sample temperature at the peak maximum in an Arrheniusgraph .Analysis of the three peak maxima is made by fitting Gaussian profiles tothe DLTS spectra. The energetic levels of the defects obtained by this methodare Et EV = 214 meV 16 meV (A), 412 meV 53 meV (B), and 330 meV 6 meV(C). The given error of the measurement is the error of the linear fit.


18/46

Influence of deposition temperature, rate, and silicon ions

Deposition temperature similar to the results from photoluminescencemeasurements, defect levels were only found in films deposited at Tdep = 460 C,whereas for higher deposition temperatures Tdep fi 510C no peaks in the DLTS-spectra are observed. Hence, the defect concentration for films deposited athigher temperatures is below the detection limit of the DLTS-method, which isabout 1 x 1013 cm 3 for p-type films. It is found that the defect density decaysexponentially with the deposition temperature. Deposition rate figure shows theinfluence of the deposition rate on the deep level defects. Two strong peaks arefound for the film deposited at rdep = 0.12 um=min. These two peaks are stillpresent in the spectrum of the film deposited at rdep = 0.36 um=min, albeit to amuch lower extent. The peaks clearly visible for the higher deposition rate arebarely visible for films deposited at the lower deposition rate.


19/46

MICROELECTRONICS

ASSIGNMENT

No.:2

Submd To:

Mr. DIVNEET SINGH KAPOOR

Submd By:

Manish Maheshwari

EC/09/9365

Group Y-1


20/46

EPITAXY

Epitaxy refers to the deposition of a crystalline overlayer on a crystalline

substrate, where the overlayer is in registry with the substrate. In other words,there must be one or more preferred orientations of the overlayer with respect to

the substrate for this to be termed epitaxial growth. The overlayer is called anepitaxial film or epitaxial layer. The term epitaxycomes from the Greek roots epi,

meaning "above", and taxis, meaning "in ordered manner". It can be translated

"to arrange upon". For most technological applications, it is desired that the

deposited material form a crystalline overlayer that has one well-defined

orientation with respect to the substrate crystal structure (single-domain epitaxy).

Epitaxial films may be grown from gaseous or liquid precursors. Because the

substrate acts as a seed crystal, the deposited film may lock into one or morecrystallographic orientations with respect to the substrate crystal. If the overlayer

either forms a random orientation with respect to the substrate or does not forman ordered overlayer, this is termed non-epitaxial growth. If an epitaxial film is

deposited on a substrate of the same composition, the process is called

homoepitaxy; otherwise it is called heteroepitaxy.

Homoepitaxy is a kind of epitaxy performed with only one material. In

homoepitaxy, a crystalline film is grown on a substrate or film of the same

material. This technology is used to grow a film which is more pure than the

substrate and to fabricate layers having different doping levels. In academic

literature, homoepitaxy is often abbreviated to "homoepi".

Heteroepitaxy is a kind of epitaxy performed with materials that are different

from each other. In heteroepitaxy, a crystalline film grows on a crystalline

substrate or film of a different material. This technology is often used to grow

crystalline films of materials for which crystals cannot otherwise be obtained and

to fabricate integrated crystalline layers of different materials. Examplesinclude gallium nitride (GaN) on sapphire, aluminum gallium indium

phosphide (AlGaInP) on gallium arsenide (GaAs) or diamond or iridium [1].

Heterotopotaxy is a process similar to heteroepitaxy except for the fact that thin

film growth is not limited to two dimensional growths. Here the substrate is similar

only in structure to the thin film material.

Epitaxy is used in silicon-based manufacturing processes for BJTs and

modern CMOS, but it is particularly important for compound

semiconductors such as gallium arsenide. Manufacturing issues include controlof the amount and uniformity of the deposition's resistivity and thickness, the

cleanliness and purity of the surface and the chamber atmosphere, the

prevention of the typically much more highly doped substrate wafer's diffusion of

dopant to the new layers, imperfections of the growth process, and protecting thesurfaces during the manufacture and handling.


21/46

EPITAXIAL DEFECTS

Defects in epitaxial films on Si(100)The electronic and mechanical properties of silicon depend to a high extend onthe defects present in the material. Photoluminescence and DLTS spectroscopy,as well as defect etching serve to analyze the density of extended structuraldefects and the density and electronic levels of point defects in the filmsdeposited by MBE and IAD.

Extended structural defectsPreferential wet chemical etching, using the etch solution proposed by Seccod'Aragona serves to determine the type and density of structural defects in thefilms. Defects in low temperature epitaxial films on Si(100) underwent an in-situannealing step for oxygen removal. The ex-situ pretreatment consists of a cuttingstep on semiconductor disc saw and a subsequent RCA cleaning [133] of thesamples. During the cutting, the wafer surface is covered with an adhesive tape,that is easily removed after UV-light exposure. The density of dislocations andstacking faults is below 1 x 103 cm 2, when epitaxial films are deposited onwafers without ex-situ pretreatment (WACKER SILTRONIC). Note that the valuesfor the as delivered (100)-oriented films only represent an upper limit for thedefect density due to the detection limit of the analysis method. On some wafers,

the extended defect density is estimated to be below 1 x 102 cm 2. Filmsdeposited on substrates that underwent the ex-situ pretreatment show highdislocation densities above 1 x 104 cm 2. The dislocations most likely originatefrom particles on the wafer surface that are not completely removed by thecleaning step. It is noted, that old wafers, though stored in original packaging,have a high density of defects visible on the surface (before and after deposition)after Secco etching. This is a result of contamination from the plastic coverage,aging over the years and emitting particles.

Substrate defect density (cm 2)

pretreatment dislocations stacking faults

cutting + RCA > 1 x 104 < 1 x 102no pretreatment < 1 x 103 < 1 x 102

Density of structural defects in films deposited on substrates with and without ex-situpretreatment


22/46

Optically active defects

The density of extended defects in the films is low and therefore, film propertiesare mainly dominated by the presence of point defects, such as interstitials,vacancies, impurities, and their complexes. Photoluminescence as well asDLTS allow for the characterization of thin films in respect to point defects actingas recombination centers or traps for carriers. The density of optically active pointdefects is determined using photoluminescence while DLTS analyzes electricallyactive point defects. Photoluminescence spectra reveal information aboutradiative recombination of excess carriers only. Non-radiative recombination,such as Auger recombination or SRH recombination via multi-phonon orcascading processes is not directly accessible by luminescence methods.However, if non-radiative recombination occurs, the number of excess carriers

recombining radiatively is reduced and lower defect and band to bandluminescence is observed. Therefore, the total luminescence intensity is asignature of the non-radiative recombination, and in particular the band to bandluminescence is a measure of the carrier lifetime. Deep level transientspectroscopy, on the other hand, is sensitive to the capture process of traps inthe depletion layer of pn-junctions or Schottky contacts. The DLTS signal isproportional to the number of traps, and from several DLTS measurements atdifferent repetition rates the energetic level of a trap can be deduced. Theinformation obtained by the combination of these two methods combined givesan insight in the energetic distribution and recombination activity of point defectsin the films.

Deep level defectsDefect-bands

The DLTS-spectra of low temperature epitaxial films typically consist of relativelybroad overlapping peaks for a film deposited at Tdep = 460fiC and rdep= 0.16um=min. The film has a low boron doping concentration of NA = 5 x 1015cm 3.The maxima of the DLTS spectra correspond to majority-carrier traps forthe chosen representation, i.e. in this case of a p-type film the peaks A, B, and C

represent hole-traps. Minority-carrier traps would appear as minima in thespectra. Each peak corresponds to a distinct defect level. Several spectrarecorded at different emission frequencies ep are used to determine the energeticlevels of the defects in the films by plotting the emission frequency versus theinverse sample temperature at the peak maximum in an Arrheniusgraph .Analysis of the three peak maxima is made by fitting Gaussian profiles tothe DLTS spectra. The energetic levels of the defects obtained by this methodare Et EV = 214 meV 16 meV (A), 412 meV 53 meV (B), and 330 meV 6 meV(C). The given error of the measurement is the error of the linear fit.


23/46

MICROELECTRONICS

ASSIGNMENT 3

ONLIFT OFF TECHOLOGY

AD

FIE LIE LITHOGRAPHY

SUBMITTED TO: SUBMITTED BY:

Mr. Divneet Singh Sukhminder Kaur

Roll no: EC/09/9418

Group: Y3


24/46

"LIFT-OFF TECHOLOGY"

Lift-off process in micro structuring technology is a method of creating structures(patterning) of a target material on the surface of a substrate (ex. wafer) using a

sacrificial material (ex. Photoresist ). It is an additive technique as opposed to more

traditional subtracting technique like etching. The scale of the structures can vary

from the nanoscale up to the centimeter scale or further, but are typically of

a micrometric dimensions.

"Lift-off" is a simple, easy method for patterning films that are deposited. A

pattern is defined on a substrate using photoresist. A film, usually metallic, is

blanket-deposited all over the substrate, covering the photoresist and areas inwhich the photoresist has been cleared. During the actual lifting-off, the photoresist

under the film is removed with solvent, taking the film with it, and leaving only thefilm which was deposited directly on the substrate.

Depending on the type of lift-off process used, patterns can be defined withextremely high fidelity and for very fine geometries. Lift-off, for example, is theprocess of choice for patterning e-beam written metal lines. Because film sticks

only where photoresist is cleared, the defect modes are opposite what one might

expect for etching films (for example, particles lead to opens, scratches lead toshorts in metal lift-off.)

Any deposited film can be lifted-off, provided:

1. During film deposition, the substrate does not reach temperatures highenough to burn the photoresist.

2. The film quality is not absolutely critical. Photoresist will outgas veryslightly in vacuum systems, which may adversely affect the quality of thedeposited film.

3. Adhesion of the deposited film on the substrate is very good.4. The film can be easily wetted by the solvent.5. The film is thin enough and/or grainy enough to allow solvent to seep

underneath.

6. The film is not elastic and is thin and/or brittle enough to tear along adhesionlines.


25/46

There are three basic ways in which lift-off can be performed:

1. Standard photoresist processing;

2. LOL 2000 processing;

3. Surface-modified photoresist processing.

STADARD PHOTORESIST PROCESSIG:

This is the easiest method, because it involves only one mask step and thephotolithography is completely standard. The main disadvantage of this method isthat film is deposited on the sidewall of the photoresist and will generally continue

to adhere to the substrate following resist removal. This sidewall may peel off insubsequent processing, resulting in particulates and shorts, or it may flop over and

interfere with etches or depositions that follow.

Prior to film deposition, particularly for sputtering or evaporation processes, a

post-develop bake is recommended. This will drive off excess solvent so that therewill be less outgassing during the film deposition. However, bake should not toolong or at too high a temperature, otherwise resist will reflow slightly.

The film should be deposited as usual. Lift-off can be accomplished by immersingin acetone. The length of time for lift-off will depend on the film quality(generally, the higher the film quality, the more impermeable it is and the longer it

will take to lift-off.) Depending on how robust the film and substrate are, sidewalls

from deposited film can be removed using a gentle swipe of a clean-room swab or

a directed stream of acetone from a squeeze bottle. As a rule, keep the substrateimmersed in acetone until all the film has been lifted-off and there are no traces of

film particulates -- once particles dry on the substrate, they are notoriously difficultto remove.


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a.) Substrate with AZ3612 resist. b.) Following expose and develop. c.) Following film deposition. d.)Following lift-off. e.) Following mechanical "scrub".


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"FIE LIE PHOTOLITHOGRAPHY"

It is known that focused-ion-beam lithography has the capability of writingextremely fine lines (less than 50 nm line and space has been achieved) withoutproximity effect. However, because the writing field in ion-beam lithography is

quite small, large area patterns must be created by stitching together the smallfields. The precision with which this can be done is much poorer than the

resolution, typical stitching errors are -100 nm. A spatial-phase-locking method

has been proposed to reduce stitching errors and provide both pattern placement

accuracy and precision. The fundamental flaw in conventional particle-beam

(electron and ion) lithography, which gives rise to most of the stitching error, isthat the beam location is not directly monitored. The stage position is monitored

via laser interferometer, but the beam location is not. Thus, the beam can drift fromits assumed position due to thermal expansion, charging, or any other error

sources. The spatial-phase-locking enables direct monitoring of beam location andclosed loop beam positioning.

Ion beam lithography is the practice of scanning a focused beam of ions in a

patterned fashion across a surface in order to create very small structures suchas integrated circuits or other nanostructures.

Ion beam lithography has been found to be useful for transferring high-fidelitypatterns on three-dimensional surfaces.

Ion beam lithography offers higher resolution patterning than UV, X-ray, or

electron beam lithography because these heavier particles have more momentum.

This gives the ion beam a smaller wavelength than even an e-beam and thereforealmost no diffraction. The momentum also reduces scattering in the target and in

any residual gas. There is also a reduced potential radiation effect to sensitive

underlying structures compared to x-ray and e-beam lithography.

Ion beam lithography, or ion projection lithography, is similar to Electron beam

lithography, but uses much heavier charged particles, ions. In addition todiffraction being negligible, ions move in straighter paths than electrons do boththrough vacuum and through matter, so there seems be a potential for very high

resolution. Secondary particles (electrons and atoms) have very short range,

because of the lower speed of the ions. On the other hand, intense sources are more

difficult to make and higher acceleration voltages are needed for a given range.Due to the higher energy loss rate, higher particle energy for a given range and theabsence of significant space charge effects, shot noise will tend to be greater.


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Fast moving ions interact differently with matter than electrons do, and, due to

their higher momentum, their optical properties are different. They have much

shorter range in matter and move straighter through it. At low energies, at the endof the range, they lose more of their energy to the atomic nuclei, rather than to the

atoms, so that atoms are dislocated rather than ionized. If the ions don't defuse out

of the resist, they dope it. The energy loss in matter follows a Bragg curve and hasa smaller statistical spread. They are "stiffer" optically, they require larger fields or

distances to focus or bend. The higher momentum resists space charge effects.

Collider particle accelerators have shown that it is possible to focus and steer high

momentum charged particles with very great precision. FIB lithography has high

potential to play an important role in nanometer technology because of the lack of

backscattered electrons. This may be especially important in fields in which backscattering electrons are a severe problem such as in patterning high-Z x-ray masks.

Unlike electron beam technology, FIB technology (and FIB lithography inparticular) is relatively new and there is still a need to accumulate basic knowledgethrough comprehensive and energetic research works. In this section, basic of FIB

technology will be reviewed.

Liquid Metal Ion SourcesThe development of liquid metal ion sources (LMIS) has brought practical

application of focused ion beam (FIB) technology to the semiconductor industry


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The high brightness of the LMIS has made it possible to focus ion beams with a

current density of the order of 1 A cm-2 down to sub-micron diameters.

An LMIS usually consists of a needle emitter with an end radius of 1 - 10 gtm,which is coated with a metal having a high surface tension and a low vapor

pressure at its melting point. The emitter is heated to the melting point of the metal

while a high positive voltage is placed on it relative to an extraction electrode. Theliquid metal is drawn into a conical shape by the balance between the electrostatic

and surface tension forces. The apex of the liquid cone is drawn to an end radius so

small that the high electric field causes ions to begin to form through fieldevaporation. The cone apex is believed to have a radius of about 5 nm .The most

commonly used source metal is Ga. Au/Si and Au/Si/Be alloys have also been usedfor lithography because these sources can supply lighter mass ions.


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ASSIGNMENTASSIGNMENTASSIGNMENTASSIGNMENT 3

ON

LIFT OF TECHNOLOGY

AND

FINE LINE LITHOGRAPHY

SUBMITTED TO:SUBMITTED TO:SUBMITTED TO:SUBMITTED TO: SUBMITTED BY:SUBMITTED BY:SUBMITTED BY:SUBMITTED BY:

Mr. Divneet Singh Kapoor SATNAM KAURRoll no:EC/L-09/9446

Group: Y3


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"LIFT-OFF TECHOLOGY"

Lift-off process is a method of creating structures (patterning) of a target

material on the surface ofa substrate (ex. wafer) using a sacrificial material

(ex. Photoresist ). It is an additive technique as opposed to more traditional

subtracting technique like etching. The scale of the structures can vary from

the nanoscale up to the centimeter scale or further, but are typically of

a micrometric dimensions.

"Lift-off" is a simple, easy method for patterning films that are deposited. Apattern is defined on a substrate using photoresist. A film, usually metallic,is blanket-deposited all over the substrate, covering the photoresist and areas

in which the photoresist has been cleared. During the actual lifting-off, thephotoresist under the film is removed with solvent, taking the film with it,and leaving only the film which was deposited directly on the substrate.

Depending on the type oflift-off process used, patterns can be defined withextremely high fidelity and forvery fine geometries. Lift-off, for example, is

the process of choice for patterning e-beam written metal lines. Because film

sticks only where photoresist is cleared, the defect modes are opposite whatone might expect for etching films (for example, particles lead to opens,scratches lead to shorts in metal lift-off.)

Any deposited film can be lifted-off, provided:

During film deposition, the substrate does not reach temperatures highenough to burn the photoresist.

The film quality is not absolutely critical. Photoresist will outgas veryslightly in vacuum systems, which may adversely affect the quality ofthe deposited film.

Adhesion of the deposited film on the substrate is very good.

The film can be easily wetted by the solvent.

The film is thin enough and/orgrainy enough to allow solvent to seepunderneath.

The film is not elastic and is thin and/orbrittle enough to tear alongadhesion lines.


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There are three basic ways in which lift-off can be performed:

. Standard photoresist processing;

. LOL 000 processing;

. Surface-modified photoresist processing.

STADARD PHOTORESIST PROCESSIG:

This is the easiest method, because it involves only one mask step and the

photolithography is completely standard. The main disadvantage of this

method is that film is deposited on the sidewall of the photoresist and will

generally continue to adhere to the substrate following resist removal. Thissidewall may peel off in subsequent processing, resulting in particulates and

shorts, or it may flop over and interfere with etches or depositions thatfollow.

Prior to film deposition, particularly for sputtering or evaporation processes,

a post-develop bake is recommended. This will drive off excess solvent sothat there will be less outgassing during the film deposition. However, bake

should not too long orat too high a temperature, otherwise resist will reflow

slightly.

The film should be deposited as usual. Lift-off can be accomplished byimmersing in acetone. The length of time forlift-offwill depend on the filmquality (generally, the higher the film quality, the more impermeable it is

and the longerit will take to lift-off.) Depending on how robust the film and

substrate are, sidewalls from deposited film can be removed using a gentleswipe ofa clean-room swab ora directed stream ofacetone from a squeeze

bottle. As a rule, keep the substrate immersed in acetone until all the film

has been lifted-off and there are no traces of film particulates -- onceparticles dry on the substrate, they are notoriously difficult to remove.


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a.) Substrate with AZ resist. b.) Following expose and develop. c.) Following filmdeposition. d.) Following lift-off. e.) Following mechanical "scrub".

Modification of Standard Photoresist Processing

Photoresist (PR): .um (AZ)

Over expose to get a negative slope profile (exposure time longerthans)

PR descum

Evaporate metal

Remove PR by


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ASSIGNMENT NO. 4

OF

EXTRINSIC DIFFUSION

SUBMITTED TO - SUBMITTED BY

Mr.DAVNEET SINGH ROHIT KUMAR

KAPOOR EC/09-L/9445

Y(1)


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EXTRINSIC DIFFUSION

One of the main applications for polysilicon layers is to serve as outdiffusion source. Polysilicon

layers are deposited on top of the substrate and excessively high doped. During the subsequent

furnace (FA) or RTA annealing step dopants diffuse from the polysilicon into the underlyingsubstrate. The amount of outdiffused dopants depends on the applied thermal budget and the

structure of the interface. The dopant transport during this anneal in the polysilicon as well asacross the interface is a very complex mechanism being still an area of interest for many

researchers

It is known from experiments, that polysilicon shows extraordinary high diffusivity for dopants.This fact allows the dopants to diffuse even long distances within the polysilicon material inreasonable short time periods.

Dopant transport within polysilicon involves four major mechanism:

fast diffusion in grain boundaries

segregation between grain interior and grain boundaries

grain boundary motion

grain interior diffusion

To gain insight into the dopant/grain boundary system and the according diffusion mechanisms,we take a closer look onto the crystal structure of a grain bulk/grain boundary network.

Figure 3.2-4 gives the subtle tetrahedral bonding network for two polysilicon grains separated by

a grain boundary. It can be seen that the number of bonds crossing from one grain into the

neighboring grain is reduced at the interface, so that the fracture of the crystal along the interface

causes a corresponding low density of dangling bonds. Therefore, we suggest that this boundaryarea may be a preferred low energy local minimum for dopants. This outstanding energetic

properties in combination with the irregularity of the tetrahedral bonding at the interface makes

the grain boundary to a fast diffusion path for dopants.


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Figure 3.2-4: Three-dimensional perspective drawing of a grain/grain boundary network. The

atoms labeledgb and i refer to substitutional sites of dopants at the grain boundary and the graininterior, respectively. Dopants show high possibility to segregate into the grain boundaries where

they find fast diffusion pathes .

These energetically favorable grain boundaries also affect the adjacent grain interior regions. It is

possible for dopants to segregate into the grain boundary, if they are close enough and if there is

enough space in the grain boundary, which can be already occupied by other dopant atoms. Thesegregation of dopants into the grain boundary can be described by trapping and emission

mechanisms. The capture and emission rates depend on the number of occupied and free states in

the grain boundary, where the total number of states is limited by the grain boundary area.

The third transport mechanism is related to the grain growth phenomenon. Due to grain growth,

the grain boundaries are moving and so do the dopants incorporated in the grain boundaries. This

movement results in a net dopant transport.

As the crystal structure of the polysilicon grain bulk region shows a regular silicon lattice, the

diffusion of dopants within the grain interior regions is treated like normal diffusion in silicon

(see Section 3.1.4). Additionally, effects like dopant activation and clustering play an importantrole in the grain bulk and have to be considered for a complete description of the polysilicon

diffusion problem.

For practical outdiffusion applications the interface between the polysilicon and the underlying

substrate material plays a major role. Unfortunately, it is not possible with reasonable effort to

fabricate native-oxide-free poly-/monosilicon interfaces. The thickness and the chemical

properties of this native oxide layer influence the dopant profile during outdiffusionsignificantly. By applying moderate diffusion temperatures, as given by a furnace annealing

process (FA), the interface oxide remains stable and the dopant is able to overcome this diffusion


37/46

barrier because of the small extension of this oxide layer ( ). A classical dopant

segregation approach is used to account for the dopant flux across the interface (see

Section 4.4.2). Nevertheless, SIMS measurements reveal a typical pile-up in the dopantconcentration on either side of the boundary [Kod92] [Sch85] , which cannot be explained by

segregation kinetics. The interface exhibits some typical charging capabilities for the dopants. To

model the interface consistently, we assume the interface to be an extraordinary large grain

boundary with fewer free states compared to bulk grain boundaries, because most of the freesites are already occupied by oxide molecules. This phenomenon leads to an additional

trapping/emission relation for the interface concentrations (see Section 4.4.3).

By increasing the diffusion temperature and the doping concentrations the native oxide film

breaks up and the interface changes its properties. The typical dopant pile-up vanishes due to

dopant transport into the substrate [Kan94] . This rupture is not occurring immediately. There is

a delay time observed from experiments, which is needed to induce the rupture of the interface

native oxide film [Spi93] [Wil92] . The delay time depends on the local dopant concentration.

Table (3.2-2) shows a summary of delay times available from literature for different doping andtemperature conditions.

Table 3.2-2: Polysilicon interface break-up delay time for different doping conditions andtemperatures taken from literature. There is a significant impact of the doping conditions onto

the delay time.

At temperature above for doped samples and for undoped samples, epitaxial

realignmentcan occur. The break-up of the the native oxide is necessary for the onset ofepitaxial alignment, otherwise the temperature must be above for recrystallization of a

polysilicon layer, which is not an applicable temperature range for microelectronic processing.


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MICROELECTRONICS

ASSIGNMENT 5

On

IC PACKAGING

Submitted To:-

Mr. Divneet Singh Kapoor


39/46

Integrated circuit packaging

Integrated circuit packaging is the final stage of semiconductor device fabrication per se,

followed by IC testing. The die, which represents the core of the device, is encased in a

support that prevents physical damage and corrosion and supports the electrical contactsrequired to assemble the integrated circuit into a system.

In the integrated circuit industry it is called simply packaging and sometimes semiconductor

device assembly, or simply assembly. Also, sometimes it is called encapsulation or seal, by

the name of its last step, which might lead to confusion, because the term packaging

generally comprises the steps or the technology of mounting and interconnecting of

devices.

Approaches

The earliest integrated circuits were packaged in ceramic flat packs, which continued to be

used by the military for their reliability and small size for many years. Commercial circuit

packaging quickly moved to the dual in-line package (DIP), first in ceramic and later in

plastic. In the 1980s pin counts of VLSI circuits exceeded the practical limit for DIP

packaging, leading to pin grid array (PGA) and leadless chip carrier (LCC) packages. Surface

mount packaging appeared in the early 1980s and became popular in the late 1980s, using

finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by small-

outline integrated circuit a carrier which occupies an area about 30 50% less than an

equivalent DIP, with a typical thickness that is 70% less. This package has "gull wing" leads

protruding from the two long sides and a lead spacing of 0.050 inches.

Small-outline integrated circuit (SOIC) and Plastic leaded chip carrier (PLCC) packages. In the

late 1990s, plastic quad flat pack(PQFP) and thin small-outline packages (TSOP) became the

most common for high pin count devices, though PGA packages are still often used for high-

end microprocessors. Intel and AMD transitioned in the 2000s from PGA packages on high-

end microprocessors to land grid array (LGA) packages.

Ball grid array (BGA) packages have existed since the 1970s. Flip-chip ball grid array

packages developed in the 1990s allow for much higher pin count than other package types.

In an FCBGA package the die is mounted upside-down (flipped) and connects to the package

balls via a package substrate that is similar to a printed-circuit board rather than by wires.

FCBGA packages allow an array of input-output signals (called Area-I/O) to be distributed

over the entire die rather than being confined to the die periphery.

Traces out of the die, through the package, and into the printed circuit board have very

different electrical properties, compared to on-chip signals. They require special design

techniques and need much more electric power than signals confined to the chip itself.


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When multiple dies are stacked in one package, it is called SiP, for System In Package, or

three-dimensional integrated circuit. When multiple dies are combined on a small substrate,

often ceramic, it's called an MCM, or Multi-Chip Module. The boundary between a big MCM

and a small printed circuit board is sometimes fuzzy.

Operations

The following operations are performed at the stage of packaging.

Die attachment is the step during which a die is mounted and fixed to the package or

support structure (header)[1]

. For high-powered applications, the die is usually eutectic

bonded onto the package, using e.g. gold-tin or gold-silicon solder (for good heat

conduction). For low-cost, low-powered applications, the die is often glued directly onto a

substrate (such as a printed wiring board) using an epoxy adhesive.

IC Bonding

o Wire bonding

o Thermosonic Bonding

Down bonding

Tape-automated bonding

o

Flip chip

o Quilt packaging

o Tab bonding

o Film attaching

o Spacer attaching

IC encapsulation

o Baking

o Plating

o Lasermarking

o Trim and form

Wafer bonding


41/46

Overview of IC packages


42/46


43/46


44/46

1. Define Integrated Circuits. Write their advantages as well as disadvantages.

2. Categorize the integrated circuits on the basis of application, fabrication and scale

of integration.

3. Write down the steps of IC fabrication.

ITITUTE OF EGIEERIG & TECHOLOGY-BHADDALELECTROICS & COMMUICATIO EGIEERIG

Tutorial Sheet No. 1

Topic Introduction Group Date of Conduct of Tutorial

Session Dec-April 2012 Y1, Y2, Y3Batch 2009

Subject Microelectronics

Semester 6th

Subject code DE - 1.2

Name of Faculty Mr. Divneet Singh Kapoor


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1. Briefly describe the steps for formation of the starting material for Si wafer

production.

2. How can we obtain a single crystal ingot from polycrystalline substance? Briefly

describe the methods that are used.

3. How the dopants distribute themselves during the solidification in the crystal

growth process?

4. Briefly discuss the steps of Si wafer preparation after getting the single crystal

ingot.


Tutorial Sheet No. 2Topic Crystal Growth Group Date of Conduct of Tutorial



Semester 6th




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1. What is Epitaxy and how many types of epitaxies do we have?

2. How can epitaxy be done? Discuss the technique of LPE.

3. Discuss in detail the process of VPE.

4. Discuss the process of MBE.


Tutorial Sheet No. 3Topic Epitaxy Group Date of Conduct of Tutorial



Semester 6th



Subject File

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