STUDENT OBSERVATION MANUALvemu.org/uploads/lecture_notes/23_01_2020_1549251665.pdf · PART B: Embedded Systems (List of Experiments) (For Laboratory Examination-Minimum of Six Experiments)

VLSI & EMBEDDED SYSTEM LAB

IV/IV B. TECH., I SEMESTER

STUDENT OBSERVATION MANUAL

DEPARTMENT

OF

ELECTRONICS & COMMUNICATION ENGINEERING

VEMU INSTITUTE OF TECHNOLOGY Tirupati - Chittoor Highway Road, P. Kothakota, Chittoor- 517 112.

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

VEMU INSTITUTE OF TECHNOLOGY

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING

Vision of the institute

To be a premier institute for professional education producing dynamic and vibrant force of

technocrat with competent skills, innovative ideas and leadership qualities to serve the society

with ethical and benevolent approach.

Mission of the institute

Mission_1: To create a learning environment with state-of-the art infrastructure, well equipped

laboratories, research facilities and qualified senior faculty to impart high quality technical

education.

Mission_2: To facilitate the learners to foster innovative ideas, inculcate competent research and

consultancy skills through Industry-Institute Interaction.

Mission_3: To develop hard work, honesty, leadership qualities and sense of direction in rural

youth by providing value based education.

Vision of the Department

To become a centre of excellence in the field of Electronics and Communication Engineering

and produce graduates with Technical Skills, Research & Consultancy Competencies, Life-long

Learning and Professional Ethics to meet the challenges of the Industry and Society.

Mission of the Department

Mission_1: To enrich Technical Skills of students through Effective Teaching and Learning

practices for exchange of ideas and dissemination of knowledge.

Mission_2: To enable the students with research and consultancy skill sets through state-of-the

art laboratories, industry interaction and training on core & multidisciplinary technologies.

Mission_3: To develop and instill creative thinking, Life-long learning, leadership qualities,

Professional Ethics and social responsibilities among students by providing value based

education.

Programme Educational Objectives ( PEOs)

PEO_1: To prepare the graduates to be able to plan, analyze and provide innovative ideas to

investigate complex engineering problems of industry in the field of Electronics and

Communication Engineering using contemporary design and simulation tools.

PEO_2: To provide students with solid fundamentals in core and multidisciplinary domain for

successful implementation of engineering products and also to pursue higher studies.

PEO_3: To inculcate learners with professional and ethical attitude, effective communication

skills, teamwork skills, and an ability to relate engineering issues to broader social context at

work place.

Programme Outcome (POs)

PO_1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering

problems.

PO_2: Problem analysis: Identify, formulate, review research literature, and analyze complex

engineering problems reaching substantiated conclusions using first principles of mathematics,

natural sciences, and engineering sciences.

PO_3: Design/development of solutions: Design solutions for complex engineering problems

and design system components or processes that meet the specified needs with appropriate

consideration for the public health and safety, and the cultural, societal, and environmental

considerations.

PO_4: Conduct investigations of complex problems: Use research-based knowledge and

research methods including design of experiments, analysis and interpretation of data, and

synthesis of the information to provide valid conclusions.

PO_5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and

modern engineering and IT tools including prediction and modeling to complex engineering

activities with an understanding of the limitations.

PO_6: The engineer and society: Apply reasoning informed by the contextual knowledge to

assess societal, health, safety, legal and cultural issues and the consequent responsibilities

relevant to the professional engineering practice.

PO_7: Environment and sustainability: Understand the impact of the professional engineering

solutions in societal and environmental contexts, and demonstrate the knowledge of, and need

for sustainable development.

PO_8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities

and norms of the engineering practice.

PO_9: Individual and team work: Function effectively as an individual, and as a member or

leader in diverse teams, and in multidisciplinary settings.

PO_10: Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write

effective reports and design documentation, make effective presentations, and give and receive

clear instructions.

PO_11: Project management and finance: Demonstrate knowledge and understanding of the

engineering and management principles and apply these to one’s own work, as a member and

leader in a team, to manage projects and in multidisciplinary environments.

PO_12: Life-long learning: Recognize the need for, and have the preparation and ability to

engage in independent and life-long learning in the broadest context of technological change.

Programme Specific Outcome (PSOs)

PSO_1: Higher Education: Qualify in competitive examinations for pursuing higher education

by applying the fundamental concepts of Electronics and Communication Engineering domains

such as Analog & Digital Electronics, Signal Processing, Communication & Networking,

Embedded Systems, VLSI Design and Control Systems etc..

PSO_2: Employment: Get employed in allied industries through their proficiency in program

specific domain knowledge, specialized software packages and Computer programming or

become an entrepreneur.

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

IV B.Tech. I-Sem (ECE)

(13A04709) VLSI & EMBEDDED SYSTEMS LABORATORY

Course Outcomes (COs):

C417.1 Design and simulate combinational and sequential logic circuits using VHDL.

C417.2 Design and Implement combinational and sequential logic circuits in FPGA.

C417.3 Analysis of simulation results and schematic diagram of combinational and sequential logic circuits

C417.4 Develop programs for configuration of GPIO ports using TM4C 123GH6PM microcontroller

C417.5 Design and develop programs for interface modules with TM4C 123GH6PM microcontroller

PART A: VLSI (List of Experiments)

(For Laboratory Examination-Minimum of Six Experiments)

1. Realization of Logic Gates.

2. 3- to - 8Decoder- 74138.

3. 8 x 1 Multiplexer-74151 and 2 x 4 De-multiplexer-74155.

4. 4-Bit Comparator-7485.

5. D Flip-Flop-7474.

6. Decade counter-7490.

7. Shift registers-7495.

8. ALU Design.

PART B: Embedded Systems (List of Experiments)

(For Laboratory Examination-Minimum of Six Experiments)

9. Learn and understand how to configure EK-TM4C123GXL Launch pad digital I/O pins.

Write a C program for configuration of GPIO ports for Input and output operation

(blinking LEDs, push buttons interface).

10. Learn and understand Timer based interrupt programming. Write a C program for EK-

TM4C123GXL Launch pad and associated Timer ISR to toggle onboard LED using

interrupt programming technique.

11. Configure hibernation module of the TM4C123GH6PM microcontroller to place the

device in low power state and then to wake up the device on RTC (Real- Time Clock)

interrupt.

12. Configure in-build ADC of TM4C123GH6PM microcontroller and interface

potentiometer with EK-TM4C123GXL Launch pad to observe corresponding 12- bit

digital value.

13. Learn and understand the generation of Pulse Width Module (PWM) signal by

configuring and programming the in-build PWM module of TM4C123GH6PM

microcontroller.

14. Configure the PWM and ADC modules of TM4C123GH6PM microcontroller to control

the speed of a DC motor with a PWM signal based on the potentiometer output.

15. Learn and understand to connect EK-TM4C123GXL Launch pad to PC terminal and

send an echo of the data input back to the PC using UART.

16. Learn and understand interfacing of accelerometer in Sensor Hub Booster pack with EK-

TM4C123GXL Launch pad using I2C.

17. USB bulk transfer mode: Learn and understand to transfer data using bulk transfer mode

with the USB2.0 peripheral of the TM4C123GH6PM device.

18. Learn and understand to find the angle and hypotenuse of a right angle triangle using IQ

math library of Tiva Ware.

19. Learn and understand interfacing of CC3100 WiFi module with EKTM4C123GXL

Launch pad and configuration of static IP address for CC3100 booster pack.

20. Configure CC3100 Booster Pack connected to EK-TM4C123GXL Launch pad as a

Wireless Local Area Network (WLAN) Station to send Email over SMTP.

21. Configure CC3100 Booster Pack connected to EK-TM4C123GXL Launch pad as a

HTTP server.

VEMU INSTITUTE OF TECHNOLOGY

P.KOTHAKOTA, NEAR PAKALA, CHITTOOR, AP

Department of Electronics &Communication Engineering

PART A: VLSI (List of Experiments)


2. 3- to - 8Decoder- 74138.


4. 4-Bit Comparator-7485.

5. D Flip-Flop-7474.

6. ALU Design.

PART B: Embedded Systems (List of Experiments)

7. Blinking led’s and push button interface using TM4CGH6PM.

8. Timer based interrupt programming using TM4C123GXL

9. Hibernation module for TM4C123GH6PM microcontroller

10. In-Build ADC of TM4C123GH6PM & Potentiometer with TM4C123GXL

11. PWM and ADC Modules of TM4C123GH6PM Microcontroller

12. Sensor Hub booster pack with TM4C123GXL

PART C: Advanced Experiments

13. Implementation of JK- Flipflop using VHDL

14. Echo of the data input back to the PC using UART

CONTENTS

S. NO. NAME OF THE EXPERIMENT PAGE NO

PART A: VLSI


2. 3- to - 8Decoder- 74138


4. 4-Bit Comparator-7485

5. D Flip-Flop-7474

6. ALU Design

PART B: Embedded Systems

7. Blinking led’s and push button interface using TM4CGH6PM

8. Timer based interrupt programming using TM4C123GXL

9. Hibernation module for TM4C123GH6PM microcontroller

10. In-Build ADC of TM4C123GH6PM & potentiometer with

TM4C123GXL

11. PWM and ADC Modules of TM4C123GH6PM Microcontroller


PART-C : Advanced Experiments


14. Echo of the data input back to the PC using UART

DOS & DONTS IN LABORATORY

1. While entering the Laboratory, the students should follow the dress code

Wear shoes, White Apron & Female students should tie their hair back).

2. The students should bring their observation note book, practical manual,

record note book, calculator, necessary stationary items and graph sheets if

any for the lab classes without which the students will not be allowed for

doing the practical.

3. All the equipments and components should be handled with utmost care.

Any breakage/damage will be charged.

4. If any damage/breakage is noticed, it should be reported to the instructor

immediately.

5. If a student notices any short circuits, improper wiring and unusual smells

immediately the same thing is to be brought to the notice of technician/lab in

charge.

6. At the end of practical class the apparatus should be returned to the lab

technician and take back the indent slip.

7. Each experiment after completion should be written in the observation note

book and should be corrected by the lab in charge on the same day of the

practical class.

8. Each experiment should be written in the record note book only after getting

signature from the lab in charge in the observation note book.

9. Record should be submitted in the successive lab session after completion of

the experiment.

10. 100% attendance should be maintained for the practical classes.

SCHEME OF EVALUVATION

S No Date Name Of The Experiment

Marks Awarded

Sign. Observa

tion

(10M)

Viva

voce

(10M)

Total

(20M)

PART-A: VLSI


2. 3- to - 8Decoder- 74138

3. 8 x 1 Multiplexer-74151 and 2 x 4 De-

multiplexer-74155.

4. 4-Bit Comparator-7485

5. D Flip-Flop-7474

6. ALU Design

PART B: Embedded Systems

7. Blinking led’s and push button interface using

TM4CGH6PM

8. Timer based interrupt programming using

TM4C123GXL

9. Hibernation module for TM4C123GH6PM

microcontroller

10. In-Build ADC of TM4C123GH6PM &

potentiometer with TM4C123GXL

11. PWM and ADC Modules of

TM4C123GH6PM Microcontroller


PART C: Advanced Experiments


14. Echo of the data input back to the PC using

UART

Signature of Lab In-charge

VLSI & ES LAB IV B.Tech I SEMESTER

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 1

PART A (VLSI LAB)



CIRCUIT DIAGRAM & TRUTH TABLES

AND GATE TRUTH TABLE

OR GATE

NOT GATE

NAND GATE

NOR GATE

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

A Y

0 1

1 0

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

A B Y

0 0 1

0 1 0

1 0 0

1 1 0



AIM:

To write a VHDL/Verilog code for All Logic Gates and to generate

synthesis report, RTL schematic and to implement designs using FPGA (Spartan-2).

APPARATUS:

1. Synthesis Tool: Xilinx Project Navigator - ISE 9.1i.

2. Simulation Tool: Modelsim Simulator.

PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.

3. Create the file in VHDL/Verilog module.

4. Select the appropriate input and output ports according to the requirements.

5. Type the program and save it and synthesize the process.

6. Select Synthesize XST, check for syntax errors and generate report and RTL

schematic.

7. Create another new source.

8. Select source type as Test bench wave form.

9. Associate the test bench to the source.

10. Assign clock and timing details.

11. Give the input waveforms for the source.

12. Save the input waveforms and perform behavioral simulation.

13. The simulated output waveforms window will be shown.

DUMPING PROCESS:

1. In the process window, go to ‘user constraints’ and select ‘assign package pins’

and after that double click on ‘implement design’.

2. Select properties by right clicking on ‘generate programming file’. Select

‘JTAG’ clock in startup options.

3. Select boundary scan in ‘impact window’ after double clicking on ‘configure

Device’.

4. In ‘generate programming file’ double clicking on ‘programming file

generation report. Bit file will be generated.

5. Xilinx boundary scan window will appear when the bit file is selected. Right

click on Xilinx component and select program.

6. Programming properties will appear and finally program will be succeeded.

7. Thus the program can be dumped into FPGA kit and finally output can be seen

on the kit.

EXP NO.

REALIZATION OF ALL LOGIC GATES

DATE

1



SIMULATED MODEL OUTPUT WAVEFORMS

AND gate

OR gate

NOT GATE



VHDL CODE:

AND GATE :

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Andgate is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

y : out STD_LOGIC);

end Andgate ;

architecture Behavioral of Andgate is

begin

y <= a and b;

end Behavioral;

OR GATE :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity orgate is


b : in STD_LOGIC;

y : out STD_LOGIC);

end orgate ;

architecture Behavioral of orgate is

begin

y <= a or b;

end Behavioral;

NAND gate



NOR gate

BLOCK DIAGRAM:

NOT GATE :

library IEEE;






entity notgate is


y : out STD_LOGIC);

end notgate ;

architecture Behavioral of notgate is

begin

y <= not a;

end Behavioral;

NAND GATE :

library IEEE;




entity nandgate is


b : in STD_LOGIC;

y : out STD_LOGIC);

end nandgate ;

architecture Behavioral of nandgate is

begin

y <= a nand b;

end Behavioral;

NOR GATE : library IEEE;




entity norgate is


b : in STD_LOGIC;

y : out STD_LOGIC);

end norgate ;

TECHNOLOGY SCHEMATIC:



RTL SCHEMATIC:

architecture Behavioral of norgate is

begin

y <= a nor b;

end Behavioral;



DESIGN SUMMARY:

Number of Slices : 3 out of 960 0%

Number of 4 input LUTs : 5 out of 1920 0%

Number of IOs : 7

Number of bonded IOBs : 7 out of 66 10%

SYNTHESIS REPORT:

RTL Top Level Output File Name : allgates.ngr

Top Level Output File Name : allgates

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : NO

Design Statistics

# IOs : 7

Cell Usage :

# BELS : 5

# INV : 1

# LUT2 : 4

# IO Buffers : 7

# IBUF : 2

# OBUF : 5

RESULT:

Thus, the VHDL/Verilog code for all logic gates was simulated and

its synthesis report, RTL schematic and Technology schematic was generated and

implemented successfully using FPGA (Spartan-3).

CONCLUSION:

It is concluded that we observed how the basic logic operator works and then write

down the truth table of each of the logic gates. Then compared the result of truth table and the

original function of the gate. After the experiment, it is concluded that NOR Gate which also

works as inventor give output opposite to its input. It is also concluded that the total path

delay is obtained as 5.934ns.

VIVA QUESTIONS:

1. Design all basic gates using 2:1 multiplexer?

2. Write the dataflow code for the logic gates

3. What are logic gates why the called so?

4. Which gates are called as universal gates? What are its advantages?

5. What are the applications of logic gates?



PIN DIAGRAM:

CIRCUIT DIAGRAM:

IC74X138

G1

G2A

G2B

A

B

C

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

G1

G2A_L

G2B_L

A

B

C

Y0_L

Y1_L

Y2_L

Y3_L

Y4_L

Y5_L

Y6_L

Y7_L

G1

G2A_L

G2B_L

A

B

C

Y0_L

Y1_L

Y2_L

Y3_L

Y4_L

Y5_L

Y6_L

Y7_L



AIM:

To write a VHDL/Verilog code for 3x8 Decoder and to generate synthesis

report, RTL schematic and to implement designs using FPGA (Spartan-2).

APPARATUS:



PROCEDURE:







schematic.








DUMPING PROCESS:

1. In the process window, go to ‘user constraints’ and select ‘assign package

pins’ and after that double click on ‘implement design’.




device’.






7. Thus the program can be dumped into FPGA kit and finally output can be

seen on the kit.

TRUTH TABLE:

Selected enable inputs inputs outputs

G1 G2A_L G2B_L A(2) A(1) A(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)

0

X

X

X

1

X

X

X

1

X

X

X

X

X

X

X

X

X

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

EXP NO.

IC 74X138-3x8 DECODER

DATE

2



1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

0

1

1

1

1

1

1

0

1

1

1

1

1

1

0

1

1

1

1

1

1

0

1

1

1

1

1

1

0

1

1

1

1

1

1

0

1

1

1

1

1

1

0

1

1

1

1

1

1

0

1

1

1

1

1

1

1

SIMULATION MODEL OUTPUT WAVEFORM

BLOCK DIAGRAM:

VHDL CODE:

VHDL CODE FOR 3 t0 8 DECODER-BEHAVIORAL MODEL IC-74138

library IEEE;




entity dec3to8_beh is

port ( g1 : in STD_LOGIC;

g2a_l : in STD_LOGIC;



g2b_l : in STD_LOGIC;

a : in STD_LOGIC_VECTOR(2 downto 0);

y_l : out STD_LOGIC_VECTOR(7 downto 0));

end dec3to8_beh;

architecture Behavioral of dec3to8_beh is

begin

process (g1,g2a_l,g2b_l,a)

begin

if (g1='0' and g2a_l='0' and g2b_l='0')then

y_l<= "11111111";

elsif(g1 ='1' and g2a_l='0' and g2b_l='0') then

if(a="000")then

y_l<="11111110";

elsif(a="001") then

y_l<="11111101";

elsif(a="010")then

y_l<="11111011";

elsif(a="011")then

y_l<="11110111";

elsif(a="100")then

y_l<="11101111";

elsif(a="101")then

y_l<="11011111";

elsif(a="110")then

y_l<="10111111";

elsif(a="111") then

y_l<="01111111";

end if;

end if;

end process;

end Behavioral;




RTL SCHEMATIC:

DEVICE UTILIZATION SUMMARY:

Number of Slices: 8 out of 960 0%

Number of 4 input LUTs: 14 out of 1920 0%

Number of IOs: 14



Number of bonded IOBs: 14 out of 66 21%

IOB Flip Flops: 8

SYNTHESIS REPORT:

RTL Top Level Output File Name : decoder.ngr

Top Level Output File Name : decoder

Output Format : NGC


Keep Hierarchy : NO

Design Statistics

# IOs : 14

Cell Usage:

# BELS : 14

# LUT2 : 4

# LUT3 : 2

# LUT4 : 8

# FlipFlops/Latches : 8

# LD : 8

# IO Buffers : 14

# IBUF : 6

# OBUF : 8

RESULT:

Thus, the VHDL/Verilog code for 3x8 decoder was simulated and its

synthesis report, RTL schematic and Technology schematic was generated and


CONCLUSION:

It is concluded that 3x8 decoder is simulated and synthesized by using Xilinx ISE Tool. RTL

view and Schematic diagram of 3x8 decoder and their internal modules makes the internal

structures and connections easily understandable. Device Utilization Summary reveals the

amount of memory used by each module. It is also concluded that minimum input and

maximum output required time is 4.203ns and 4.114ns.

VIVA QUESTIONS:

1. Write the behavioral code for the IC 74x138.

2. Write the VHDL code for the IC 74x138 using CASE statement.

3. What does priority encoder mean?

4. How many outputs will a decimal-to-BCD encoder have?

5. Can an encoder be a transducer?



PIN DIAGRAM:

LOGIC DIAGRAM OF 8X1 MUX:



AIM:

To write a VHDL/Verilog code for 8X1 Multiplexer and to generate synthesis

report, RTL schematic and to implement designs using FPGA (Spartan-2).

APPARATUS:



PROCEDURE:







schematic.








DUMPING PROCESS:






Device’.







on the kit.

EXP NO.

IC74X151-8x1 MULTIPLEXER

DATE

3.A



TRUTH TABLE:

Inputs Outputs

EN_L S2 S1 S0 Y Y_L

1

0

0

0

0

0

0

0

0

X

0

0

0

0

1

1

1

1

X

0

0

1

1

0

0

1

1

X

0

1

0

1

0

1

0

1

0

d(0)

d(1)

d(2)

d(3)

d(4)

d(5)

d(6)

d(7)

1

OUTPUT WAVEFORM:

BLOCK DIAGRAM:

VHDL CODE:

library IEEE;






entity mux8_1 is

port ( en : in STD_LOGIC;

d : in STD_LOGIC_VECTOR(0 to 7);

s : in STD_LOGIC_VECTOR(0 to 2);

y,y_l : out STD_LOGIC);

end mux8_1;

architecture Behavioral of mux8_1 is

begin

process(en,d,s)

begin

if(en='1') then

y<='0';

y_l<='1';

else

case s is

when "000"=>y<=d(0);y_l<=not d(0);

when "001"=>y<=d(1); y_l<=not d(1);

when "010"=>y<=d(2); y_l<=not d(2);

when "011"=>y<=d(3); y_l<=not d(3);

when "100"=>y<=d(4); y_l<=not d(4);

when "101"=>y<=d(5); y_l<=not d(5);

when "110"=>y<=d(6); y_l<=not d(6);

when "111"=>y<=d(7); y_l<=not d(7);

when others=>null;

end case;

end if;

end process;

end Behavioral;




RTL SCHEMATIC:


Number of Slices: 3 out of 960 0%

Number of 4 input LUTs: 6 out of 1920 0%

Number of IOs: 14

Number of bonded IOBs: 14 out of 66 21%



SYNTHESIS REPORT:

RTL Top Level Output File Name : multiplexer.ngr

Top Level Output File Name : multiplexer

Output Format : NGC


Keep Hierarchy : NO

# IOs : 14

Cell Usage :

# BELS : 8

# LUT3 : 4

# LUT4 : 2

# MUXF5 : 2

# IO Buffers : 14

# IBUF : 12

# OBUF : 2

RESULT: Thus, the VHDL/Verilog code for 8x1multiplexer

was simulated and its synthesis report, RTL schematic and Technology schematic

was generated and implemented successfully using FPGA (Spartan-3).

CONCLUSION:

It is concluded that 8x1multiplexer is simulated and synthesized by using Xilinx

ISE Tool. RTL view and Schematic diagram of 8x1 multiplexer and their internal

modules makes the internal structures and connections easily understandable. Device

Utilization Summary reveals the amount of memory used by each module.

VIVA QUESTIONS:

1. Write the advantages of TDM.

2. What is meant by multiplexer?

3. What does demultiplexer mean?

4. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?

5. Compare decoder with demultiplexer?

PIN DIAGRAM:



LOGIC DIAGRAM OF 1X8 DEMUX:

AIM:

EXP NO.

IC74X155-1x4 DEMULTIPLEXER

DATE

3.B



To write a VHDL/Verilog code for 1X4 Demultiplexer and to generate


APPARATUS:



PROCEDURE:







schematic.








DUMPING PROCESS:






Device’.






7. Thus the program can be dumped into FPGA kit and finally output can be seen on

the kit.

TRUTH TABLE:



BLOCK DIAGRAM:

SIMULATED MODEL OUTPUT WAVEFORM:

VHDL CODE:



library IEEE;




entity demux is

port (

d : in STD_LOGIC;

s : in STD_LOGIC_VECTOR(0 to 1);

y0,y1,y2,y3 : out STD_LOGIC);

end demux;

architecture Behavioral of demux is

begin

process(d,s)

begin

case s is

when "00"=>y<=d;

when "01"=>y<=d;

when "10"=>y<=d;

when "11"=>y<=d;

when others=>null;

end case;

end process;

end Behavioral;




RTL SCHEMATIC:



Number of Slice Flip Flops : 4 out of 1920 0%


Number of IOs : 7




IOB Flip Flops : 4

SYNTHESIS REPORT:

RTL Top Level Output File Name : demux.ngr

Top Level Output File Name : demux

Output Format : NGC


Keep Hierarchy : NO

Design Statistics

# IOs : 7

Cell Usage :

# BELS : 4

# LUT2 : 4


# LD : 3

# LD_1 : 1

# IO Buffers : 7

# IBUF : 3

# OBUF : 4

RESULT:

Thus, the VHDL/Verilog code 1x4 Demultiplexer was simulated and its



CONCLUSION:

It is concluded that 1x4 Demultiplexer is simulated and synthesized by using

Xilinx ISE Tool. RTL view and Schematic diagram of 1x4 Demultiplexer and their

internal modules makes the internal structures and connections easily understandable.

Device Utilization Summary reveals the amount of memory used by each module. It is

also concluded that Minimum input and maximum output required time is 1.873ns and

4.113ns.

VIVA QUESTIONS:

1. Write the advantages of Multiplexer.

2. What is meant by Demultiplexer?

3. Write differences between multiplexer and Demultiplexer.

4. How many 1x4 Demultiplexers are needed to construct 1x8 Demultiplexer?

5. Demultiplexer is also called as?



PIN DIAGRAM OF IC74X85:

IC

7

4

X

8

5

ALTBIN

AEQBIN

AGTBIN

ALTBOUT

AEQBOUT

AGTBOUT

VCC

A0

B0

A1

B1 A2

B2

A3

B3

GND



LOGIC DIAGRAM:

AIM:

To write a VHDL/Verilog code for 4-bit Comparator and to generate


APPARATUS:



PROCEDURE:

EXP. NO.

74x85 – 4-BIT COMPARATOR

DATE

4









schematic.








DUMPING PROCESS:






Device’.







on the kit.




BLOCK DIAGRAM:

VHDL CODE:

library IEEE;




entity comparator is

port(A,B:in STD_LOGIC_VECTOR(3 downto 0);

ALTBIN, AEQBIN, AGTBIN: IN STD_LOGIC;

AGTBOUT, AEQBOUT, ALTBOUT:OUT STD_LOGIC);

end comparator;

Architecture comparator_b of comparator is

Begin

--ALTBIN<=’0’; AEQBIN<=’1’; AGTBIN<=’0’;

Process(A,



Begin

If(A>B)then

ALTBOUT<=’0’;

AEQBOUT<=’0’;

AGTBOUT<=’1’;

End if;

If(A<B) then

ALTBOUT<=’1’;

AEQBOUT<=’0’;

AGTBOUT<=’0’;

End if;

If(A=B) then

ALTBOUT<=’0’;

AEQBOUT<=’1’;

AGTBOUT<=’0’;

End if;

End process;

End comparator_b;




RTL SCHEMATIC:




Number of IOs 14


IOB Flip Flops : 3



SYNTHESIS REPORT:

RTL Top Level Output File Name : comparator.ngr

Top Level Output File Name : comparator

Output Format : NGC


Keep Hierarchy : NO

Design Statistics

# IOs : 14

Cell Usage :

# BELS : 13

# GND : 1

# LUT2 : 1

# LUT4 : 8

# MUXF5 : 2

# VCC : 1


# LDC : 1

# LDCP : 2

# IO Buffers : 11

# IBUF : 8

# OBUF : 3

RESULT:

Thus, the VHDL/Verilog code for 4-Bit Comparator was

simulated and its synthesis report, RTL schematic and Technology schematic was

generated and implemented successfully using FPGA (Spartan-3).

CONCLUSION:

It is concluded that 4-Bit Comparator is simulated and synthesized by using Xilinx

ISE Tool. RTL view and Schematic diagram of 4-Bit Comparator and their internal modules

makes the internal structures and connections easily understandable. Device Utilization



Summary reveals the amount of memory used by each module. It is also concluded that

Minimum input time path is not found and maximum output required time is 4.114ns.

VIVA QUESTIONS:

1. Write the dataflow model for the IC 74x85.

2. If two numbers are not equal then binary variable will be.

3. How many inputs are required for a digital comparator?

4. The purpose of a Digital Comparator is?

5. Design a 2-bit comparator using gates?

PIN DIAGRAM OF IC 74X74:



LOGIC DIAGRAM OF IC 74X74:

EXP NO.

IC7474—A POSITIVE EDGE TRIGGERING D

FLIP FLOP

DATE

PR-L

CLR-L

CLK

D

Q

QN

LOGIC DIARAM OF D FLIP FLOP



AIM:

To write a VHDL/Verilog code for a positive edge triggering D-Flip Flop and to

generate synthesis report, RTL schematic and to implement designs using FPGA

(Spartan-2).

APPARATUS:



PROCEDURE:







schematic.








DUMPING PROCESS:






Device’.






7. Thus the program can be dumped into FPGA kit and finally output can be seen on

the kit.

TRUTH TABLE:

5



0

1

1

1

0

QN

1

0

1

0

1

Q

x

x

x

0

1

x

1

0

0

1

1

1

0

1

0

1

1

1

x

x

x

1

1

QNQDCLR_LPR_LCLK

TRUTH TABLE :

BLOCK DIAGRAM:


VHDL CODE:

library IEEE;






entity dfff is

Port ( d: in STD_LOGIC_VECTOR(0 to 1);

clk : in STD_LOGIC_VECTOR;

pr : in STD_LOGIC_VECTOR(0 to 1);

clr : in STD_LOGIC_VECTOR(0 to 1);

q : inout STD_LOGIC_VECTOR(0 to 1);

nq :inout STD_LOGIC_VECTOR(0 to 1));

end DFFF;

architecture structural of DFFF is

component dff1

port(d1,clk1,pr1,clr1:in std_logic;

q1,nq1:inout std_logic);

end component;

begin

D1:dff1 port map(d(0),clk, pr(0),clr(0),q(0),nq(0));

D2:dff1 port map(d(1),clk, pr(1),clr(1),q(1),nq(1));

end structural;




RTLSCHEMATIC:

VHDL CODE FOR COMPONENT D FLIPFLOP:

entity dff1 is

Port ( d1: in STD_LOGIC;

Clk1 : in STD_LOGIC;

Pr1 : in STD_LOGIC;



Clr1 : in STD_LOGIC;

Q1 : inout STD_LOGIC;

Nq1 :inout STD_LOGIC);

end dff1;

architecture Behavioral of dff1 is

begin

process(d1,pr1,clr1,clk1)

begin

if(pr1='0' and clr1='0')then

q1<='1';nq1<='1';

elsif(pr1='0' and clr1='1')then

q1<='1';nq1<='0';

elsif(pr1='1' and clr1='0')then

q1<='0';nq1<='1';

else

if(clk1='1' and clk1'event)then

q1<=d1;nq1<=not d1;

else

q1<=q1;nq1<=nq1;

end if;

end if;

end process;

end Behavioral;





Number of IOs : 6


IOB Flip Flops : 2

Number of GCLKs : 1 out of 24 4%

SYNTHESIS REPORT:

RTL Top Level Output File Name : dff.ngr

Top Level Output File Name : dff

Output Format : NGC




Keep Hierarchy : NO

Design Statistics

# IOs : 6

Cell Usage :

# BELS : 5

# INV : 3

# LUT2 : 2


# FDCP : 2

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 5

# IBUF : 3

# OBUF : 2

RESULT:

Thus, the VHDL/Verilog code for D-Flip-flop was simulated and its



CONCLUSION:

It is concluded that D-Flip-flop is simulated and synthesized by using Xilinx

ISE Tool. RTL view and Schematic diagram of D-Flip-flop and their internal modules



Minimum input and maximum output required time is 2.723ns and 4.040ns.

VIVA QUESTIONS:

1. What are the applications of Flip flops?



2. The truth table for an S-R flip-flop has how many VALID entries?

3. When both inputs of a J-K flip-flop cycle, the output will?

4. How many types of sequential circuits are?

5. In D flip-flop, if clock input is LOW, the D input?



BLOCK DIAGRAM:



AIM:

To write a VHDL/Verilog code for ALU Design and to generate synthesis report,

RTL schematic and to implement designs using FPGA (Spartan-2).

APPARATUS:



PROCEDURE:







schematic.








DUMPING PROCESS:






Device’.







seen on the kit.

RTL SCHEMATIC:

EXP NO.

DESIGN AND IMPLEMENTATION OF ALU

DATE

6



TRUTH TABLE:

m=0 Logic

s(2) s(1) s(0) Function Operation (bit wise)

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

~a

~b

a&b

a|b

~(a&b)

~(a|b)

a^b

~(a^b)

NOT

NOT

AND

OR

NAND

NOR

EXOR

EXNOR

m=1 Arithmetic

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

a

a+1

a+b

a+b+1

a+(~b)

a-b

(~a)+b

b-a

Transfer a

Increment a by 1

Add a and b

Increment the sum of a and b by 1

a plus one’s complement of b

Subtract b from a (i.e. ~b+a+1)

b plus one’s compliment of a

Subtract a from b (i.e. ~a+b+1)



OUTPUT WAVEFORMS:

VHDL CODE: library IEEE;




entity alu4b is

Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);

s : in STD_LOGIC_VECTOR (2 downto 0);

m,clk : in STD_LOGIC;

y: out STD_LOGIC_VECTOR (3 downto 0));

end alu4b;

architectureBehavioral of alu4b is

begin

process(a,b,s,m)

begin

if(clk'event and clk='1')then

elsif(m='0')then

case s is

when"000"=>y<=not a;

when"001"=>y<=not b;

when"010"=>y<=a and b;



when"011"=>y<=a or b;

when"100"=>y<=a nand b;

when"101"=>y<=a nor b;

when"110"=>y<=a xor b;

when"111"=>y<=a xnor b;

when others=>null;

end case;

else

case s is

when"000"=>y<=a;

when"001"=>y<=a+1;

when"010"=>y<=a+b;

when"011"=>y<=a+b+1;

when"100"=>y<=a+(not b);

when"101"=>y<=a-b;

when"110"=>y<=(not a)+b;

when"111"=>y<=b-a;

when others=>y<=b;

end case;

end if;

end process;

end Behavioral;





Number of IOs : 6


Number of GCLKs : 1 out of 24 4%

SYNTHESIS REPORT:

RTL Top Level Output File Name : alu.ngr

Top Level Output File Name : alu

Output Format : NGC


Keep Hierarchy : NO

Design Statistics

# IOs : 6

Cell Usage :

# BELS : 4

# INV : 1

# LUT3 : 1

# LUT4 : 2


# FDC : 4

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 5

# IBUF : 1



# OBUF : 4

RESULT:

Thus, the VHDL/Verilog code for ALU Design was simulated and its



CONCLUSION:

It is concluded that ALU Design is simulated and synthesized by using Xilinx

ISE Tool. RTL view and Schematic diagram of ALU and their internal modules makes

the internal structures and connections easily understandable. Device Utilization



VIVA QUESTIONS:

1. What is the purpose of ALU?

2. What are the functional blocks of ALU?

3. In a 16-bit ALU, what does the number ‘16’ indicates?

4. Draw the schematic of Subtractor- using adder circuit.

5. What are the advantages of ALU Design?



PART-B

(EMBEDDED SYSTEMS LAB)



AIM:

To learn and understand how to configure of GPIO ports for input and output

operation (Blinking LED’s, Push Button Interface) using TM4C123GXL Launch Pad.

APPARATUS :

1. Software Required: Code Composer Studio (CCS)

2. Hardware Required: TIVA TM4C123GXL Launch Pad

PROCEDURE:

1. Connect the TM4C123GXL to the PC using the USB cable supplied.

2. Build, program and debug the code into the Launch Pad using CCS to view

the status of the green LED.

BLOCK DIAGRAM:

EXP NO.

BLINKING LED’S AND PUSH BUTTON INTERFACE

USING TM4CGH6PM

DATE

7



PROGRAM :

#include <stdint.h>

#include <stdbool.h>

#include "inc/hw_types.h"

#include "inc/hw_memmap.h"

#include "driverlib/sysctl.h"

#include "driverlib/pin_map.h"

#include "driverlib/debug.h"

#include "driverlib/gpio.h"

int main(void)

{

SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16M

HZ|

SYSCTL_OSC_MAIN);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);

GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE,

GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);

while(1){

GPIOPinWrite(GPIO_PORTF_BASE,GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3,

0x08);

SysCtlDelay(20000000);


0x00);


}

}



FLOW CHART:



RESULT:

CONCLUSION:

1.

2.

VIVA:

1. How do you use a push button switch?

2. How does a button work Arduino?

3. What is a debounce?

4. What is link debounce?

5. What is bounce elimination switch?



AIM:

To Learn and understand timer based interrupt programming for TM4C123GXL

Launch pad and associated timer ISR to toggle on board LED.

APPARATUS :



PROCEDURE:

1. Connect the EK-TM4C123GXL to the PC using the USB cable supplied.

2. Build, program and debug the code into the EK-TM4C123GXL using CCS to

View the status of the green LED.

BLOCK DIAGRAM:

FLOW DIAGRAM:

EXP NO.

TIMER BASED INTERRUPT PROGRAMMING USING

TM4C123GXL

DATE

8



PROGRAM :

#include <stdint.h>


#include "inc/tm4c123gh6pm.h"




#include "driverlib/interrupt.h"


#include "driverlib/timer.h"

int main(void)

{

uint32_t ui32Period;


HZ|

SYSCTL_OSC_MAIN);




SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);

TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);

ui32Period = (SysCtlClockGet() / 10) / 2;

TimerLoadSet(TIMER0_BASE, TIMER_A, ui32Period -1);

IntEnable(INT_TIMER0A);



TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);

IntMasterEnable();

}

TimerEnable(TIMER0_BASE, TIMER_A);

while(1) { }

void Timer0IntHandler(void)

{ // Clear the timer interrupt

TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);

// Read the current state of the GPIO pin and write back the opposite state

if(GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_2))

{ GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3,

0);

}

else

{ GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 4);

}

}

RESULT:

CONCLUSION:

1.

2.

VIVA:

1. . What is the clock source for the timers?

2. What is the frequency of the clock that is being used as the clock source for the

timer?

3. What steps are followed when we need to turn on any timer?

4. What is auto reload mode?

.



AIM:

To conf igure hibernat ion module of the TM4C123GH6PM

microcontroller and wake up the device on RTC Interrupt.

APPARATUS :


2. Hardware Required: TIVA TM4C123GH6PM Launch Pad

PROCEDURE:


2. Build, program and debug the code to view the status of the green LED.

3. After 4 seconds, the green LED will switch off, indicating that the

TM4C123GH6PM device has gone into hibernation.

4. Observe the status of the LED. After 5 seconds (RTC wake up time set in the

code), the LED turns ON, indicating the RTC has woken the processor.

5. Also you can press and hold the SW2 button located at the lower right corner of

the EKTM4C123GXL to wake up the processor at any time.

6. On wake up the green LED will turn ON again.

BLOCK DIAGRAM:

EXP NO.

HIBERNATION MODULE FOR TM4C123GH6PM

MICROCONTROLLER

DATE

9



FLOW CHART:

PROGRAM :

#include <stdint.h>


#include "utils/ustdlib.h"




#include "driverlib/pin_map.h"

#include "driverlib/debug.h"

#include "driverlib/hibernate.h"


int main(void)

{


HZ|

SYSCTL_OSC_MAIN);





0x08);

SysCtlPeripheralEnable(SYSCTL_PERIPH_HIBERNATE);

HibernateEnableExpClk(SysCtlClockGet());

HibernateGPIORetentionEnable();


HibernateRTCSet(0);



HibernateRTCEnable();

HibernateRTCMatchSet(0,5);

HibernateWakeSet(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC);

GPIOPinWrite(GPIO_PORTF_BASE,GPIO_PIN_3, 0x00);

HibernateRequest();

while(1){}

}

RESULT:

CONCLUSION:

1.

2.

VIVA:

1. What is TivaWare?

2.Difference between Mp and Mc?

3. What are registers in Microcontroller ?

4. What is an interrupt? List various types of interrupts available in 8051

Microcontroller?

5. Which interrupt has highest priority in Microcontroller ?



AIM:

To configure in build ADC of TM4C123GH6PM Microcontroller, interface

potentiometer with EK-TM4C123GXL and observe corresponding 12 bit digital value.

APPARATUS :



PROCEDURE:

1. Connect one lead of the potentiometer (Vcc) to +3.3V DC Supply Voltage (J1

connector Pin1).

2. Connect the other lead of the potentiometer to the GND pin (J3 connector, Pin 2).

3. Connect the center lead of the potentiometer to pin PE3 which is the Analog

Channel AN0 (J3 connector, Pin 9).

4. The Millimeter can be probed at the center lead of the potentiometer to observe the

analog voltage input.

5. This configuration varies the Analog Voltage from 0V to 3.3V depending on the

wiper position on PE3 which is the AN0 or Analog Input 0 of the TM4C123GH6PM.

6. The current configuration connects the VREFP of ADC to VDDA which is 3.3V

and VREFP to GND which is 0V.

BLOCK DIAGRAM:

EXP NO.

IN-BUILD ADC OF TM4C123GH6PM &

POTENTIOMETER WITH TM4C123GXL

DATE

10



PROGRAM :

#include<stdint.h>

#include<stdbool.h>

#include"inc/hw_memmap.h"

#include"driverlib/gpio.h"

#include"inc/hw_types.h"

#include"driverlib/debug.h"

#include"driverlib/sysctl.h"

#include"driverlib/adc.h"



// TO STORE THE VALUE IN VARIABLE ui32ADC0Value FOR EVERY

SAMPLING

uint32_tui32ADC0Value[1];

intmain(void)

{

SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_OSC_MAIN

SYSCTL_XTAL_16MHZ); // SYSTEM CLOCK AT 40MHZ

SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); // ENABLE ADC0 MODULE

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

MODULE // ENABLE GPIO for ADC0

GPIOPinTypeADC(GPIO_PORTE_BASE,GPIO_PIN_3);// ENABLE AN0 OF

ADC0

MODULE

// ADC0 MODULE, TRIGGER IS PROCESSOR EVENT, SEQUENCER 0 IS

CONFIGURED ADCSequenceConfigure(ADC0_BASE, 1,

ADC_TRIGGER_PROCESSOR,

0);

// ADC0 MODULE, SEQUENCER 0 , FOR 1 SAMPLING, INPUT IS FROM

CHANNEL 0

PE3 ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_CH0);

// ENABLE THE SEQUENCE 1 FOR ADC0

ADCSequenceEnable(ADC0_BASE, 1);

while(1) {

// CLEAR INTERRUPT FLAG FOR ADC0, SEQUENCER 1

ADCIntClear(ADC0_BASE, 1);

// TRIGGER IS GIVEN FOR ADC 0 MODULE, SEQUENCER 1

ADCProcessorTrigger(ADC0_BASE, 1);

// STORE THE CONVERTED VALUE FOR ALL DIFFERENT SAMPLING IN

ARRAY

//ui32ADC0Value

ADCSequenceDataGet(ADC0_BASE, 1, ui32ADC0Value); }

}

FLOW CHART:



RESULT:

CONCLUSION:

1.

2.



VIVA:

1. Why 8051 Is Called 8 Bit Microcontroller?

2. What Is The Width Of Data Bus?

3. List Out The Features Of 8051 Microcontroller?

4.what is ADC

5.what is potentiometer?



AIM:

To Configure the PWM and ADC Modules of TM4C123GH6PM

Microcontroller for control the speed of DC Motor with Potentiometer Output.

APPARATUS :



PROCEDURE:

1. Position DIP IC ULN2003A on a Breadboard.

2. Connect one terminal of the DC motor to the Common pin (IC Pin 9) of

ULN2003.

3. Connect the junction of the above 2 terminals to the VBUS (5V Power from USB)

(available at J3 Connector Pin 1).

4. Connect the other terminal of the DC motor to the Drive Pin (IC Pin 16) of ULN

2003.

5. Connect J3 Connector Pin 2 (GND) to the Ground Pin (IC Pin 8) of ULN2003.

6. Connect the PWM Output PD0 (J3 connector Pin 3) to Input Signal (IC Pin 1) of

ULN2003.

7. Connect one lead of the Potentiometer to the +3.3V Supply Voltage (J1 connector,

Pin 1).

8. Connect other lead of the Potentiometer to the GND Pin of ULN2003 (IC Pin 8).

9. Connect the center lead of the Potentiometer (variable analog output) to PE3 (J3

Connector

Pin 9) which is the AN0 or Analog Input 0 of the Tiva TM4C123GH6PM.

BLOCK DIAGRAM:

EXP NO.

PWM AND ADC MODULES OF TM4C123GH6PM

MICROCONTROLLER

DATE

11



PROGRAM :

#include<stdint.h>

#include<stdbool.h>



#include"driverlib/debug.h"


#include"driverlib/adc.h"



#include"driverlib/pwm.h"

#include"driverlib/pin_map.h"

#include"inc/hw_gpio.h"



#include"driverlib/rom.h"

uint32_tui32ADC0Value[1];

// TO STORE THE VALUE IN VARIABLE ui32ADC0Value FOR EVERY

SAMPLING

intmain(void)

{

SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_OSC_MAIN|

SYSCTL_XTAL_16MHZ); // SET SYSTEM CLOCK AT 40MHZ

SysCtlPWMClockSet(SYSCTL_PWMDIV_64); //SET PWM CLOCK AT SYSTEM

CLOCK

DIVIDED BY 64

SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1); //ENABLE PWM1 MODULE

SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); / /ENABLE ADC0 MODULE

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

MODULE //ENABLE GPIO FOR ADC0

GPIOPinTypeADC(GPIO_PORTE_BASE,GPIO_PIN_3); //CONFIGURE PE3 AS

AN0

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);

MODULE //ENABLE GPIO FOR PWM1

GPIOPinTypePWM(GPIO_PORTD_BASE, GPIO_PIN_0);

OUTPUT //CONFIGURE PD0 AS PWM

GPIOPinConfigure(GPIO_PD0_M1PWM0); //SET PD0 AS M1PWM0

PWMGenConfigure(PWM1_BASE, PWM_GEN_0, PWM_GEN_MODE_DOWN);

//SET PWM GENERATOR WITH MODEOF OPERATION AS COUNTING

PWMGenPeriodSet(PWM1_BASE, PWM_GEN_0,4095);

//SET THE PERIOD OF PWM GENERATOR

PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT, true); //ENABLE BIT0

OUTPUT

PWMGenEnable(PWM1_BASE, PWM_GEN_0); //ENABLE PWM GENERATOR

ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_PROCESSOR, 0);

// ADC0 MODULE, TRIGGER IS PROCESSOR EVENT, SEQUENCER 0 IS

CONFIGURED

ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_CH0);

// ADC0 MODULE, SEQUENCER 0 , FOR 1 SAMPLING, INPUT IS FROM

CHANNEL 0

PE3

ADCSequenceEnable(ADC0_BASE, 1);

// ENABLE THE SEQUENCE 1 FOR ADC0

while(1)

{

ADCIntClear(ADC0_BASE, 1); // CLEAR INTERRUPT FLAG FOR ADC0,

SEQUENCER1

ADCProcessorTrigger(ADC0_BASE, 1);

SEQUENCER1 // TRIGGER IS GIVEN FOR ADC0 MODULE,

// STORE THE CONVERTED VALUE FOR ALL DIFFERENT SAMPLING IN

ARRAY

ui32ADC0Value

ADCSequenceDataGet(ADC0_BASE, 1, ui32ADC0Value);

PWMPulseWidthSet(PWM1_BASE, PWM_OUT_0, ui32ADC0Value[0]);



// SET THE PULSE WIDTH

} }

FLOW CHART:



RESULT:

CONCLUSION:

1.

2.

VIVA:

1. What is PWM and its application?

2. What are the types of PWM techniques?

3. Is PWM AC or DC?

4.what is ADC



AIM:

To Learn and understand interfacing of accelerometer in Sensor Hub Booster

pack with TM4C123GXL Launch pad Using I2C.

APPARATUS :



PROCEDURE:

1. Install TivaWare.

2. Open CCS and create a new workspace.

3. Choose the Import Project link on the TI Resource Explorer page.

4. Import compdcm_mpu9150 project from TivaWare using the following steps:

a. Choose the Import Project link on the TI Resource Explorer page

b. Select the Browse button in the Import CCS Eclipse Projects dialog box

c. Select the compdcm_mpu9150 directory within C:\ti\TivaWare_C_Series-

2.1.0.12573\examples \boards\ek-tm4c123gxl-boostxl

SENSHUB\compdcm_mpu9150.

5. Open compdcm_mpu9150.c and comment the portion from the Line No. 659 to

690. The printing of all these values are commented and hence prevented to be sent

to the serial terminal.

6. Add the 3 lines of code given below after the commented portion. This is the code

to print the x, y and z values in the serial terminal. The code is now modified to print

only the 3 axis values as x, y and z.

BLOCK DIAGRAM:

EXP NO.

SENSORHUB BOOSTER PACK WITH TM4C123GXL

DATE

12



PROGRAM:

// Print the x,y,z measured in a table format.

UARTprintf("x=%3d.%03d\n", i32IPart[0], i32FPart[0]);

UARTprintf("y=%3d.%03d\n", i32IPart[1], i32FPart[1]);

UARTprintf("z=%3d.%03d\n", i32IPart[2], i32FPart[2]);

7. Save, Build, Debug the Project and Run.



FLOW CHART:



RESULT:

CONCLUSION:

1.

2.

VIVA:

1.what is sensorhub?

2. What is microprocessor give example?

3. What is the use of microcontroller?

4. What are types of microcontroller?



PART-C

(ADDITIONAL EXPERIMENTS)



AIM:

To write a VHDL/Verilog code for FPGA Implementation of UP and DOWN counter

APPARATUS:

• PC with Windows XP.

• XILINX 9.2i • FPGA-SPARTAN-3 KIT

• PARALLEL TO JTAG CABLE

PROCEDURE:







schematic.








DUMPING PROCESS:






Device’.







seen on the kit.

EXP NO.

FPGA Implementation of UP and DOWN counter

DATE

1



THEORY:

Counters are used in many different applications. Some count up from zero and

provide a change in state of output upon reaching a predetermined value; others

count down from a preset value to zero to provide an output state change.

However, some counters can operate in both up and down count mode, depending on

the state of an up/down count mode input pin. They can be reversed at any point

within their count sequence. Dual purpose ICs such as the TTL 74LS190 and

75LS191 are available which implement both Up and Down count functions.

The TTL 74LS190 is a 4-bit device that can be switched between Up and Down

modes, and provides a BCD decade output; the 74LS191 is a binary counter. The

counters are synchronous, but they are asynchronously presettable. Four data inputs

(A – D) allow the preset target to be loaded. The counter is decremented or

incremented synchronously with the low to high transition of the clock. The counters

can be cascaded in high-speed mode.

A simple three-bit Up/Down synchronous counter can be built using JK flip-flops

configured to operate as toggle or T-type flip-flops giving a maximum count of zero

(000), advancing through 001, 010 to seven (111) and back to zero again.

UP COUNTER:

PROGRAM:

module upcounterr(clk,clr,q); input clk, clr; output [3:0]q; reg [3:0]tmp; always@(posedge clk or posedge clr) begin

if (clr) tmp <= 4'b0000;

else

tmp <= tmp + 1'b1; end

assign q = tmp; endmodule



RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:



DOWN COUNTER:

PROGRAM:

module downcounterr(clk,clr,q); input clk, clr; output [3:0]q; reg [3:0]tmp; always@(posedge clk or posedge clr)

begin if (clr)

tmp <= 4'b1111; else tmp <= tmp - 1'b1; end assign q = tmp; endmodule



RTL SCHEMATIC:


RESULT:

OUTPUT WAVEFORM:



RESULT:

Thus, the VHDL/Verilog code for up counter and down counter was simulated and

its synthesis report, RTL schematic and Technology schematic was generated and


CONCLUSION:

It is concluded that up counter and down counter is simulated and

synthesized by using Xilinx ISE Tool. RTL view and Schematic diagram of up counter

and down counter and their internal modules makes the internal structures and

connections easily understandable. Device Utilization Summary reveals the amount of

memory used by each module. It is also concluded that Minimum input and maximum

output required time is 3.758ns and 4.137ns.

VIVA QUESTIONS:

1. What is up and down counter

2. What Is Fpga

3. How many different states does a 5 bit asynchronous counter have

4. What is the preset condition for a ring shift counter



AIM:

To implement finite state machine (mealy machine) using Verilog HDL

APPARATUS:




PROCEDURE:







schematic.








DUMPING PROCESS:






Device’.







seen on the kit.

EXP NO.

FPGA implementation of finite state machine(MEALY

MACHINE)

DATE

2



THEORY:

A finite-state machine (FSM) or simply a state machine is used to design both

computer programs and sequential logic circuits. It is conceived as an abstract

machine that can be in one of a finite number of user-defined states. The machine is

in only one state at a time; the state it is in at any given time is called the current

state. It can change from one state to another when initiated by a triggering event or

condition; this is called a transition. A particular FSM is defined by a list of its states,

and the triggering condition for each transition. The behavior of state machines can

be observed in many devices in modern society performing a predetermined

sequence of actions depending on a sequence of events with which they are

presented. Simple examples are vending machines which dispense products when the

proper combination of coins are deposited, elevators which drop riders off at upper

floors before going down, traffic lights which change sequence when cars are

waiting, and combination locks which require the input of combination numbers in

the proper order. The state machines are modeled using two basic types of sequential

networks- Mealy and Moore. In a Mealy machine, the output depends on both the

present (current) state and the present (current) inputs. In Moore machine, the output

depends only on the present state.

MEALY MACHINE: State diagram

PROGRAM:

module mealy( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state; reg outp;

always @( posedge clk, posedge rst ) begin

if( rst ) begin

state <= 2'b00;

outp <= 0; end



else begin

case( state ) 2'b00: begin

if( inp ) begin

state <= 2'b01;

outp <= 0; end

else begin

state <= 2'b10;

outp <= 0; end

end

2'b01: begin

if( inp ) begin

state <= 2'b00;

outp <= 1; end

else begin

state <= 2'b10;

outp <= 0; end

end

2'b10: begin

if( inp ) begin

state <= 2'b01; outp <= 0;

end

else begin

state <= 2'b00;

outp <= 1; end

end

default: begin

state <= 2'b00; outp <= 0;

end

endcase

end



RTL SCHEMATIC:


OUTPUT WAVEFORM:



RESULT: Thus, the VHDL/Verilog code for finite state machine (Mealy

machine) was simulated and its synthesis report, RTL schematic and Technology

schematic was generated and implemented successfully using FPGA (Spartan-3).

CONCLUSION:

It is concluded that finite state machine (Mealy machine) is simulated and

synthesized by using Xilinx ISE Tool. RTL view and Schematic diagram of finite state

machine (Mealy machine) and their internal modules makes the internal structures and

connections easily understandable. Device Utilization Summary reveals the amount of

memory used by each module. It is also concluded that Minimum input and maximum

output required time is 3.758ns and 4.137ns.

VIVA:

1. How does a mealy machine work?

2. What is mealy FSM?

3. How do you know if its Moore or mealy?

4. What is finite state machine in VLSI?



AIM:

To implement JK-Flipflop using VHDL

APPARATUS:




PROCEDURE:







schematic.








DUMPING PROCESS:






Device’.






EXP NO.

IMPLEMENTATION OF JK-FLIPFLOP USING

VHDL

DATE

1




seen on the kit.

THEORY:

This simple JK flip Flop is the most widely used of all the flip-flop designs and is

considered to be a universal flip-flop circuit. The two inputs labelled “J” and “K” are

not shortened abbreviated letters of other words, such as “S” for Set and “R” for

Reset, but are themselves autonomous letters chosen by its inventor Jack Kilby to

distinguish the flip-flop design from other types.

The sequential operation of the JK flip flop is exactly the same as for the previous

SR flip-flop with the same “Set” and “Reset” inputs. The difference this time is that

the “JK flip flop” has no invalid or forbidden input states of the SR Latch even

when S and R are both at logic “1”.

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input

circuitry that prevents the illegal or invalid output condition that can occur when both

inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK

flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and

“toggle”. The symbol for a JK flip flop is similar to that of an SR Bistable Latch as

seen in the previous tutorial except for the addition of a clock input.

JK-FLIPFLOP:

TRUTH TABLE:



VHDL CODE:

library ieee;

use ieee. std_logic_1164.all;

use ieee. std_logic_arith.all;

use ieee. std_logic_unsigned.all;

entity JK_FF is

PORT( J,K,CLOCK: in std_logic;

Q, QB: out std_logic);

end JK_FF;

Architecture behavioral of JK_FF is

begin

PROCESS(CLOCK)

variable TMP: std_logic;

begin

if(CLOCK='1' and CLOCK'EVENT) then

if(J='0' and K='0')then

TMP:=TMP;

elsif(J='1' and K='1')then

TMP:= not TMP;

elsif(J='0' and K='1')then

TMP:='0';

else

TMP:='1';



end if;

end if;

Q<=TMP;

Q <=not TMP;

end PROCESS;

end behavioral;

RTL SCHEMATIC:

OUTPUT WAVEFORM:



RESULT:

Thus, the VHDL/Verilog code for JK-Flipflop was simulated and its



CONCLUSION:

It is concluded that JK-Flipflop is simulated and synthesized by using Xilinx

ISE Tool. RTL view and Schematic diagram of JK-Flipflop and their internal modules




VIVA QUESTIONS:

1. What is the use of JK flip flop?

2. What is the significance of the J and K terminals on the JK flip flop?

3. What does the triangle on the clock input of a JK flip flop mean?

4. What is toggle State in JK flip flop?



AIM:

To connect TM4C123GXL Launch pad to the PC Terminal and send an echo of

the data input back to the PC Using UART.

APPARATUS :



PROCEDURE:


2. Build, program and debug the code.

3. Open Tera Term UART terminal window and configure which is explained.

4. Type characters on the keyboard and observe the terminal window.

THEORY:

The universal asynchronous receiver-transmitter (UART) takes bytes of data and

transmits the individual bits in a sequential fashion. At the destination, a second

UART re-assembles the bits into complete bytes. Each UART contains a shift

register, which is the fundamental method of conversion between serial and parallel

forms. Serial transmission of digital information (bits) through a single wire or other

medium is less costly than parallel transmission through multiple wires.

The UART usually does not directly generate or receive the external signals

used between different items of equipment. Separate interface devices are used to

convert the logic level signals of the UART to and from the external signalling

levels, which may be standardized voltage levels, current levels, or other signals.

Communication may be simplex (in one direction only, with no provision for

the receiving device to send information back to the transmitting device), full

duplex (both devices send and receive at the same time) or half duplex (devices take

turns transmitting and receiving).

EXP NO.

ECHO OF THE DATA INPUT BACK TO THE PC USING

UART

DATE



BLOCK DIAGRAM:



PROGRAM :

#include<stdint.h>

#include<stdbool.h>




#include"driverlib/pin_map.h"


#include"driverlib/uart.h"

#define GPIO_PA0_U0RX 0x00000001 // UART PIN ADDRESS FOR UART RX

#define GPIO_PA1_U0TX 0x00000401 // UART PIN ADDRESS FOR UART TX

{ // SYSTEM CLOCK AT 40 MHZ

SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_OSC_MAIN|

SYSCTL_XTAL_16MHZ); // ENABLE PERIPHERAL UART

0

SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); // ENABLE GPIO PORT

A,FOR

UART

GPIOPinConfigure(GPIO_PA0_U0RX); // PA0 IS CONFIGURED TO UART RX

GPIOPinConfigure(GPIO_PA1_U0TX); // PA1 IS CONFIGURED TO UART TX

GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);

// CONFIGURE UART, BAUD RATE 115200, DATA BITS 8, STOP BIT 1,

PARITY NONE

UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200,

(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |

UART_CONFIG_PAR_NONE));

UARTCharPut(UART0_BASE, 'E'); UARTCharPut(UART0_BASE, 'c');

UARTCharPut(UART0_BASE, 'h'); UARTCharPut(UART0_BASE, 'o');

// SEND "Echo Output: " IN UART

UARTCharPut(UART0_BASE, ' '); UARTCharPut(UART0_BASE, 'O');

UARTCharPut(UART0_BASE, 'u'); UARTCharPut(UART0_BASE, 't');

UARTCharPut(UART0_BASE, 'p'); UARTCharPut(UART0_BASE, 'u');

UARTCharPut(UART0_BASE, 't'); UARTCharPut(UART0_BASE, ': ');

UARTCharPut(UART0_BASE, ' '); UARTCharPut(UART0_BASE, '\n');

while (1)

{ //UART ECHO -

what is received is transmitted back //

if (UARTCharsAvail(UART0_BASE)) UARTCharPut(UART0_BASE,

UARTCharGet(UART0_BASE)); } }



FLOW CHART:



RESULT:

We have successfully configured the serial port to send and receive bytes and

monitor the data on a serial terminal. We have also learnt how the UART peripheral

can be used for serial interface.

CONCLUSION:

1. After compiling and running the program the Serial Terminal displays - 'Echo

Output:'. As the characters are typed in, they will be displayed on the terminal.

2.The inference is that the program in the Tiva LaunchPad is doing the echo

operation.

VIVA:

1. What is UART and how does it work?

2. Which is the most commonly used UART?

3. What is baud rate in serial communication?

4. What is a framing error on serial port?

https://learn.sparkfun.com/tutorials/serial-communication/all




STUDENT OBSERVATION MANUALvemu.org/uploads/lecture_notes/23_01_2020_1549251665.pdf · PART B: Embedded Systems (List of Experiments) (For Laboratory Examination-Minimum of Six Experiments)

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