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A Self-Test Approach Using Accumulators as Test Pattern GeneratorsAlbrecht P. StroeleUniversity of Karlsruhe, Institute of Computer Design and Fault ToleranceP. 0. Box 6980, D-76128 Karlsruhe, Germany

Abstract: Configurations of adders an d registers,which ar e available in tnany datapaths, can be utilized togenerate pat tem s and t o compact test responses. This paperunalyzes tlie patiern sequences produced by different typesof accuriiulators and shows that they can achieve similar,fault coverage as pseud o-rand om patterns. Corizpared to filewell-known selftest tnethods that insert test registers, theapproach using accumulators saves the additional gatesthat are needed to iniplenient test registers, and it avoidspecfortnunce degracilition diw to atitiitionnl d e l q x1. Introduction

The basic idea of built-in self-test (BIST) is to generatetest patterns on-chip and also compact the test responsesof the circuit under test (CIJT) on-chip. IJsually testregisters are inserted that are based on linear feedback shiftregisters (e.g. BILBOs [4]) or linear cellular automata [3 ][1, 5 , 61. These test registers can generate pseudo-randomor (pseudo-)exhaustive patterns and perform signatureanalysis. But the benefits of BIST using multimode testregisters have some cost:0 Hardware overhead due to additional gates that arerequired for implementing the test registers0 Performance degradation due to the slower test registercells0 Increased complexity of the test control unit, which hasto control tlie modes of the test registers during testapplicationThc datapaths o f processors and in particular circuits fordigital signal processing often contain accumulatorscomposed of binary adders or arithmetic logic unils andregisters. If accumulators arc used in place of test registers,tire disadvantages mentioned above do not occur since theaccumulators do not have to be reconligured for specialtest modes. Recently it has been shown that accumulatorscan hc crnploycd to compact t e s t responses [ 7 , 81. Thispaper studies tlieir properties regarding pattern generation.Figurc I shows the basic configuration. The input v isadded to the contents of the register, s(t). The sum givesthe next state, s(t+l)= s(t)+v. So with each clock pulse, anew pattern s is generated and applied to the circuit undertest. s(t) denotes the decimal cncoding of the k-bit patternat time t, ( sk . l ( t ) , sk.2(t), ..., so(t)) is the correspondingbinary vector. The input v is kept constant. In thefollowing we assume v # O since otherwise o n l y (m epattern could be generated. The number of states o f the

0-7803-2570-2/95 $4.00 01995 IEEE

accumulator is 2k. SO after 2k steps at the latest, states arerepeated and the pattem sequence gets periodic.input v l k

accumulator(state s)

Figitre 1:Definition: The period qf the pattern sequence s(t),s ( t+ l ) , ... is the smallest integer p with s(t+p) =s(t) forall t > O . Th e period qf the bit sequence si(t), si(t+l), ...is the smallest integer pi with si(t+pi) =si(t) for all t>O.Generally, the periods of the bit sequenc es can differfrom one another and from the period of the patternsequence.If an accumulator generates a pattem sequence that hassimilar characteristics as those observed at the outputs of aBILBO-like test register, we can expect similar faultdetection capabilities. It is well-known that a k-bit test

register with a primitive characteristic polynomial - an dthese are preferred - can generate all possible pattems a partfroin the all zero pattern. The bit sequences generated ineach o f the k test register cells also have period 2k-l . nthis paper we are looking for accumulators that havecomparab le features regarding paltern generation but avoidthe disadvantages of BILBO-like test registers.The rest of the paper is organized as follows. Section 2ai d section 3 present an analysis of the pattem sequencesthat are generated by accum ulators with binary adders and1's complement adders, respectively. Section 4 shows ex-perimental results, and section 5 gives som e conclusions.2. Accumula tor With Binary Adder

The binary adder performs addition modulo 2k. (Thecarry-in line of the least significant bit, ci, is set to 0.)Every accumulator state s(t) has exactly one successors ( t+ l ) = ~s( t )+V I mod 2k and one predecessor s(t-1) =Is(() - v ] mod 2k. S o its state transition diagram is com-posed o f disjoint cycles. lh e following theorem show show th e Icngths of rhe cycles depend on the input v.

A c c u m u l a t o r as pat te rn genera to r

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Theorem 1: The state transition diagram of a k-bitaccumulator with a binary adder and constant input vconsists of d =gcd(v, 2k) cycles of length 2k/d each. Thegenerated pattern sequence is s(O), [s(O)+v] mod 2k,is(0)+2v1 mod 2k, ..., [s (o)+(d-l ) .vl mod 2 k , s(o), ...Proof: s(t) = [s(t)+p.v] mod 2k holds if and only if(p.v) mod 2k = 0. Let d = gcd(v, 2k ) be the greatestcommon d ivisor of v and 2k.Then p =2k/d is the sm allestnumber such that 2k is a divisor of pv.For a l l odd input values v , we have d = 1, andirrespective of the initial state s(0), a pattern sequencecontaining all possible patterns is generated.Theorem 2: Let a k-bit accumulator with a binaryadder operate under constant input v. The periods of thegenerated bit sequences s;(t), si(t+l), ... aref o r 0 5 i < b{ li + 1 - h f o r b I i < kwhere b is the number of factors 2 that are contained in v(i.e. v =2h.u, U odd).In ordcr to prove theorcm 2, the sm allest num ber pi hasto be determined such that s and s+pjv agree in bi tposition i for all possible states s. We begin by provingthe following lemma.Lemma 1: If pi is the period of the bit sequenceSi((), si(t+l), ..., then the i+l least significant bits of pivhave value 0, PiV mod 2i+1=0.Proof (by contradiction): Let W i , Wi. 1 , ..., W O bethe least significant bits of piv, and assume that at leastone of these bits is 1.If w i= 1: Fo r s =0 we have si =0, hut s+p,v has a I inbit position i. S o pi cannot be the peritd.If wi =0: Lct j be the most significant bit position inwi,wi-l , ...,WO with value 1. For a state s with

pi :=

~s i=o, s i -1= W j . 1 , ... ( sj+1= W j + l , si=',s j - i = ...=s0=0, the sum s+pjv has value 1 inbit position i, and thus differs from si.

For the sp ecial case of v odd (b=O),,froin piv mod 2i+ 1=0 it follows that the period is pi=2'+ l . For the generalcase, in the least significant b bit positions only zeros areadded and the hit values do not change (pi = @ .To dealwith the remaining k-b bits, we shift them h positions tothe right and consider a (k-h)-hit accumulator underconstant input U =~ / 2 ~ .hen we can apply the aboveresult for the special case o f an odd input value. Thiscom pletes the proof of theorem 2.Table 1 (a) show s an ex amp le using initial state s(0)=1and constant input 5 . The period o f the paltein sequenceand of al l the bit seque nces is Z4=16.3. A c c u m u l a t o r W i t h 1's C o m p l e m e n t A d d e r

Fo r BIST, accumulators should he able no? only togenerate pattems but also to compact test respon ses. Theirpcrformance regarding test response compaction can besignificantly improved by a simple modification: Thecarry-out line of the most significant bit position (C O infigure 1) is connected to the carry-in line o f the leastsignificant bit position (ci i n f igure 1 ) [8] . This

corresponds to the "end-around carry" when numbers in 1'scomplement representation are added.Of course, i t is desirable to use the same configurationalso for pattern generation. In an accumulator with 1'scomplem ent adder the next state is computed byif ( s( t )+v 2 2k ) then s(t+l> := s ( t ) + v - 2 k + I ;else s(t+l) := s ( t ) + vor equivalentlys(t+l) = [s(t) - 1 + V I mod (2k-I) + 1I t can be shown that each state s# O has exactly onesuccessor and one predecessor. The state transition diagramconsists of disjoint cycles containing all the states s f O .One additional edge conn ects the state 0 to the state v. Th einitial state s(0) may be the state 0, but after t=O the state0cannever be reached again.Theorem 3: The state transition diagram of a k-bitaccumulator with a 1's complement adder and constantinput v contains d =gcd(v , N) cyc les of length N/d eac h,N =2k-1. The generated patterns are0, v, 1-1 +2 v] mod N +1, ..., [ - 1 + d . v ] mo d N +1,v, ... if s(0) =0,

ands(O), [s(O)- 1 + V I mod N + 1, [s(0) 1+2v] mod N + 1,..., [ d o ) -1 +(d - l ) .v ] mod N +1, s(0), ... else.Proof: The state transition diagram for t>O, whereonly states SE {1, . . ,2k-1}can occur, is isomorphic to thestate transition diagram of an accumulator with a binaryadder mo dulo 2 k-1 , where only states S' E ( 0 , . . . , 2 k - 2 ]occur. The bijective mapping is s'=s-1. IIence theorem 3is proved by replacing Zk by 2k-l i n the proof of theorem1. 8If the accumulator starts with s( 0) =0 and the in utvalue does not have a no ntrivial common d ivisor with 2E-1( d = l ) , hen the accumulator generates a pattern sequencecontaining all possible patterns. In the following, theperiodic behavior of the bit sequence is analysed for themost im portant case, namely d= 1. The bit sequ ence Si(t),

s i ( t + l ) , ... h as y i o d p i if t h e s ta te s and the state[s -I+p,v] mod (2 -1) + 1 agree in hi t position i for allstates SE {I , 2, ..., 2k-11 .Theorem 4: If the state transition diagram of a k-bitaccumulator operating under constant input contains acycle of length 2k-1 , then the generated bit sequencessi(t), s i ( t+ l ) , ... have period pi =2k-1, i =0, 1, ...,k-1 .Theorem 4 can be generalized. I t holds for arbitraryfinite state machines that have k state hits and run througha cycle of 2k-1 different states.

Proof: 'I'he accumulator generates all the pattems outof (0 , 1, ..., 2 k - l ] except one pattern. 1,er that specificpattern be x =(Xk-1, Xk-2, ..., xg). When the bit sequencesi((),si(t+l), ... is observed over one p eriod of the patternsequence, two ca.ses are distinguished:(i) xj=0: The considered hit seyucnce Si(t), si(t+T), ....s;(1 +2 ~-2 ) onsists of 2k-1-X 0"-bits and 2k-1(ii) x i = l : 'l'lie colisiderecl bit scquence si(t), si(I+l), ...,~ ; ( t + 2 ~ - 2 )onsists of 2k-1 0"-bits and 2"l-I

'I 1"-bits.

1"-bits.

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The period p i of the bit sequence si(t), Si(t+l), ... mustdivide the periodof the pattern sequence. S O a=(2'-1)/piis an integer value. Let no (n l) be the number of "0"-bits("1"-bits) in one period of this bit sequence, no+nl =p i .For case ( i) we et a n 0 2k-1-1 and a .nl =Zk-'. Sincegcd (2k-1 -1, 2k-q) =1, th=e value of a must be 1. For case(ii), a=1 is proved in the same way. So the result ispi = (2k-1)/a = 2k-1.Table 1 (b) gives an example using initial state s(O)= 1and constant input 4. The period of the pattern seyuenceand of all the bit sequences is 24-1 =15 .Addition of 1's complement numbers sometimes causesproblems since the carry bit from the most significant bitposition must be added to the least significa nt bit positionduring the same clock cycle. This problem can be solvedby storing the carry bit in a flip-tlop and adding it duringthe next clock cycle (see figure 2). Many datapaths have"add with carry" functions, which can be used for thispurpose. With respect to test response compaction, anaccumulator with stored carry bit perform s equally well asan accumulator with a conventional 1 's complement add er[7]. The rest of this section shows that also with respectto pattern generation these two types of accum ulators havesimilar features.

i n p u t v ICk

Figure 2: Accumula to r wi th s to red cc l r ry bi tTheorem 5: 'The state transition diagram of a k-bit

accumulator with stored carry hit operating under constantinput v, v #2k-1, contains d =gcd (v ,N ) disjoint cycles.and each cycle contains N/ d states, N =2k- l .Proof: The state of an accumulator with stored carrybit is defined by the contents of the register, s, and thecontents of the flip-flop, c. We cornpare its state transitiondiagram STG (states (s,c)) with the state transition dia-gram STG' of an accumulator with l's-complement adder(states s'), both using the same input value v and theinitialization s'(O)=s(O). According to theorem 3, the statetransition diagram STG' has d =gcd (v, N) cycles of lengthN/d. Each cycle of STG' corresponds to n cycle i n STGthat is found by the following mapping of states:

If and only if s ' t { I , , .._, ) , the preceding addition of vproduced an overtlow ( C O = 1).With the accumulator o f fig-ure 2, this overflow docs not lcad to irnmediate addition of1, but it is stored in the Ilip-flop and we have s= s ' -1 , c= 1.In all cases where ove:flow did not occur with the pre-ceding addition, both accurnulators have the sane register

contents and the stored carry bit is 0. As the mapping (*)is injective, the d cycles in S TG resulting from the cyclesin STG' are disjoint. Moreover, it is found that all theother states (s, c) are not included in an y cycle.The cycles include the s ta tes (0,1) , (1,1) , (2,1) ,...,(v- l , l ) , (v+l ,O) , ...,(2k-1,0). A detailed analysis showsthat after at most two clock pulses o ne of these states isreached, irrespective of the initial state. Since (v,O) and(v , l ) are not included in a cycle, they cannot be reachedafter t =1. If v # 2k-1, gcd (v , 2k-1) =1, and the initialstate is chosen from the set {(0,0),(~,0),(v,l),(2~-l,l)},all possible k-bit patterns can b e generated.For th e case of g c d ( ~ , 2 ~ - 1 )1, the bit sequencesS,(t),Si(t+l), .. have period ~ i = 2 ~ - 1 ,=O, 1 ..., -1. Thisfollows immediately from theorem 4. Table 1 (c) shows:an example using initialization (s,c)= 1,O) and constantinput 4. The period of the pattern sequence and of all thehit sequences is 24-1=15 .-ime

012345678910111213141516

-

-oh/e 1: Se q u e n c e s g e n e r a t e d h y d i f f e r e n t 4-hit accumula to rs( a ) h i n a ry a d d i t io n ( i n p u t value 5)( h ) 1's com plem ent at l t li t ion ( inpu t va lue 4)

( c ) add i t ion wi th s to red car ry b i t( i n p u t v a l u e 4, carry hit initiali7,ed to 0)4. Experimental Results

A variety of accumulators was simulated and the pro-duced patterns were applied to the ISCAS'85 benchmarkcircuits [2]. lisin g fault sim ulation , the test lengths weredetermined that are necessary to achievc 10 0% coverage ofa l l t e x t a b l c s t u c k a t fau l t s . Fig. 7 shows typical examples.

circuit c432

#patterns0 500 1000 2000

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circuit c499

#pat ternsI I I I c0 50 0 1000

Detec t ion of t e s t a b l e s t u c k - a t f a u l t s( A I : A c c u m u l a t o r w i t h b i n a r y a d d e r,A2: A c c u m u l a t o r with 1'sc o m p l e m e n t a d d e r )Accum ulators with binary a dders and accum ulators with1's comp lement adders and for comp arison also linear feed-back shift registers with primitive characteristic polyno-mials were employed as pattem generators. For each typeof pattern gen erator, 4 different input values v or 4 differ-ent primitive p olynomials, respectively, were investigated,and for each of these configurations 10 initial states s(0)were tried. The input values were chosen randomly out ofthe set of input value s that lead lo a maximal length cycle

in the state transition diagram (i.e. d= 1). The initial stateswere the all-1 state and 9 other states that were chosenrandomly with the restriction that not more than 4consecutive bits should have the same value. Thisrestriction prevents that a larger part of the accumulatorbehaves like a binary counter where the more significantbits change very rarely.Altogether 40 experimen ts were conducted for each typeof pattem gen erator and for each of the considered circuits.Then the average test length and the shortest test length ofeach set of 40 experim ents were determined. Table 2 andtable 3 list the results for the four circuits that are wellsuited for random resting, c432, c499, ~ 1 9 0 8 ,nd c6288.These data show that in order to achieve 100% stuck-atfault coverage accumu lator generated p attems require abou tthe sam e test length as pseudo-random pattems generatedby LFSRs with primitive characteristic polynom ials.

Figure 3:

Tuhle 2: T e s t l e n g t h t o a c h i e v e 100 5% f a u l t c o v e r a g e ,a v e r a g e of each set of 40 e x p e r i m e n t sI ircuit IILFSKS (prim. I accumulators I accumulators I

Table .?; T e s t l e n g t h to a c h i e v e 1 0 0 7~ a u l t c o v e r a g e ,hest resu l t of e a c h s e t of 40 e x p e r i m e n t s

In addition, it was investigated how the choice of theinput value (o r characteristic polynomial) and the choice ofthe initial state influen ce the required test length. For eachinput value, the test lengths achieved with the 10 initialstates were comp ared. They differed by a factor between 2and more than 10, almost independent of the type of thepattern generator. Then the best initial state was deter-mined for each input value. The test lengths correspondingto th e 4 input values combined with their best initialstates differed by a factor ranging between 1.5 and 2.5,irrespective of the type of the pattern generator. Thisindicates that the imp act of the initial state is much m oreimportant than the impact of the input value (or character-istic polynomial) as long as the maximal length cycle inthe state transition diagram is guaranteed. To reduce therequired test leng th, different initial stztes should be tried.5. Conclusions

This paper investigated pattern gencration usingaccumulators with binary adders, accumulators with 1'scomp lement adders , and accu mulators with stored carry bit.For many different input values these accumulators cangenerate a sequence of all possible pattems. Furthermore, ak-bit accum ulator with 1's complem ent adder and also a k-bit accumulator with stored carry bit can generate bitsequences that all have period 2k- l . Thus the periodicbehavior of these accum ulators is the same as that of a k-bit linear feedback shift register (LFSR ) with a primitivecharacteristic polynomial. The results have shown thataccum ulator generated patterns can achieve about the samefault coverag e as pseudo-random pattems and require aboutthe scme est lengths.Since these accum ulators can also be used as testresponse com pactors, a com plete self-test approach basedon accum ulators is feasible. As in many d atapaths addersand registers are available, no o r only few additional testregisters are needed . So the test hardw xe overhead is verysmall. Moreover, using accumulators does not introduceadditional delays and does not lead to performancedegndation.6. References

pp. 56-68[ I ] M. S . Ahatiir, M. A. Breuer: " A Knowledge-Based System fo rDesigning Testahle VI31 Chips", IEEE DesignkTest, Aug. 1985,[Zj F. Brglez, 1. Fujiwara: "A neutral nrtlist of 10 coitibinationalbenchniark circuits and a target translator in FORTRAN", Int.Syniposiuni on Circuits and Systems, 1985131 P. D. Hortensius et al.: "Cellular Automata-Based PseudorantlornNuriibcr Generators for Built-In Self-Test", IEEE Transactions onCAD, Aug. 1989, pp . 842-859141 B. Koeneniann, J . Mucha. G. Zwielioff: "Built-In Logic BlockObservation Techniques". Test Conf.. Cherry Hill, 1979, pp. 37-41[ 5 ] A. Krasniewski, A. Albicki: "Autoiliatic Design of ExhaustivelySelf-Testing Chips with BILBO Modules". int. Test Conference,[6] C. Papacliristou, S.Chiou, H. Harmanani: "A data padi synthesismethod for self-testable designs", Design Automation Conference,

with Rotate Carry Adders", IEEE Trans. CAD, 1993, pp. 531-539[8] J. Rajski, J. Tyszer: "Accumulator-Based Compaction of TestResponses", IEEE Trans. on Computers, 1993, pp. 643-650

198.5,pp. 362-3711991. pp. 378-384J. Ra.iski, J . Tyszer: "Test Response Cornpaction i n Accumulators171

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