Stochastic Physical Synthesis for FPGAs with Pre-routing Interconnect Uncertainty and Process Variation Yan Lin and Lei He EE Department, UCLA http://eda.ee.ucla.edu Partially supported by NSF and UC Micro sponsored by Partially supported by NSF and UC Micro sponsored by Actel Actel
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Stochastic Physical Synthesis for FPGAs with Pre-routing Interconnect Uncertainty and Process Variation Yan Lin and Lei He EE Department, UCLA .
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Stochastic Physical Synthesis for FPGAs with Pre-routing
Interconnect Uncertainty and Process Variation
Yan Lin and Lei HeEE Department, UCLAhttp://eda.ee.ucla.edu
Partially supported by NSF and UC Micro sponsored by ActelPartially supported by NSF and UC Micro sponsored by Actel
Motivation Variations
Pre-routing interconnect uncertainty Process variation
Impact Any near-critical paths statistically timing critical STA ignores near-criticality
Related work for FPGAs Chipwise placement [Cheng, FPL’06] Stochastic placement [Lin, FPL’06] Stochastic routing [Sivaswamy, FPGA’07]
Stochastic physical synthesis and the interaction have not been studied for FPGAs
Deterministic clusterer, placer + stochastic router is a good flow Significant wiring gains and less runtime
Conclusions The timing gain mainly due to clusterer and placer
modeling interconnect uncertainty for clustering considering process variation for placement
The stochastic flow reduces yield loss from 50 to 5pp10K mean delay by 6.2%, standard deviation by 7.5% but takes 3X runtime
Deterministic clusterer, placer + stochastic router reduces wire length by 4.5% also runs slightly faster than deterministic flow
Stochastic clusterer + deterministic P&R reduces yield loss from 50 to 9pp10K mean delay by 5.0%, standard deviation by 6.4% also runs slightly faster than deterministic flow