Stellaris LM3S9B92 Microcontroller Data Sheet (Rev. M)perrotol/LM3S9B92-DataSheet.pdf · 2013. 9. 26. · 16.3.1 Transmit.....831 16.3.2 Receive.....835

Stellaris® LM3S9B92 Microcontroller

DATA SHEET

Copyr ight © 2007-2012Texas Instruments Incorporated

DS-LM3S9B92-11425

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright © 2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas InstrumentsIncorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as theproperty of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standardwarranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

January 20, 20122Texas Instruments-Production Data

Table of ContentsRevision History ............................................................................................................................. 41About This Document .................................................................................................................... 52Audience .............................................................................................................................................. 52About This Manual ................................................................................................................................ 52Related Documents ............................................................................................................................... 52Documentation Conventions .................................................................................................................. 53

1 Architectural Overview .......................................................................................... 551.1 Overview ...................................................................................................................... 551.2 Target Applications ........................................................................................................ 571.3 Features ....................................................................................................................... 571.3.1 ARM Cortex-M3 Processor Core .................................................................................... 571.3.2 On-Chip Memory ........................................................................................................... 591.3.3 External Peripheral Interface ......................................................................................... 601.3.4 Serial Communications Peripherals ................................................................................ 621.3.5 System Integration ........................................................................................................ 681.3.6 Advanced Motion Control ............................................................................................... 721.3.7 Analog .......................................................................................................................... 741.3.8 JTAG and ARM Serial Wire Debug ................................................................................ 761.3.9 Packaging and Temperature .......................................................................................... 771.4 Hardware Details .......................................................................................................... 77

2 The Cortex-M3 Processor ...................................................................................... 782.1 Block Diagram .............................................................................................................. 792.2 Overview ...................................................................................................................... 802.2.1 System-Level Interface .................................................................................................. 802.2.2 Integrated Configurable Debug ...................................................................................... 802.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 812.2.4 Cortex-M3 System Component Details ........................................................................... 812.3 Programming Model ...................................................................................................... 822.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 822.3.2 Stacks .......................................................................................................................... 822.3.3 Register Map ................................................................................................................ 832.3.4 Register Descriptions .................................................................................................... 842.3.5 Exceptions and Interrupts .............................................................................................. 972.3.6 Data Types ................................................................................................................... 972.4 Memory Model .............................................................................................................. 972.4.1 Memory Regions, Types and Attributes ........................................................................... 992.4.2 Memory System Ordering of Memory Accesses ............................................................ 1002.4.3 Behavior of Memory Accesses ..................................................................................... 1002.4.4 Software Ordering of Memory Accesses ....................................................................... 1012.4.5 Bit-Banding ................................................................................................................. 1022.4.6 Data Storage .............................................................................................................. 1042.4.7 Synchronization Primitives ........................................................................................... 1052.5 Exception Model ......................................................................................................... 1062.5.1 Exception States ......................................................................................................... 1072.5.2 Exception Types .......................................................................................................... 107

3January 20, 2012Texas Instruments-Production Data


2.5.3 Exception Handlers ..................................................................................................... 1102.5.4 Vector Table ................................................................................................................ 1102.5.5 Exception Priorities ...................................................................................................... 1112.5.6 Interrupt Priority Grouping ............................................................................................ 1122.5.7 Exception Entry and Return ......................................................................................... 1122.6 Fault Handling ............................................................................................................. 1142.6.1 Fault Types ................................................................................................................. 1152.6.2 Fault Escalation and Hard Faults .................................................................................. 1152.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1162.6.4 Lockup ....................................................................................................................... 1162.7 Power Management .................................................................................................... 1162.7.1 Entering Sleep Modes ................................................................................................. 1172.7.2 Wake Up from Sleep Mode .......................................................................................... 1172.8 Instruction Set Summary .............................................................................................. 118

3 Cortex-M3 Peripherals ......................................................................................... 1213.1 Functional Description ................................................................................................. 1213.1.1 System Timer (SysTick) ............................................................................................... 1213.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1223.1.3 System Control Block (SCB) ........................................................................................ 1243.1.4 Memory Protection Unit (MPU) ..................................................................................... 1243.2 Register Map .............................................................................................................. 1293.3 System Timer (SysTick) Register Descriptions .............................................................. 1313.4 NVIC Register Descriptions .......................................................................................... 1353.5 System Control Block (SCB) Register Descriptions ........................................................ 1483.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 177

4 JTAG Interface ...................................................................................................... 1874.1 Block Diagram ............................................................................................................ 1884.2 Signal Description ....................................................................................................... 1884.3 Functional Description ................................................................................................. 1894.3.1 JTAG Interface Pins ..................................................................................................... 1894.3.2 JTAG TAP Controller ................................................................................................... 1914.3.3 Shift Registers ............................................................................................................ 1914.3.4 Operational Considerations .......................................................................................... 1924.4 Initialization and Configuration ..................................................................................... 1944.5 Register Descriptions .................................................................................................. 1954.5.1 Instruction Register (IR) ............................................................................................... 1954.5.2 Data Registers ............................................................................................................ 197

5 System Control ..................................................................................................... 1995.1 Signal Description ....................................................................................................... 1995.2 Functional Description ................................................................................................. 1995.2.1 Device Identification .................................................................................................... 2005.2.2 Reset Control .............................................................................................................. 2005.2.3 Non-Maskable Interrupt ............................................................................................... 2055.2.4 Power Control ............................................................................................................. 2055.2.5 Clock Control .............................................................................................................. 2065.2.6 System Control ........................................................................................................... 2125.3 Initialization and Configuration ..................................................................................... 2145.4 Register Map .............................................................................................................. 214


Table of Contents

5.5 Register Descriptions .................................................................................................. 216

6 Internal Memory ................................................................................................... 3076.1 Block Diagram ............................................................................................................ 3076.2 Functional Description ................................................................................................. 3076.2.1 SRAM ........................................................................................................................ 3086.2.2 ROM .......................................................................................................................... 3086.2.3 Flash Memory ............................................................................................................. 3106.3 Register Map .............................................................................................................. 3156.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 3166.5 Memory Register Descriptions (System Control Offset) .................................................. 328

7 Micro Direct Memory Access (μDMA) ................................................................ 3447.1 Block Diagram ............................................................................................................ 3457.2 Functional Description ................................................................................................. 3457.2.1 Channel Assignments .................................................................................................. 3467.2.2 Priority ........................................................................................................................ 3477.2.3 Arbitration Size ............................................................................................................ 3477.2.4 Request Types ............................................................................................................ 3477.2.5 Channel Configuration ................................................................................................. 3487.2.6 Transfer Modes ........................................................................................................... 3507.2.7 Transfer Size and Increment ........................................................................................ 3587.2.8 Peripheral Interface ..................................................................................................... 3587.2.9 Software Request ........................................................................................................ 3587.2.10 Interrupts and Errors .................................................................................................... 3597.3 Initialization and Configuration ..................................................................................... 3597.3.1 Module Initialization ..................................................................................................... 3597.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 3597.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 3617.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 3627.3.5 Configuring Channel Assignments ................................................................................ 3657.4 Register Map .............................................................................................................. 3657.5 μDMA Channel Control Structure ................................................................................. 3667.6 μDMA Register Descriptions ........................................................................................ 373

8 General-Purpose Input/Outputs (GPIOs) ........................................................... 4028.1 Signal Description ....................................................................................................... 4028.2 Functional Description ................................................................................................. 4078.2.1 Data Control ............................................................................................................... 4088.2.2 Interrupt Control .......................................................................................................... 4098.2.3 Mode Control .............................................................................................................. 4108.2.4 Commit Control ........................................................................................................... 4108.2.5 Pad Control ................................................................................................................. 4118.2.6 Identification ............................................................................................................... 4118.3 Initialization and Configuration ..................................................................................... 4118.4 Register Map .............................................................................................................. 4128.5 Register Descriptions .................................................................................................. 415

9 External Peripheral Interface (EPI) ..................................................................... 4589.1 EPI Block Diagram ...................................................................................................... 4599.2 Signal Description ....................................................................................................... 460



9.3 Functional Description ................................................................................................. 4629.3.1 Non-Blocking Reads .................................................................................................... 4639.3.2 DMA Operation ........................................................................................................... 4649.4 Initialization and Configuration ..................................................................................... 4649.4.1 SDRAM Mode ............................................................................................................. 4659.4.2 Host Bus Mode ........................................................................................................... 4699.4.3 General-Purpose Mode ............................................................................................... 4809.5 Register Map .............................................................................................................. 4889.6 Register Descriptions .................................................................................................. 489

10 General-Purpose Timers ...................................................................................... 53110.1 Block Diagram ............................................................................................................ 53210.2 Signal Description ....................................................................................................... 53210.3 Functional Description ................................................................................................. 53510.3.1 GPTM Reset Conditions .............................................................................................. 53610.3.2 Timer Modes ............................................................................................................... 53610.3.3 DMA Operation ........................................................................................................... 54210.3.4 Accessing Concatenated Register Values ..................................................................... 54310.4 Initialization and Configuration ..................................................................................... 54310.4.1 One-Shot/Periodic Timer Mode .................................................................................... 54310.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 54410.4.3 Input Edge-Count Mode ............................................................................................... 54410.4.4 Input Edge Timing Mode .............................................................................................. 54510.4.5 PWM Mode ................................................................................................................. 54610.5 Register Map .............................................................................................................. 54610.6 Register Descriptions .................................................................................................. 547

11 Watchdog Timers ................................................................................................. 57811.1 Block Diagram ............................................................................................................ 57911.2 Functional Description ................................................................................................. 57911.2.1 Register Access Timing ............................................................................................... 58011.3 Initialization and Configuration ..................................................................................... 58011.4 Register Map .............................................................................................................. 58011.5 Register Descriptions .................................................................................................. 581

12 Analog-to-Digital Converter (ADC) ..................................................................... 60312.1 Block Diagram ............................................................................................................ 60412.2 Signal Description ....................................................................................................... 60512.3 Functional Description ................................................................................................. 60712.3.1 Sample Sequencers .................................................................................................... 60712.3.2 Module Control ............................................................................................................ 60812.3.3 Hardware Sample Averaging Circuit ............................................................................. 61012.3.4 Analog-to-Digital Converter .......................................................................................... 61112.3.5 Differential Sampling ................................................................................................... 61412.3.6 Internal Temperature Sensor ........................................................................................ 61712.3.7 Digital Comparator Unit ............................................................................................... 61712.4 Initialization and Configuration ..................................................................................... 62212.4.1 Module Initialization ..................................................................................................... 62212.4.2 Sample Sequencer Configuration ................................................................................. 62312.5 Register Map .............................................................................................................. 62312.6 Register Descriptions .................................................................................................. 625


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13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 68313.1 Block Diagram ............................................................................................................ 68413.2 Signal Description ....................................................................................................... 68413.3 Functional Description ................................................................................................. 68613.3.1 Transmit/Receive Logic ............................................................................................... 68713.3.2 Baud-Rate Generation ................................................................................................. 68713.3.3 Data Transmission ...................................................................................................... 68813.3.4 Serial IR (SIR) ............................................................................................................. 68813.3.5 ISO 7816 Support ....................................................................................................... 68913.3.6 Modem Handshake Support ......................................................................................... 69013.3.7 LIN Support ................................................................................................................ 69113.3.8 FIFO Operation ........................................................................................................... 69213.3.9 Interrupts .................................................................................................................... 69313.3.10 Loopback Operation .................................................................................................... 69413.3.11 DMA Operation ........................................................................................................... 69413.4 Initialization and Configuration ..................................................................................... 69413.5 Register Map .............................................................................................................. 69513.6 Register Descriptions .................................................................................................. 697

14 Synchronous Serial Interface (SSI) .................................................................... 74714.1 Block Diagram ............................................................................................................ 74814.2 Signal Description ....................................................................................................... 74814.3 Functional Description ................................................................................................. 74914.3.1 Bit Rate Generation ..................................................................................................... 75014.3.2 FIFO Operation ........................................................................................................... 75014.3.3 Interrupts .................................................................................................................... 75014.3.4 Frame Formats ........................................................................................................... 75114.3.5 DMA Operation ........................................................................................................... 75814.4 Initialization and Configuration ..................................................................................... 75914.5 Register Map .............................................................................................................. 76014.6 Register Descriptions .................................................................................................. 761

15 Inter-Integrated Circuit (I2C) Interface ................................................................ 78915.1 Block Diagram ............................................................................................................ 79015.2 Signal Description ....................................................................................................... 79015.3 Functional Description ................................................................................................. 79115.3.1 I2C Bus Functional Overview ........................................................................................ 79115.3.2 Available Speed Modes ............................................................................................... 79315.3.3 Interrupts .................................................................................................................... 79415.3.4 Loopback Operation .................................................................................................... 79515.3.5 Command Sequence Flow Charts ................................................................................ 79615.4 Initialization and Configuration ..................................................................................... 80315.5 Register Map .............................................................................................................. 80415.6 Register Descriptions (I2C Master) ............................................................................... 80515.7 Register Descriptions (I2C Slave) ................................................................................. 818

16 Inter-Integrated Circuit Sound (I2S) Interface .................................................... 82716.1 Block Diagram ............................................................................................................ 82816.2 Signal Description ....................................................................................................... 82816.3 Functional Description ................................................................................................. 829



16.3.1 Transmit ..................................................................................................................... 83116.3.2 Receive ...................................................................................................................... 83516.4 Initialization and Configuration ..................................................................................... 83716.5 Register Map .............................................................................................................. 83816.6 Register Descriptions .................................................................................................. 839

17 Controller Area Network (CAN) Module ............................................................. 86417.1 Block Diagram ............................................................................................................ 86517.2 Signal Description ....................................................................................................... 86517.3 Functional Description ................................................................................................. 86617.3.1 Initialization ................................................................................................................. 86717.3.2 Operation ................................................................................................................... 86817.3.3 Transmitting Message Objects ..................................................................................... 86917.3.4 Configuring a Transmit Message Object ........................................................................ 86917.3.5 Updating a Transmit Message Object ........................................................................... 87017.3.6 Accepting Received Message Objects .......................................................................... 87117.3.7 Receiving a Data Frame .............................................................................................. 87117.3.8 Receiving a Remote Frame .......................................................................................... 87117.3.9 Receive/Transmit Priority ............................................................................................. 87217.3.10 Configuring a Receive Message Object ........................................................................ 87217.3.11 Handling of Received Message Objects ........................................................................ 87317.3.12 Handling of Interrupts .................................................................................................. 87517.3.13 Test Mode ................................................................................................................... 87617.3.14 Bit Timing Configuration Error Considerations ............................................................... 87817.3.15 Bit Time and Bit Rate ................................................................................................... 87817.3.16 Calculating the Bit Timing Parameters .......................................................................... 88017.4 Register Map .............................................................................................................. 88317.5 CAN Register Descriptions .......................................................................................... 884

18 Ethernet Controller .............................................................................................. 91518.1 Block Diagram ............................................................................................................ 91618.2 Signal Description ....................................................................................................... 91718.3 Functional Description ................................................................................................. 91818.3.1 MAC Operation ........................................................................................................... 91818.3.2 Internal MII Operation .................................................................................................. 92118.3.3 PHY Operation ............................................................................................................ 92118.3.4 Interrupts .................................................................................................................... 92418.3.5 DMA Operation ........................................................................................................... 92418.4 Initialization and Configuration ..................................................................................... 92518.4.1 Hardware Configuration ............................................................................................... 92518.4.2 Software Configuration ................................................................................................ 92618.5 Register Map .............................................................................................................. 92618.6 Ethernet MAC Register Descriptions ............................................................................. 92818.7 MII Management Register Descriptions ......................................................................... 953

19 Universal Serial Bus (USB) Controller ............................................................... 97419.1 Block Diagram ............................................................................................................ 97519.2 Signal Description ....................................................................................................... 97519.3 Functional Description ................................................................................................. 97719.3.1 Operation as a Device ................................................................................................. 97719.3.2 Operation as a Host .................................................................................................... 982


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19.3.3 OTG Mode .................................................................................................................. 98619.3.4 DMA Operation ........................................................................................................... 98819.4 Initialization and Configuration ..................................................................................... 98919.4.1 Pin Configuration ......................................................................................................... 98919.4.2 Endpoint Configuration ................................................................................................ 98919.5 Register Map .............................................................................................................. 99019.6 Register Descriptions ................................................................................................. 1001

20 Analog Comparators .......................................................................................... 111320.1 Block Diagram ........................................................................................................... 111420.2 Signal Description ..................................................................................................... 111420.3 Functional Description ............................................................................................... 111520.3.1 Internal Reference Programming ................................................................................ 111620.4 Initialization and Configuration .................................................................................... 111720.5 Register Map ............................................................................................................ 111820.6 Register Descriptions ................................................................................................. 1119

21 Pulse Width Modulator (PWM) .......................................................................... 112721.1 Block Diagram ........................................................................................................... 112821.2 Signal Description ..................................................................................................... 112921.3 Functional Description ............................................................................................... 113221.3.1 PWM Timer ............................................................................................................... 113221.3.2 PWM Comparators .................................................................................................... 113221.3.3 PWM Signal Generator .............................................................................................. 113421.3.4 Dead-Band Generator ............................................................................................... 113421.3.5 Interrupt/ADC-Trigger Selector ................................................................................... 113521.3.6 Synchronization Methods .......................................................................................... 113521.3.7 Fault Conditions ........................................................................................................ 113621.3.8 Output Control Block .................................................................................................. 113721.4 Initialization and Configuration .................................................................................... 113721.5 Register Map ............................................................................................................ 113821.6 Register Descriptions ................................................................................................. 1141

22 Quadrature Encoder Interface (QEI) ................................................................. 120422.1 Block Diagram ........................................................................................................... 120422.2 Signal Description ..................................................................................................... 120522.3 Functional Description ............................................................................................... 120622.4 Initialization and Configuration .................................................................................... 120822.5 Register Map ............................................................................................................ 120922.6 Register Descriptions ................................................................................................. 1210

23 Pin Diagram ........................................................................................................ 122724 Signal Tables ...................................................................................................... 122924.1 100-Pin LQFP Package Pin Tables ............................................................................. 123024.2 108-Ball BGA Package Pin Tables .............................................................................. 126724.3 Connections for Unused Signals ................................................................................. 1305

25 Operating Characteristics ................................................................................. 130726 Electrical Characteristics .................................................................................. 130826.1 Maximum Ratings ...................................................................................................... 130826.2 Recommended Operating Conditions ......................................................................... 130826.3 Load Conditions ........................................................................................................ 1309



26.4 JTAG and Boundary Scan .......................................................................................... 130926.5 Power and Brown-Out ............................................................................................... 131126.6 Reset ........................................................................................................................ 131226.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 131326.8 Clocks ...................................................................................................................... 131326.8.1 PLL Specifications ..................................................................................................... 131326.8.2 PIOSC Specifications ................................................................................................ 131426.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 131426.8.4 Main Oscillator Specifications ..................................................................................... 131526.8.5 System Clock Specification with ADC Operation .......................................................... 131626.8.6 System Clock Specification with USB Operation .......................................................... 131626.9 Sleep Modes ............................................................................................................. 131626.10 Flash Memory ........................................................................................................... 131626.11 Input/Output Characteristics ....................................................................................... 131726.12 External Peripheral Interface (EPI) .............................................................................. 131726.13 Analog-to-Digital Converter (ADC) .............................................................................. 132326.14 Synchronous Serial Interface (SSI) ............................................................................. 132426.15 Inter-Integrated Circuit (I2C) Interface ......................................................................... 132626.16 Inter-Integrated Circuit Sound (I2S) Interface ............................................................... 132726.17 Ethernet Controller .................................................................................................... 132826.18 Universal Serial Bus (USB) Controller ......................................................................... 133126.19 Analog Comparator ................................................................................................... 133126.20 Current Consumption ................................................................................................. 133226.20.1 Nominal Power Consumption ..................................................................................... 133226.20.2 Maximum Current Consumption ................................................................................. 1332

A Register Quick Reference ................................................................................. 1334B Ordering and Contact Information ................................................................... 1387B.1 Ordering Information .................................................................................................. 1387B.2 Part Markings ............................................................................................................ 1387B.3 Kits ........................................................................................................................... 1388B.4 Support Information ................................................................................................... 1388

C Package Information .......................................................................................... 1389C.1 100-Pin LQFP Package ............................................................................................. 1389C.1.1 Package Dimensions ................................................................................................. 1389C.1.2 Tray Dimensions ....................................................................................................... 1391C.1.3 Tape and Reel Dimensions ........................................................................................ 1391C.2 108-Ball BGA Package .............................................................................................. 1393C.2.1 Package Dimensions ................................................................................................. 1393C.2.2 Tray Dimensions ....................................................................................................... 1395C.2.3 Tape and Reel Dimensions ........................................................................................ 1396


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List of FiguresFigure 1-1. Stellaris LM3S9B92 Microcontroller High-Level Block Diagram ............................... 56Figure 2-1. CPU Block Diagram ............................................................................................. 80Figure 2-2. TPIU Block Diagram ............................................................................................ 81Figure 2-3. Cortex-M3 Register Set ........................................................................................ 83Figure 2-4. Bit-Band Mapping .............................................................................................. 104Figure 2-5. Data Storage ..................................................................................................... 105Figure 2-6. Vector Table ...................................................................................................... 111Figure 2-7. Exception Stack Frame ...................................................................................... 113Figure 3-1. SRD Use Example ............................................................................................. 127Figure 4-1. JTAG Module Block Diagram .............................................................................. 188Figure 4-2. Test Access Port State Machine ......................................................................... 191Figure 4-3. IDCODE Register Format ................................................................................... 197Figure 4-4. BYPASS Register Format ................................................................................... 197Figure 4-5. Boundary Scan Register Format ......................................................................... 198Figure 5-1. Basic RST Configuration .................................................................................... 202Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 202Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 203Figure 5-4. Power Architecture ............................................................................................ 206Figure 5-5. Main Clock Tree ................................................................................................ 208Figure 6-1. Internal Memory Block Diagram .......................................................................... 307Figure 7-1. μDMA Block Diagram ......................................................................................... 345Figure 7-2. Example of Ping-Pong μDMA Transaction ........................................................... 351Figure 7-3. Memory Scatter-Gather, Setup and Configuration ................................................ 353Figure 7-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 354Figure 7-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 356Figure 7-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 357Figure 8-1. Digital I/O Pads ................................................................................................. 407Figure 8-2. Analog/Digital I/O Pads ...................................................................................... 408Figure 8-3. GPIODATA Write Example ................................................................................. 409Figure 8-4. GPIODATA Read Example ................................................................................. 409Figure 9-1. EPI Block Diagram ............................................................................................. 460Figure 9-2. SDRAM Non-Blocking Read Cycle ...................................................................... 468Figure 9-3. SDRAM Normal Read Cycle ............................................................................... 468Figure 9-4. SDRAM Write Cycle ........................................................................................... 469Figure 9-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 475Figure 9-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 477Figure 9-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 478Figure 9-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 478Figure 9-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual

CSn .................................................................................................................. 479Figure 9-10. Continuous Read Mode Accesses ...................................................................... 479Figure 9-11. Write Followed by Read to External FIFO ............................................................ 480Figure 9-12. Two-Entry FIFO ................................................................................................. 480Figure 9-13. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 484



Figure 9-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,WRCYC=1 ........................................................................................................ 484

Figure 9-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 485Figure 9-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 485Figure 9-17. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 485Figure 9-18. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 486Figure 9-19. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 486Figure 9-20. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 486Figure 9-21. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 486Figure 9-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 487Figure 9-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 488Figure 9-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 488Figure 10-1. GPTM Module Block Diagram ............................................................................ 532Figure 10-2. Timer Daisy Chain ............................................................................................. 538Figure 10-3. Input Edge-Count Mode Example ....................................................................... 540Figure 10-4. 16-Bit Input Edge-Time Mode Example ............................................................... 541Figure 10-5. 16-Bit PWM Mode Example ................................................................................ 542Figure 11-1. WDT Module Block Diagram .............................................................................. 579Figure 12-1. Implementation of Two ADC Blocks .................................................................... 604Figure 12-2. ADC Module Block Diagram ............................................................................... 605Figure 12-3. ADC Sample Phases ......................................................................................... 609Figure 12-4. Doubling the ADC Sample Rate .......................................................................... 610Figure 12-5. Skewed Sampling .............................................................................................. 610Figure 12-6. Sample Averaging Example ............................................................................... 611Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 612Figure 12-8. Internal Voltage Conversion Result ..................................................................... 613Figure 12-9. External Voltage Conversion Result .................................................................... 614Figure 12-10. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 615Figure 12-11. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 616Figure 12-12. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 616Figure 12-13. Internal Temperature Sensor Characteristic ......................................................... 617Figure 12-14. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 620Figure 12-15. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 621Figure 12-16. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 622Figure 13-1. UART Module Block Diagram ............................................................................. 684Figure 13-2. UART Character Frame ..................................................................................... 687Figure 13-3. IrDA Data Modulation ......................................................................................... 689Figure 13-4. LIN Message ..................................................................................................... 691Figure 13-5. LIN Synchronization Field ................................................................................... 692Figure 14-1. SSI Module Block Diagram ................................................................................. 748Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 752Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 752Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 753Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 753Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 754Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 755Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 755Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 756


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Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 757Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 758Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 758Figure 15-1. I2C Block Diagram ............................................................................................. 790Figure 15-2. I2C Bus Configuration ........................................................................................ 791Figure 15-3. START and STOP Conditions ............................................................................. 792Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 792Figure 15-5. R/S Bit in First Byte ............................................................................................ 793Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 793Figure 15-7. Master Single TRANSMIT .................................................................................. 797Figure 15-8. Master Single RECEIVE ..................................................................................... 798Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 799Figure 15-10. Master RECEIVE with Repeated START ............................................................. 800Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated

START .............................................................................................................. 801Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated

START .............................................................................................................. 802Figure 15-13. Slave Command Sequence ................................................................................ 803Figure 16-1. I2S Block Diagram ............................................................................................. 828Figure 16-2. I2S Data Transfer ............................................................................................... 831Figure 16-3. Left-Justified Data Transfer ................................................................................ 831Figure 16-4. Right-Justified Data Transfer .............................................................................. 831Figure 17-1. CAN Controller Block Diagram ............................................................................ 865Figure 17-2. CAN Data/Remote Frame .................................................................................. 867Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 875Figure 17-4. CAN Bit Time .................................................................................................... 879Figure 18-1. Ethernet Controller ............................................................................................. 916Figure 18-2. Ethernet Controller Block Diagram ...................................................................... 916Figure 18-3. Ethernet Frame ................................................................................................. 918Figure 18-4. Interface to an Ethernet Jack .............................................................................. 925Figure 19-1. USB Module Block Diagram ............................................................................... 975Figure 20-1. Analog Comparator Module Block Diagram ....................................................... 1114Figure 20-2. Structure of Comparator Unit ............................................................................ 1116Figure 20-3. Comparator Internal Reference Structure .......................................................... 1116Figure 21-1. PWM Module Diagram ..................................................................................... 1129Figure 21-2. PWM Generator Block Diagram ........................................................................ 1129Figure 21-3. PWM Count-Down Mode .................................................................................. 1133Figure 21-4. PWM Count-Up/Down Mode ............................................................................. 1133Figure 21-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1134Figure 21-6. PWM Dead-Band Generator ............................................................................. 1135Figure 22-1. QEI Block Diagram .......................................................................................... 1205Figure 22-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1207Figure 23-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1227Figure 23-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1228Figure 26-1. Load Conditions ............................................................................................... 1309Figure 26-2. JTAG Test Clock Input Timing ........................................................................... 1310Figure 26-3. JTAG Test Access Port (TAP) Timing ................................................................ 1310Figure 26-4. Power-On Reset Timing ................................................................................... 1311



Figure 26-5. Brown-Out Reset Timing .................................................................................. 1311Figure 26-6. Power-On Reset and Voltage Parameters ......................................................... 1312Figure 26-7. External Reset Timing (RST) ............................................................................ 1312Figure 26-8. Software Reset Timing ..................................................................................... 1312Figure 26-9. Watchdog Reset Timing ................................................................................... 1313Figure 26-10. MOSC Failure Reset Timing ............................................................................. 1313Figure 26-11. SDRAM Initialization and Load Mode Register Timing ........................................ 1318Figure 26-12. SDRAM Read Timing ....................................................................................... 1318Figure 26-13. SDRAM Write Timing ....................................................................................... 1319Figure 26-14. Host-Bus 8/16 Mode Read Timing ..................................................................... 1320Figure 26-15. Host-Bus 8/16 Mode Write Timing ..................................................................... 1320Figure 26-16. Host-Bus 8/16 Mode Muxed Read Timing .......................................................... 1321Figure 26-17. Host-Bus 8/16 Mode Muxed Write Timing .......................................................... 1321Figure 26-18. General-Purpose Mode Read and Write Timing ................................................. 1322Figure 26-19. General-Purpose Mode iRDY Timing ................................................................. 1322Figure 26-20. ADC Input Equivalency Diagram ....................................................................... 1324Figure 26-21. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1325Figure 26-22. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1325Figure 26-23. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1326Figure 26-24. I2C Timing ....................................................................................................... 1327Figure 26-25. I2S Master Mode Transmit Timing ..................................................................... 1327Figure 26-26. I2S Master Mode Receive Timing ...................................................................... 1328Figure 26-27. I2S Slave Mode Transmit Timing ....................................................................... 1328Figure 26-28. I2S Slave Mode Receive Timing ........................................................................ 1328Figure 26-29. External XTLP Oscillator Characteristics ........................................................... 1331Figure C-1. Stellaris LM3S9B92 100-Pin LQFP Package Dimensions ................................... 1389Figure C-2. 100-Pin LQFP Tray Dimensions ........................................................................ 1391Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1392Figure C-4. Stellaris LM3S9B92 108-Ball BGA Package Dimensions .................................... 1393Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1395Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1396


Table of Contents

List of TablesTable 1. Revision History .................................................................................................. 41Table 2. Documentation Conventions ................................................................................ 53Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 83Table 2-2. Processor Register Map ....................................................................................... 84Table 2-3. PSR Register Combinations ................................................................................. 89Table 2-4. Memory Map ....................................................................................................... 97Table 2-5. Memory Access Behavior ................................................................................... 100Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 102Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 102Table 2-8. Exception Types ................................................................................................ 108Table 2-9. Interrupts .......................................................................................................... 109Table 2-10. Exception Return Behavior ................................................................................. 114Table 2-11. Faults ............................................................................................................... 115Table 2-12. Fault Status and Fault Address Registers ............................................................ 116Table 2-13. Cortex-M3 Instruction Summary ......................................................................... 118Table 3-1. Core Peripheral Register Regions ....................................................................... 121Table 3-2. Memory Attributes Summary .............................................................................. 124Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 127Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 128Table 3-5. AP Bit Field Encoding ........................................................................................ 128Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 128Table 3-7. Peripherals Register Map ................................................................................... 129Table 3-8. Interrupt Priority Levels ...................................................................................... 156Table 3-9. Example SIZE Field Values ................................................................................ 184Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 188Table 4-2. JTAG_SWD_SWO Signals (108BGA) ................................................................. 189Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 190Table 4-4. JTAG Instruction Register Commands ................................................................. 195Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 199Table 5-2. System Control & Clocks Signals (108BGA) ........................................................ 199Table 5-3. Reset Sources ................................................................................................... 200Table 5-4. Clock Source Options ........................................................................................ 207Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 209Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 209Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 210Table 5-8. System Control Register Map ............................................................................. 214Table 5-9. RCC2 Fields that Override RCC Fields ............................................................... 236Table 6-1. Flash Memory Protection Policy Combinations .................................................... 311Table 6-2. User-Programmable Flash Memory Resident Registers ....................................... 315Table 6-3. Flash Register Map ............................................................................................ 315Table 7-1. μDMA Channel Assignments .............................................................................. 346Table 7-2. Request Type Support ....................................................................................... 348Table 7-3. Control Structure Memory Map ........................................................................... 349Table 7-4. Channel Control Structure .................................................................................. 349Table 7-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 358Table 7-6. μDMA Interrupt Assignments .............................................................................. 359



Table 7-7. Channel Control Structure Offsets for Channel 30 ................................................ 360Table 7-8. Channel Control Word Configuration for Memory Transfer Example ...................... 360Table 7-9. Channel Control Structure Offsets for Channel 7 .................................................. 361Table 7-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 362Table 7-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 363Table 7-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 364Table 7-13. μDMA Register Map .......................................................................................... 365Table 8-1. GPIO Pins With Non-Zero Reset Values .............................................................. 403Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 403Table 8-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 405Table 8-4. GPIO Pad Configuration Examples ..................................................................... 411Table 8-5. GPIO Interrupt Configuration Example ................................................................ 412Table 8-6. GPIO Pins With Non-Zero Reset Values .............................................................. 413Table 8-7. GPIO Register Map ........................................................................................... 413Table 8-8. GPIO Pins With Non-Zero Reset Values .............................................................. 426Table 8-9. GPIO Pins With Non-Zero Reset Values .............................................................. 432Table 8-10. GPIO Pins With Non-Zero Reset Values .............................................................. 434Table 8-11. GPIO Pins With Non-Zero Reset Values .............................................................. 437Table 8-12. GPIO Pins With Non-Zero Reset Values .............................................................. 444Table 9-1. External Peripheral Interface Signals (100LQFP) ................................................. 460Table 9-2. External Peripheral Interface Signals (108BGA) ................................................... 461Table 9-3. EPI SDRAM Signal Connections ......................................................................... 466Table 9-4. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 470Table 9-5. EPI Host-Bus 8 Signal Connections .................................................................... 471Table 9-6. EPI Host-Bus 16 Signal Connections .................................................................. 473Table 9-7. EPI General Purpose Signal Connections ........................................................... 482Table 9-8. External Peripheral Interface (EPI) Register Map ................................................. 488Table 10-1. Available CCP Pins ............................................................................................ 532Table 10-2. General-Purpose Timers Signals (100LQFP) ....................................................... 533Table 10-3. General-Purpose Timers Signals (108BGA) ......................................................... 534Table 10-4. General-Purpose Timer Capabilities .................................................................... 535Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 536Table 10-6. 16-Bit Timer With Prescaler Configurations ......................................................... 537Table 10-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 538Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 539Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 540Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 541Table 10-11. Timers Register Map .......................................................................................... 546Table 11-1. Watchdog Timers Register Map .......................................................................... 581Table 12-1. ADC Signals (100LQFP) .................................................................................... 605Table 12-2. ADC Signals (108BGA) ...................................................................................... 606Table 12-3. Samples and FIFO Depth of Sequencers ............................................................ 607Table 12-4. Differential Sampling Pairs ................................................................................. 614Table 12-5. ADC Register Map ............................................................................................. 623Table 13-1. UART Signals (100LQFP) .................................................................................. 685Table 13-2. UART Signals (108BGA) .................................................................................... 685Table 13-3. Flow Control Mode ............................................................................................. 691


Table of Contents

Table 13-4. UART Register Map ........................................................................................... 696Table 14-1. SSI Signals (100LQFP) ...................................................................................... 749Table 14-2. SSI Signals (108BGA) ........................................................................................ 749Table 14-3. SSI Register Map .............................................................................................. 760Table 15-1. I2C Signals (100LQFP) ...................................................................................... 790Table 15-2. I2C Signals (108BGA) ........................................................................................ 790Table 15-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 794Table 15-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 804Table 15-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 810Table 16-1. I2S Signals (100LQFP) ...................................................................................... 829Table 16-2. I2S Signals (108BGA) ........................................................................................ 829Table 16-3. I2S Transmit FIFO Interface ................................................................................ 832Table 16-4. Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 833Table 16-5. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 833Table 16-6. Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 834Table 16-7. Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 834Table 16-8. I2S Receive FIFO Interface ................................................................................. 836Table 16-9. Audio Formats Configuration .............................................................................. 838Table 16-10. Inter-Integrated Circuit Sound (I2S) Interface Register Map ................................... 839Table 17-1. Controller Area Network Signals (100LQFP) ........................................................ 866Table 17-2. Controller Area Network Signals (108BGA) ......................................................... 866Table 17-3. Message Object Configurations .......................................................................... 872Table 17-4. CAN Protocol Ranges ........................................................................................ 879Table 17-5. CANBIT Register Values .................................................................................... 879Table 17-6. CAN Register Map ............................................................................................. 883Table 18-1. Ethernet Signals (100LQFP) ............................................................................... 917Table 18-2. Ethernet Signals (108BGA) ................................................................................ 917Table 18-3. TX & RX FIFO Organization ............................................................................... 920Table 18-4. Ethernet Register Map ....................................................................................... 927Table 19-1. USB Signals (100LQFP) .................................................................................... 975Table 19-2. USB Signals (108BGA) ...................................................................................... 976Table 19-3. Remainder (MAXLOAD/4) .................................................................................. 988Table 19-4. Actual Bytes Read ............................................................................................. 988Table 19-5. Packet Sizes That Clear RXRDY ........................................................................ 988Table 19-6. Universal Serial Bus (USB) Controller Register Map ............................................ 990Table 20-1. Analog Comparators Signals (100LQFP) ........................................................... 1114Table 20-2. Analog Comparators Signals (108BGA) ............................................................. 1115Table 20-3. Internal Reference Voltage and ACREFCTL Field Values ................................... 1117Table 20-4. Analog Comparators Register Map ................................................................... 1118Table 21-1. PWM Signals (100LQFP) ................................................................................. 1130Table 21-2. PWM Signals (108BGA) ................................................................................... 1131Table 21-3. PWM Register Map .......................................................................................... 1138Table 22-1. QEI Signals (100LQFP) .................................................................................... 1205Table 22-2. QEI Signals (108BGA) ..................................................................................... 1206Table 22-3. QEI Register Map ............................................................................................ 1209Table 24-1. GPIO Pins With Default Alternate Functions ...................................................... 1229Table 24-2. Signals by Pin Number ..................................................................................... 1230Table 24-3. Signals by Signal Name ................................................................................... 1242



Table 24-4. Signals by Function, Except for GPIO ............................................................... 1252Table 24-5. GPIO Pins and Alternate Functions ................................................................... 1261Table 24-6. Possible Pin Assignments for Alternate Functions .............................................. 1264Table 24-7. Signals by Pin Number ..................................................................................... 1267Table 24-8. Signals by Signal Name ................................................................................... 1279Table 24-9. Signals by Function, Except for GPIO ............................................................... 1290Table 24-10. GPIO Pins and Alternate Functions ................................................................... 1299Table 24-11. Possible Pin Assignments for Alternate Functions .............................................. 1302Table 24-12. Connections for Unused Signals (100-Pin LQFP) ............................................... 1305Table 24-13. Connections for Unused Signals (108-Ball BGA) ................................................ 1306Table 25-1. Temperature Characteristics ............................................................................. 1307Table 25-2. Thermal Characteristics ................................................................................... 1307Table 25-3. ESD Absolute Maximum Ratings ...................................................................... 1307Table 26-1. Maximum Ratings ............................................................................................ 1308Table 26-2. Recommended DC Operating Conditions .......................................................... 1308Table 26-3. JTAG Characteristics ....................................................................................... 1309Table 26-4. Power Characteristics ...................................................................................... 1311Table 26-5. Reset Characteristics ....................................................................................... 1312Table 26-6. LDO Regulator Characteristics ......................................................................... 1313Table 26-7. Phase Locked Loop (PLL) Characteristics ......................................................... 1313Table 26-8. Actual PLL Frequency ...................................................................................... 1314Table 26-9. PIOSC Clock Characteristics ............................................................................ 1314Table 26-10. 30-kHz Clock Characteristics ............................................................................ 1314Table 26-11. Main Oscillator Clock Characteristics ............................................................