STC4545M-TGR Rev2.0sz-xrz.com/Upload/pro/quancan/52.STC4545M.pdf · VDSS Drain-Source Voltage 30 -30 V VGSS Gate-Source Voltage ±20 ±20 V TA=25°C 6.8 -6.5 ID Continuous Drain Current,
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P-Channel -30V / -6.5A, RDS(ON) =38mΩ(typ.)@VGS =-10V -30V / -5.0A, RDS(ON) =54mΩ(typ.)@VGS =-4.5V Super high density cell design for extremely low
RDS(ON) Fast switching performance.
APPLICATIONS
Power Management in Notebook Computer, Portable Equipment and Battery Powered
Systems. Hight Frequency Synchronous Buck DC-DC
Converter.
S1 G1
D1 D1
D2 D2
S2 G2
S1
D1
G1
S2
D2
G2
DESCRIPTION
The STC4545 is the N & P-Channel enhancement mode power field effect transistor is produced using high cell density. advanced trench technology to provide excellent RDS(ON). This device iswidely preferred for commercial-industrial surface mount applications and suited for low voltage applications such as DC/DC converters applications. STC4545M-TRG ROHS Compliant This is Halogen Free PIN CONFIGURATION
PART NUMBER INFORMATION
ST C 4545 M - TR G a b c d e f
a : Company name. b : Channel type. c : Product Serial number. d : Package code e : Handling code f : Green product code
Gfs Forward Transconductance VDS =5.0V,ID =6.8A 5.6 S
Source-Drain Doide
VSD Diode Forward VoltageB IS=1.0A,VGS=0V 1.2 V
IS Continuous Source CurrentAD 6.2 A
Dynamic Parameters
Qg (4.5V) Total Gate Charge 4.9 7.0
Qgs Gate-Source Charge 1.5
Qgd Gate-Drain Charge
VDS =15V,VGS =4.5V ID =6.0A
1.86
nC
Ciss Input Capacitance 418 588
Coss Output Capacitance 65
Crss Reverse Transfer Capacitance
VDS =15V,VGS =0V f =1MHz
52
pF
td(on) 2.2
tr Turn-On Time
37
td(off) 12.2
tf Turn-Off Time
VDD=15V, VGEN=10V, RG=3.3Ω,
4.8
nS
Note: A. The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with TA=25°C. B. The data tested by pulsed , pulse width ≦ 300uS , duty cycle ≦ 2% C. The EAS data shows Max. rating . The N Channel test condition is VDD=25V,VGS=10V,L=0.1mH. D. The data is theoretically the same as ID and IDM , in real applications , should be limited by total power dissipation.
The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date
We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet.
V(BR)DSS Drain-Source Breakdown Voltage VGS =0V,ID =250μA -30 V
VGS(th) Gate Threshold Voltage VDS =VGS,ID =250μA -1.0 -2.0 V
IGSS Gate Leakage Current VDS =0V,VGS=±20V ±100 nA
VDS =-24V,VGS =0V TJ =25°C
-1 IDSS Zero Gate Voltage Drain Current
VDS =24V,VGS =0V TJ =55°C
-5 μA
RDS(ON) Drain-source On-ResistanceB VGS =-10V,ID=-6.5 A VGS =-4.5V, ID=-5.0A
38 54
43 60
mΩ
Gfs Forward Transconductance VDS =-5.0V,ID =-7A 6 S
Source-Drain Doide
VSD Diode Forward VoltageB IS=-1.0A,VGS=0V -1.2 V
IS Continuous Source CurrentAD -6.0 A
Dynamic Parameters
Qg (4.5V) Total Gate Charge 6.5 7.2
Qgs Gate-Source Charge 2.8
Qgd Gate-Drain Charge
VDS =-15V,VGS =-4.5V ID =-5.0A
3.2
nC
Ciss Input Capacitance 648 685
Coss Output Capacitance 270
Crss Reverse Transfer Capacitance
VDS =-15V,VGS =0V f =1MHz
105
pF
td(on) 9.0
tr Turn-On Time
16.8
td(off) 22
tf Turn-Off Time
VDD=-15V, VGEN=-10V, RG=3.3Ω,
22.6
nS
Note: A. The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with TA=25°C. B. The data tested by pulsed , pulse width ≦ 300uS , duty cycle ≦ 2% C. The EAS data shows Max. rating . The P Channel test condition is VDD=-25V,VGS=-10V,L=0.1mH. D. The data is theoretically the same as ID and IDM , in real applications , should be limited by total power dissipation.
The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date
We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet.