Station Overview, ARA Trigger & Digitizeridlab/taskAndSchedule/ARA/... · 2011. 2. 26. · ARA Tri g /Di g Electronics - 17-AUG-2010 Station Data Reduction (self-trigger) Raw Signals

Station Overview, ARA Trigger & Digitizer

Gary S. VarnerARA Workshop in Honolulu, 17-AUG-10

• Station geometry• Triggering Overview• Trigger Simulation• Geometrical constraints• Trigger rates• Digitization & • Data rates

Basic Station Geometry -- Initial

ARA Readout Electronics

• Defer general discussion of architecture– Trigger update

– ASIC (IRS) update

Basic Station Geometry -- Revised

ARA Readout Electronics: Triggering

• Maximize local and global sensitivity– Station (few 100ns window) [local]– Array prompt (10’s of us) [global, subthreshold]– High level (100’s of seconds) [global, WF low threshold]

Geometric Considerations

Top View

Consider simple coincidence – as a function of string spacing

Arriving radio front

Single Antenna “singles” rates

• Raw rates

Trigger Rates versus Trigger Threshold

1000

10000

100000

1000000

10000000

3 3.5 4 4.5

Trigger Threshold [sigma noise]

Rat

e [H

z]

Ant singles

Station coincidence

• 5 m “tight” spacing (50ns window)

Trigger Rates versus Trigger Threshold

0.00000010.000001

0.000010.0001

0.0010.01

0.11

10100

100010000

100000

3 3.5 4 4.5

Trigger Threshold [sigma noise]

Rat

e [H

z]

5 of 16

~3.8

Trigger Rates versus String Distance [5 of 16]

0.00000010.000001

0.000010.0001

0.0010.01

0.11

10100

100010000

100000

3 3.5 4 4.5

Trigger Threshold [sigma noise]

Rat

e [H

z]

5m

10m

20m

50m

Station coincidence

~3.9

Additional constraint: causality

Arriving radio front

Use temporal/spatial constraints to reduce incoherent thermal accidentals and reject pathological directions (e.g. surface noise)

Implemented as a 2D sliding window

Simplified coordinatesTop View

Antenna hits quantized with 4ns resolution (250MHz pipeline)

Arriving radio front

++

Side View

16

antennas

N time bins (32 for 128ns)

Example – strong nu signal

Arriving radio front

+

Side View

= 10o

Top View

+

= 45o

A1A2A3A4

Arriving radio front

+

Side View

= -10o

Example – strong signal (e.g. ICL)Top View

+

= 30o

A1A2A3A4

Example – at threshold nu signal

Arriving radio front

+

Side View

= 15o

Top View

+

= 67o

A1A2A3A4

Thermal Noise (~10MHz singles)Top View

++

Side View

Arriving radio front ??

A1A2A3A4

Thermal Noise (~3.x sigma)Top View

Arriving radio front ??

++

Side View

Combinatorics are enormous (C[512,5]=512!/(5!*(512-5)!))

How to implement?

1. Track “road” search? (computationally intensive)2. Step time thread logic3. Fit to plane wave (again CPU heavy)4. Brute force pattern match?

– 2^(16+32) ~ 280 Terabits (very sparse)

Direct logic search – programmable logic good at this

Use “5th” (last hit as seed)

Divide up sky into arrival directionsTop View

Arriving radio front

++

Side View

Many downgoing directions pathological

With quantization, something likeSomething like 5o

Something like 10o

36

361296 equations

Example – at threshold nu signal

Arriving radio front

+

Side View

= 15o

Top View

+

= 67o

Hit search seed

Example – at threshold nu signalHit search seed

Term of equation:

Hit = S1A3[0]*S2A1[1]*S3A4[19]*S4A1[9]*S4A2[10]

Build terms from MC

Since degenerate – some OR termsHit search seed

Reduce Terms of equation:

Hit = S1A3[0]*S2A1[1]*S3A4[19]*S4A1[9]*(S4A2[10]+S4A2[9])

Needs detailed study, but can guesstimate:

16 ant seeds * (16 theta * 8 phi) * 32 patterns ~ 65k terms

Thermal Noise (~3.x sigma)

One way to think of this: can tolerate a larger number of spurious hits Effectively raise coincidence level in the window

Combinatorics are enormous

seed Physically impossible

Hit predicts allowed other times

Trigger Rates versus Effective Threshold [10m]

0.00000010.000001

0.000010.0001

0.0010.01

0.11

10100

100010000

100000

3 3.5 4 4.5

Trigger Threshold [sigma noise]

Rat

e [H

z]

N=5

N=6

N=8

N=10

Station coincidence

~3.3

Looks promising – Lisa to continue…

ARA Readout Electronics: ASIC

• Build on experience with “next generation” ASICs– Deeper storage depth, higher bandwidth?

– Fewer timing alignment constants

Ice Radio Sampler (IRS)

• Actually a fairly generic part– Follow-on evaluation of deeper storage [TARGET, others]

(LABRADOR technology now >half decade old)

– “2 stage” transfer mechanism (reduced calibration)

– No amplifier on the input

– Self-trigger capability (not useful this application)

Collaborative effort with NTU

Ice Radio Sampler (IRS) Specifications

32768 samples/chan (16-32us trig latency)8 channels/IRS ASIC8 Trigger channels

~9 bits resolution (12-bits logging)64 samples convert window (~32-64ns)

1-2 GSa/s1 word (RAM) chan, sample readout

16 us to read all samples100's Hz sustained readout (multibuffer)

• Strictly only 5 channels necessary– 4x antenna, 1x reference channels

– Could interleave for twice depth, or multiple reference channels

IRS Floorplan

8x RF inputs(die upside down)

5.82mm

7.62mm

32k storage cells per channel

(512 groups of 64)

IRS Single Channel

• Storage: 64 x 512 (512 = 8 * 64)

• Sampling: 128 (2x 64 separate transfer lanes

Recording in one set 64, transferring other (“ping-pong”)

• Wilkinson (32x2): 64 conv/channel

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0Sampling Simulation with full parasitic Extraction

0.000

0.500

1.000

1.500

2.000

2.500

3.000

3.500

4.000

4.500

5.000

0 0.5 1 1.5 2 2.5

RCObias [V]

Sam

plin

g R

ate

[GSa

/s]

Extracted

2 stage sampling speed sim

“RCObias” VadjP1,2 = RCObias; VadjN1,2 = VDD-RCObias

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sampling speed measurement

Delta V RCObias Matches expectation, but….

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Measurement via RF sine

Samples much faster, but at higher sampling rateWrite strobe width problem

Measurements by Chih-Ching

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Measurement via RF sine

Analog BW~1GHz

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Input coupling sim (35fF sample)

~1 GHz input signal ABW

Onto chip (flip chip)

Magnitude [dB

]

From IRS Design Review

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Measurement via RF sine

Samples much faster, but at higher sampling rateWrite strobe width problem (know how to fix)

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Linearity Calibration

Comparator bias parameters NOT optimized

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Noise Measurement

mV

~ 2mV

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Need dT calibrations

Conversion/readout speed

• Assume 8 channel (5 needed)

– 5us/ADC cycle (8*64 samples/channel in parallel)

– Transfer at 50MHz (20ns/sample) to FPGA

– 1 conversion cycle ~ 5us (ADC) + 10us (transfer)

– 256ns window (512 samples @ 2GSa/s) = 8 conv cycles

– Total ~ 120us [CF: 1kHz trigger]

– Deadtimeless: 256ns (512 samples) of 16us (32k samples) held – sampling continues on others

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Station Data Reduction (self-trigger)

Raw Signals

16 RF channels@ 1.5By * 2GSa/s

= 48 GBytes/s

Level-1

Antenna

Fullband

A ~MHz (L1L)A ~ 0.1MHz (L1H)

Level-2

Station

5-of-16

100’s kHz (L2L)100’s Hz (L2H)

Level-3Phi

Patternmatch

10-50Hz@ 8kBy/evt

= 60-300kBy/s

Prioritizer?(+compress)

10H

z W

F ev

ents

/link

WF data = 80%HK/trigger timestamp = 10%

High-level req = 10%

ARA Readout Electronics – system discussion

• Uplink bandwidth (~1Mbit/s [wireless])– Multi-tier trigger

– Deeper sampling allows for “array” trigger (subthreshold)

IRS AARDVARC Specifications ?

262144 samples/chan (130us trig latency)1 channel/ASIC-- Trigger channels

~9 bits resolution (12-bits logging)64 samples convert window (32ns)2 GSa/s1 word (RAM) chan, sample readout

<10 us to read all window samples10k Hz sustained readout (multibuffer)

• Avoids issue of channel-channel cross-talk– Slave sampling all ASICs together

– Plenty depth for multi-hit buffering

Summary• Station design evolving

– Build sample station for firmware/cal testbed development

– Initially test with thermals (servo-loop software/firmware)

• Key technology decisions– Tunnel diode versus RF power mon– IRS AARDVARC– Data and fast trigger links

• Proposed architecture– Rather flexible – Optimize as we go

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Back-up slides

Askaryan Radio Array (ARA)

Askaryan Radio Array

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Buffered LABRADOR (BLAB1) ASIC• 10 real bits of dynamic range, single-shot

Measured Noise

1.45mV

1.6V dynamic range

Wilkinson Clock Generation

• Strictly only 5 channels necessary– 4x antenna, 1x reference channels

– Could interleave for twice depth, or multiple reference channels

Wilkinson Recording

Start = start 0.5-8GHz Clock Ripple counter (run as fast as can)

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Wilkinson speed measurement

0.7 GHz 1.4us conversion to 10 bits

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Output Bus Settling Time

~100MHz bus operation should be possible

~8.5ns (10-90%)

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Diode detector Response

σ

Voltageσ

Exponential distribution

<P>

Power:

P/<P>

P/<P>

~7ns integration

Gaussian distribution

Tunnel Diode DetectorLNA

Quad−ridgehorn antenna

Needs amplification!

Tunnel Diode Output Single Channel Trigger Rate

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5

Power/<Power>

Co

un

t R

ate

[M

Hz]

singles

2.3 ~= 3.9 P/<P>

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Log-amp, tunnel diode test

• Can fast log-amps give same SNR as TD trigger?

• Log-amp: V proportional to power

• Uses multi-stage switching to get wide “linear” dynamic range, good stability

• Tunnel-diode: square-law detector with long history in radio astronomomy & physics

– But they are fussy to use!

100ps Pulsegen

0.2‐1.2GHz receiver  Hybrid 

splitter

TekTDS784C scope

AD8318 test boardCoax  tunnel diode detector5ns rise time

trig

CH3

CH2DC block

CH1

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Log-amp vs. tunnel diode SNR test

• Look at Vpeak to Vrms ratio for each device

• Log-amp:– saturation evident– Loss of SNR fidelity below

SNR~3 • TD: square-law behavior evident• Conclusions: log-amps may be

problematic• We really need a true trigger

efficiency test

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Design Basis: Buffered LABRADOR (BLAB1) ASIC

• Single channel• 64k samples deep,

same SCA technique as LAB, no ripple pointer

• Multi-MSa/s to Multi-GSa/s

• 12-64us to form Global trigger

3mm x 2.8mm, TSMC 0.25umArranged as 128 x 512 samples

Simultaneous Write/Read

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BLAB1 Architecture

200ps/sample

FPGA-based TDC: 10-bits in 1us (300ps resolution)

BLAB1 Sampling Speed

200ps/sample Single sample:200/SQRT(12)~ 58ps

In practice, treat each row of 512 samples as independent

Can store 13us at 5GSa/s (before wrapping around)

BLAB1 Analog Bandwidth

• A few fixes (lower power, higher BW)• Multi-channel desired for BLAB2

-3dB ~300MHz

Buffer amps

LAB3 ~ 900MHz

IRS Input Coupling

• Input bandwidth depends on 2x terms– f3dB[input] = [2**Z*Ctot]-1

– f3dB[storage] = [2**Ron*Cstore]-1

Input Coupling versus total input Capacitance

0

0.5

1

1.5

2

2.5

3

3.5

0 500 1000 1500 2000 2500 3000

Total input Capacitance [fF]

Anal

og B

andw

idth

[-3d

B fre

quen

cy]

R_S = 50Ohm

Input coupling versus frequency

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0.1 1 10 100

Frequency [GHz]R

elat

ive

ampl

itude

[dB

]

C=15fF,Ron=1kC=15fF,Ron=5kC=25fF,Ron=1kC=25fF,Ron=5k

IRS Input Coupling

• Role of inductance

Input inductance impedance versus frequency

0

20

40

60

80

100

120

140

160

180

200

0.1 1 10 100

Frequency [GHz]

Impe

danc

e [O

hms]

Bond-wireBump-bond

Input coupling versus frequency

-10

-8

-6

-4

-2

0

2

4

6

8

10

0.1 1 10 100

Frequency [GHz]

Rela

tive

ampl

itude

[dB]

Bond-wireBump-bond

Sample Cell

• Main element is buffer amp (OTA)– Relatively low current (10’s uA) operation possible

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Constraint: kTC Noise

Desire small C for better Input Coupling

Storage Cell

• Diff. Pair as comparator– Only power on selected block

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Another Constraint: Leakage Current

Can Improve? (readout faster)

Need small C for Input Coupling

Sample channel-channel variation ~ fA leakage typically

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Temperature Dependence

0.2%/degree C(servo-loop width)

6GSa/sReference for BLAB1 ASIC

Matches SPICE simulation