State of the SJTAG Initiative

ITC 2006 Meeting

SJTAG Fringe Meeting – October 2006ITC 2006, Santa Clara, CA

State of the SJTAG Initiative

Bradford G. Van Treuren

Chairman


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Outline

Goal of SJTAG Changes in the Core Group Direction of the SJTAG Initiative Connect and Development Survey Activities accomplished since ITC 2005 Discussion


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The Goal of SJTAG

The goal for SJTAG is:

for all variants of XBST and EBST, to define the data contents and formats communicated:

between external Test Manager platforms and internal Embedded Test Controllers,

and

between Embedded Test Controllers and the UUTs they serve

in an open-standard vendor-independent and non-proprietary way.

The goal for SJTAG is:

for all variants of XBST and EBST, to define the data contents and formats communicated:

between external Test Manager platforms and internal Embedded Test Controllers,

and

between Embedded Test Controllers and the UUTs they serve

in an open-standard vendor-independent and non-proprietary way.


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Changes Coming to Core GroupThe Chairman’s Role

Goal: Move initiative to a viable standard Manage the expertise level of the core group Locate new members with relevant expertise for

issues needing to be addressed Fill positions relevant to current needs Inspire sub-teams to work on focused issues Ensure core group stays focused on the topicIdeal core group size needs to be 8 – 10 members

to be effectiveMembers of core group will change over timeSub-groups: important driving force behind SJTAG


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Core Group (September 2006)Change of Leadership – Focused Resources

SJTAG Core GroupBrad Van Treuren, Lucent Technologies – ChairGunnar Carlsson, Ericsson – Vice ChairBen Bennetts, Bennetts Associates – Chair Emeritus???????

Scan Support Device VendorsTest Manager VendorsSystem Company End Users


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Structure of the SJTAG Groups

Extended Group

Review Group

Core Group

Sub-group

Sub-group

Sub-group


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How to join

To join an SJTAG’s extended group: e-mail awareness of future events, access to archived and new documents:

– Send e-mail to Brad Van Treuren, [email protected]

To request to join the review group or core group: complete the survey from today and indicate your desire or email your survey results to Brad Van Treuren if you did not attend.

Presentations available at www.dft.co.uk/SJTAG

mailto:[email protected]


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Targets and Focus (10 Nov 2005 ITC Meeting)

Four main industries– Telecoms– Server/mass storage– Mil/Aero– Automotive

Need ways of describing:– The nature of the Test Manager function: all external, all

embedded, distributed– The access and communication protocols– Test flow control and data requirements for test, debug,

diagnosis, configuration, etc Issues:

– Security Initial focus: telecoms, especially MicroTCA/ATCA but not

exclusively.


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Direction of the SJTAG Initiative

My first attempt at the Scope – Not an official statement

This standard will develop a methodology for access to test, debug, instrument, and emulation features (but not the features themselves) of devices via the IEEE 1149.1 Test Access Port (TAP) for the board and system (multiple board) domains. The elements for this methodology include a description language describing the structure of the IEEE 1149.1 connections in the system; a description of data representation formats for test vectors, diagnostic analysis, and data logging; and software application programming interfaces (APIs) defining command primitives facilitating communications between functional command, control, and data modules of a Test Manager application.

Do not use this draft as fact!


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Direction of the SJTAG Initiative My first attempt at the Purpose – Not an official statement

There is currently no defined, independent standard for this test technology. Each vendor is free in the way of implementing test hardware and software functionality on their boards. Without an independent standard, testability at the system level is reduced or impossible making the test technology in the system less useful for users integrating designs from multiple sources – limiting the ability to use the test technology in other facets of a product’s life cycle beyond manufacturing. In practice, the software used to perform test actions is written in an ad-hoc manner across the industry to access the IEEE 1149.1 features of the devices installed on the various boards of a system. Further, communications between remote and embedded hosts managing the tests applied to the system under test is non-existent or implemented using ad-hoc communications protocols. The purpose of the SJTAG initiative is to provide an extension of the IEEE 1149.1 standard specifically aimed at the configuration, control, management, and representation of the communications required at the hierarchical system and board level to perform operations on the IEEE 1149.1 Test Access Port (TAP) Controller of one or more devices, including multiple core devices, in a uniform way across all system modules.


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Direction of the SJTAG Initiative

Identification of the issues to address– Current issues targeted

• Diagnostics Support• Software Interfaces and API architectures• Test Languages• System Description

Develop a Use Case library to baseline ideas

Scope the work to the purpose


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Core Group Focus

A. G. Lafley, CEO of Proctor & Gamble– Changed the company focus

• From: 10% new product ideas provided by customers• To: 50% new product ideas provided by customers

– Reframed the R&D imperative• From: “Research and Development”• To: “Connect and Development”

– Now P&G is the most innovative packaged-goods marketer

For our core group to be effective, it needs innovative ideas and feedback from the extended group to make SJTAG a success


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Purpose of the Survey

Survey of attendees– Provide feedback to core group members on

the current issues being addressed– Provide information regarding the extended

group members and interest areas in SJTAG– Provide demographics for what sectors of

industry are participating in SJTAG activities– To know who we can address with questions for

a particular audience– To better get to know YOU and YOUR NEEDS


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Directions for the Survey

On provided paper1. Write the number of the question followed by the

answer2. There is no need to write down the question3. Each question following the first set of questions with

have a single letter answer or a short description if your answer falls into the “Other” category

Example:– On Slide: What sector of the business are you affiliated

with?• A. Telecom• B. Mass Storage/Servers• C. Aerospace/Military/Defense• D. Automotive• E. Tool Provider• F. Other (Please state sector)

– I would answer:• A


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Survey Questions

1. What is your name?Please print your name next to 1. on your paper.

2. What is your email address?Please print your email address next to 2. on your

paper.

3. What is the name of your company?Please print the name of your company next to 3. on

your paper.


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Survey Questions

4. What sector of the business are you affiliated with?A. TelecomB. Mass Storage/ServersC. Aerospace/Military/DefenseD. AutomotiveE. Tool ProviderF. Other (Please state sector)


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Survey Questions

5. What is your role with the SJTAG initiative?A. Member of core groupB. Member of extended groupC. Would like to be a member of the core group because I

feel I have significant skills needed by the core group and am willing to sign up for work

D. Would like to be a member of the review groupE. Would like to be a member of the extended groupF. Just visiting and not interested in joining a group


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Survey Questions

6. Have you read the SJTAG White Paper?A. YesB. No

7. An SJTAG Test Manager is:A. An external system for generating and managing testsB. A hardware interface between the microprocessor and

the boundary-scan infrastructure on the boardC. Any combined hardware/software test control systemD. None of the above


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Survey Questions

8. An SJTAG Test Controller is:A. A hardware interface between the

microprocessor and the boundary-scan infrastructure on the board

B. Some or all of the functionality of a runtime-control Test Manager that is built into the UUT

C. Any combined hardware/software test control system

D. None of the above


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Survey Questions

9. A JTAG Protocol Manager (JTAG-PM) is:A. Handshake protocol between a Test Manager

and a Test ControllerB. Any combined hardware/software test control

systemC. A hardware interface between the

microprocessor and the boundary-scan infrastructure on the board

D. None of the above


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Survey Questions

10.The term EBST stands for:A. External Boundary Scan TestB. Embedded Boundary Scan TestC. Embedded Board Self TestD. Enhanced Boundary Scan TestE. None of the above


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Survey Questions

11.Do you implement Boundary-Scan as a test process for your system-level test now?A. YesB. NoC. N/A

12.Do you anticipate the use of Boundary-Scan test at the system-level in the future for your systems?A. YesB. NoC. N/A


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Survey Questions

13.I feel SJTAG is:A. Predominantly a “Software” issue and is NOT a

Hardware and Architectural one. B. Predominantly a “Hardware” issue and is NOT a

Software and Architectural one.C. Predominantly an “Architectural” issue and is NOT a

Hardware and Software one.D. An even mix of Software, Hardware, and Architectural

issues.E. A even mix of Software and Hardware issues and less

of an Architectural issue.F. An even mix of Software and Architectural issues and

less of a Hardware issue.G. An even mix of Hardware and Architectural issues and

less of a Software issue.


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Survey Questions

14.I feel that tests need to be managed (e.g. Test Manager role)A. Entirely within my systemB. Entirely from an external systemC. Primarily from within my system with provisions to add

additional tests on requestD. Primarily from an external system with provisions to run

stand-alone within my system

Tool suppliers: Please indicate what you feel your tools need to support


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Survey Questions

15.What level of diagnostics do you need from an SJTAG based system?A. GO/NO-GOB. Device Pin and Net Failure informationC. Pin Faults (stuck-at, shorts, opens)

16.Diagnostic analysis needs to be performed:A. In the system.B. Real-time from a remote computer.C. Off-line from a remote computer.


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Survey Questions

17.Do you feel emulation support at the system-level is important to you?A. YesB. No

18.Do you feel board-level access to instrumentation inside devices is important?A. YesB. No

19.Do you feel system-level (multiple board) access to instrumentation inside devices is important?A. YesB. No


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Survey Questions

20.The test language I primarily use for Boundary-Scan test application is:A. SVFB. STAPLC. Other (Please state what language that is)


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Activities accomplished since ITC 2005

May 2006 SJTAG Meeting at EBTW2006– Demonstration of an example Test Manager/Test

Controller coordinated test system– Presentation from Test Manager Developer (Adam Ley)– Presentation from Test Controller Developer (Peter

Horwood)– Presentation from Motorola and their perspective of

SJTAG (Stephen Harrison)


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Demo Shown at EBTW May 2006

Test Manager

SVF

STAPL

Translator

Return format

BVR

Full Diagnostics

First level Interchangeability

JTAG ModuleChains

JTAG ModuleChains

GatewayGateway

μPμP

ChainSelectorChain

SelectorJTAG

ControllerJTAG

Controller

OTHER?Firecron Diagnostics

BVR2

ASSET’s ScanWorks

Single boardFirecron’s FSC-1000 ControllerEthernet link

Firecron’s BVR file

SVF


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Activities accomplished since ITC 2005

September 2006 SJTAG at BTW2006– Demonstration of Lucent embedded device pin

and net failure reporting from their Lucent Test Flow Control Language™ (TFCL™)

– Presentation of an SJTAG Interface Perspective– Discussion on diagnostic representation

alternatives– Discuss relationship between IJTAG and

SJTAG


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Layers of the Software for Traditional EBST

Apply a set of vectors Capture a set of responses Compare responses to

known expected values Conditionally apply next set

of vectors based on response result of PASS or FAIL

Fixed set of tests that are applied over and over again

Test Package and TestProgram Flow Control (Ordered

collection of Test Programs)

Test Programs and Test StepFlow Control (Ordered collection

Of Test Steps)

1149.1 Scan Operations(Represents Leaf Functions

as Vector Patterns)

Test Access PortController Operations

Application

Test Steps(Ordered collection of

Scan and PIO Operations)

Test Manager

Test Controller

?


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Interface Boundaries of the Software

Test Package and TestProgram Flow Control (Ordered

collection of Test Programs)

Test Programs and Test StepFlow Control (Ordered collection

Of Test Steps)

1149.1 Scan Operations(Represents Leaf Functions

as Vector Patterns)

Test Access PortController Operations

Application

Test Steps(Ordered collection of

Scan and PIO Operations)

Test Program Interface

Test Step Interface

Scan Interface

TAP Interface

Test Package Interface

SVF

STAPL

Potential Standardization

of Interface


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SJTAG Data PerspectiveInterconnect ATPG Example – Data Representation

Databases store data in tables Related information contained on same row Can we use a table for diagnostic data storage in EBST?

Table: DIAGDATA

Chain Cell Device Cell Device Pin Nets

5 IC3.5 IC3.A5 SIG1

137 IC26.7 IC26.10 WRITE

138 IC26.8 IC26.12 CE

… … … …

Net – Device Pin – Device Cell – Chain Cell


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IJTAG Relationship with SJTAG

IJTAG provides an interface bridge for a device package between embedded instruments and the external JTAG port of the device package

IJTAG is an extension of the IEEE 1149.1 standard aimed at using the TAP to manage the configuration, operation, and collection of data from embedded instrumentation circuitry inside a device package

IJTAG defines the data file format necessary to describe the instrumentation configuration, operation, and data registers that are accessible from the TAP for tools to generate commands for the instrument (i.e., BSDL for instruments)


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SJTAG defines an interface methodology from external or embedded test systems to boards/blades installed in a system

SJTAG defines an interface methodology from embedded test systems on boards to the device packages located locally on the board or daughter boards

SJTAG defines an interface methodology from external or embedded test systems to the device packages located in system (The IJTAG world)


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SJTAG defines the software interfaces between layers of the interface methodology

SJTAG defines the data description formats that describe the JTAG interface definition for each IEEE 1149.1 architectural module in the system


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IJTAG Relationship with IEEE 1500

IJTAG provides a bridge interface from the device package JTAG port to embedded instruments

The 1500 wrapper for core features are considered one of the IJTAG specialized instruments

The IJTAG bridge interfaces directly with the 1500 wrapper as the Test Access Mechanism (TAM) control logic

IJTAG provides the control, operation, and register access to the 1500 wrapper using the 1149.1 TAP interface of the device package

TAPController

IJTAGBridge

Core w/Instrument

1500 Wrapper

TAP Interface


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Your Turn

Q & A

State of the SJTAG Initiative

Documents

test vectors

test hardware

test technology

test manager application

test manager function

effectivemembers of

core groupdirection

test access port tap